November 2020 - coreboot-gerrit

Change in coreboot[master]: volteer: Create voema variant
by David Wu (Code Review) Nov. 2, 2020

Nov. 2, 2020

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47007 ) Change subject: volteer: Create voema variant ...................................................................... volteer: Create voema variant Create the voema variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171755775 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOEMA Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/voema/include/variant/ec.h A src/mainboard/google/volteer/variants/voema/include/variant/gpio.h A src/mainboard/google/volteer/variants/voema/memory/Makefile.inc A src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/voema/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47007/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5..8fd119e 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -94,6 +94,7 @@ default "Voxel" if BOARD_GOOGLE_VOXEL default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI + default "Voema" if BOARD_GOOGLE_VOEMA config MAX_CPUS int @@ -132,6 +133,7 @@ default "voxel" if BOARD_GOOGLE_VOXEL default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI + default "voema" if BOARD_GOOGLE_VOEMA config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..9e48a2f 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -71,3 +71,7 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/ec.h b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt new file mode 100644 index 0000000..f51b3af --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 Gerrit-Change-Number: 47007 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/dood: Add G2Touch touchscreen support
by Kenneth Chan (Code Review) Nov. 2, 2020

Nov. 2, 2020

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46675 ) Change subject: mb/google/octopus/variants/dood: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/dood: Add G2Touch touchscreen support Add G2Touch touchscreen support for dood. BUG=b:171526389 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 --- M src/mainboard/google/octopus/variants/dood/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46675/1 diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index e1f12cf..6e767dd 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -144,6 +144,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 Gerrit-Change-Number: 46675 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Pass smm.ld trought src-to-obj
by Arthur Heymans (Code Review) Nov. 2, 2020

Nov. 2, 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44321 ) Change subject: cpu/x86/smm: Pass smm.ld trought src-to-obj ...................................................................... cpu/x86/smm: Pass smm.ld trought src-to-obj This allows for ccopts symbols and preprocessor to be used inside the smm.ld linker script. Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44321/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a..bbd96c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -16,7 +16,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(filter-out %.ld, $^) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -72,8 +72,10 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +smm-y += smm.ld + +$(obj)/smm/smm: $(obj)/smm/smm.o $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(call src-to-obj,smm,$(src)/cpu/x86/smm/smm.ld) $(obj)/smm/smm.o $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/44321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32 Gerrit-Change-Number: 44321 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/vilboz: Update touch screen power sequence
by EricR Lai (Code Review) Nov. 2, 2020

Nov. 2, 2020

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46929 ) Change subject: mb/google/zork/var/vilboz: Update touch screen power sequence ...................................................................... mb/google/zork/var/vilboz: Update touch screen power sequence Add ELAN touch support and update Goodix settings. BUG=b:157265632 BRANCH=zork TEST=emerge coreboot and check both touch screen are workable. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46929/1 diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a61c027..6156a57 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -103,16 +103,32 @@ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" - register "generic.enable_delay_ms" = "10" + register "generic.enable_delay_ms" = "5" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" - register "generic.reset_off_delay_ms" = "1" - register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "20" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" - register "generic.stop_off_delay_ms" = "1" + register "generic.stop_off_delay_ms" = "2" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" + register "enable_delay_ms" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "2" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 10 on end + end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" -- To view, visit https://review.coreboot.org/c/coreboot/+/46929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec Gerrit-Change-Number: 46929 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp-car: Use the coreboot defined stack
by Arthur Heymans (Code Review) Nov. 2, 2020

Nov. 2, 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37278 ) Change subject: soc/intel/fsp-car: Use the coreboot defined stack ...................................................................... soc/intel/fsp-car: Use the coreboot defined stack The stack needs to be in the coreboot defined region to not collide with other symbols. Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/37278/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index ec43311..d7ef834 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,7 +87,7 @@ jnz .halt_forever /* Setup bootblock stack */ - mov %edx, %esp + movl _ecar_stack, %esp /* coreboot assumes CAR region will be zero */ cld -- To view, visit https://review.coreboot.org/c/coreboot/+/37278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0 Gerrit-Change-Number: 37278 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/bootblock.c: Report the FSP-T output
by Arthur Heymans (Code Review) Nov. 2, 2020

Nov. 2, 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46885 ) Change subject: soc/intel/xeon_sp/bootblock.c: Report the FSP-T output ...................................................................... soc/intel/xeon_sp/bootblock.c: Report the FSP-T output Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46885/1 diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index f6653e2..5adda44 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -10,6 +10,7 @@ #include <intelblocks/lpc_lib.h> #include <soc/pci_devs.h> #include <soc/bootblock.h> +#include <fsp/util.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,5 +55,7 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + if (CONFIG(FSP_CAR)) + report_fspt_output(); bootblock_pch_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3 Gerrit-Change-Number: 46885 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/intel/fsp2_0: Add function to report FSP-T output
by Arthur Heymans (Code Review) Nov. 2, 2020

Nov. 2, 2020

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46884 ) Change subject: drivers/intel/fsp2_0: Add function to report FSP-T output ...................................................................... drivers/intel/fsp2_0: Add function to report FSP-T output This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols: Change-Id: I8d79f97f8c12c63ce215935353717855442a8290 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fspt_report.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46884/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 32140f4..46299ee 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +bootblock-$(CONFIG_FSP_CAR) += fspt_report.c + romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/fspt_report.c b/src/drivers/intel/fsp2_0/fspt_report.c new file mode 100644 index 0000000..7fa3205 --- /dev/null +++ b/src/drivers/intel/fsp2_0/fspt_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/symbols.h> +#include <console/console.h> +#include <fsp/util.h> + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fspt_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP-T: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f154a34..a57b1bb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -89,6 +89,7 @@ void fsp_find_bootloader_tolum(struct range_entry *re); void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); +void report_fspt_output(void); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b9daf08..573f5ea 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -72,6 +72,8 @@ /* Setup bootblock stack */ mov %edx, %esp + push %ecx + push %edx /* clear .bss section as it is not shared */ cld @@ -82,6 +84,11 @@ shrl $2, %ecx rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/46884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d79f97f8c12c63ce215935353717855442a8290 Gerrit-Change-Number: 46884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU
by Furquan Shaikh (Code Review) Nov. 2, 2020

Nov. 2, 2020

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46905 ) Change subject: soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU ...................................................................... soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU This change adds the dependency on SOC_INTEL_CSE_LITE_SKU for the following configs: 1. SOC_INTEL_CSE_FMAP_NAME 2. SOC_INTEL_CSE_RW_CBFS_NAME 3. SOC_INTEL_CSE_RW_FILE These configs aren't really useful for platforms not using CSE Lite SKU. Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46905/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..a651198 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -22,18 +22,21 @@ config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" + depends on SOC_INTEL_CSE_LITE_SKU default "SI_ME" help Name of CSE region in FMAP config SOC_INTEL_CSE_RW_CBFS_NAME string "CBFS entry name for CSE RW blob" + depends on SOC_INTEL_CSE_LITE_SKU default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" + depends on SOC_INTEL_CSE_LITE_SKU default "" help Intel CSE CBFS RW blob path and file name -- To view, visit https://review.coreboot.org/c/coreboot/+/46905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77 Gerrit-Change-Number: 46905 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled
by Furquan Shaikh (Code Review) Nov. 2, 2020

Nov. 2, 2020

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46904 ) Change subject: drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled ...................................................................... drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled This change replaces the checks for dev->enabled with the helper function `is_dev_enabled()`. Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46904/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 33862d9..4544b46 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -222,7 +222,7 @@ { const char *path; - if (!dev->enabled) + if (is_dev_enabled(dev)) return; path = acpi_device_path(dev); @@ -247,7 +247,7 @@ { const char *path; - if (!dev->enabled) + if (!is_dev_enabled(dev)) return; path = acpi_device_path(dev->bus->dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/46904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f Gerrit-Change-Number: 46904 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: wifi: Drop PCI IDs for JfP and HrP
by Furquan Shaikh (Code Review) Nov. 2, 2020

Nov. 2, 2020

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46866 ) Change subject: wifi: Drop PCI IDs for JfP and HrP ...................................................................... wifi: Drop PCI IDs for JfP and HrP This change drops the PCI IDs for Jefferson Peak and Harrison Peak CNVi modules from wifi/generic drivers as well as pci_ids.h. These IDs actually represent the CNVi WiFi controller PCI IDs and are now supported by intel/common/block/cnvi driver. The only ID that is being dropped without adding support in intel/common/block/cnvi driver is PCI_DEVICE_ID_HrP_6SERIES_WIFI(0x2720) since this was not found in the list of PCI IDs for any SoC. Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/wifi/generic/generic.c M src/include/device/pci_ids.h 2 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/46866/1 diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 0b13fa8..1aa6ad4 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -89,18 +89,8 @@ PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI, /* Windstorm Peak */ PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI, - /* Jefferson Peak */ - PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI, - PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI, /* Thunder Peak 2 */ PCI_DEVICE_ID_TP_9260_SERIES_WIFI, - /* Harrison Peak */ - PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI, - PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI, - PCI_DEVICE_ID_HrP_6SERIES_WIFI, /* Cyclone Peak */ PCI_DEVICE_ID_CyP_6SERIES_WIFI, /* Typhoon Peak */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 68aaa7f..36c5dc6 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3950,19 +3950,11 @@ #define PCI_DEVICE_ID_WP_7260_SERIES_2_WIFI 0x08b2 #define PCI_DEVICE_ID_SP_7265_SERIES_1_WIFI 0x095a #define PCI_DEVICE_ID_SP_7265_SERIES_2_WIFI 0x095b -#define PCI_DEVICE_ID_JP_9000_SERIES_1_WIFI 0x9df0 -#define PCI_DEVICE_ID_JP_9000_SERIES_2_WIFI 0x31dc -#define PCI_DEVICE_ID_JP_9000_SERIES_3_WIFI 0xa370 #define PCI_DEVICE_ID_SFP_8260_SERIES_1_WIFI 0x24f3 #define PCI_DEVICE_ID_SFP_8260_SERIES_2_WIFI 0x24f4 #define PCI_DEVICE_ID_WSP_8275_SERIES_1_WIFI 0x24fd #define PCI_DEVICE_ID_TP_9260_SERIES_WIFI 0x2526 -#define PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI 0x34f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI 0xa0f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI 0x02f0 -#define PCI_DEVICE_ID_HrP_9560_SERIES_4_WIFI 0x06f0 #define PCI_DEVICE_ID_CyP_6SERIES_WIFI 0x2723 -#define PCI_DEVICE_ID_HrP_6SERIES_WIFI 0x2720 #define PCI_DEVICE_ID_TyP_6SERIES_WIFI 0x2725 #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 -- To view, visit https://review.coreboot.org/c/coreboot/+/46866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830 Gerrit-Change-Number: 46866 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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