July 2016 - coreboot-gerrit - mail.coreboot.org

Patch merged into coreboot/master: intel/broadwell: fix typo
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit e8f2ef51e1809b8c20d87049586935a7f3dd90a7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jul 29 18:53:34 2016 +0200 intel/broadwell: fix typo (pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents "case 3" below from ever happening) Change-Id: Id90655c39ff53da9569441278bbf73497d643480 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1293139 Reviewed-on: https://review.coreboot.org/15965 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15965 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: Enable signalling of error condition
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 90ed31beac54f6380a78a4b3c51c8fab434db95b Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jul 29 18:37:56 2016 +0200 intel/skylake: Enable signalling of error condition Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1357450, #1357449 Reviewed-on: https://review.coreboot.org/15964 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15964 for details. -gerrit

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Patch merged into coreboot/master: google/reef: Update chromeos.fmd RO_SECTION
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit bce1807d9c06c921381ed69343ccf4cfb145308a Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jul 29 09:57:13 2016 -0700 google/reef: Update chromeos.fmd RO_SECTION Update RO_SECTION to match the changes in depthcharge: https://chromium-review.googlesource.com/#/c/364261 BUG=chrome-os-partner:55713 Change-Id: I7238856cf73a62345778ea87e191a11190b7fb38 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15966 for details. -gerrit

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Patch merged into coreboot/master: intel/amenia: Enable DPTF in mainboard
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit b97cf79e2e4d8a9c1868da60c96925db57c0912d Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 00:29:48 2016 -0700 intel/amenia: Enable DPTF in mainboard This patch enables DPTF support for Intel Amenia platform, adds the ASL settings specific to Amenia boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I400e2312a20870058f3a386004fad748d3ee4460 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15094 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15094 for details. -gerrit

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Patch merged into coreboot/master: google/reef: Enable DPTF in mainboard
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 57f221e6c47261e82bc21f6baa25dfa17b097f5a Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jul 12 16:03:29 2016 -0700 google/reef: Enable DPTF in mainboard This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15640 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15640 for details. -gerrit

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Patch merged into coreboot/master: gigabyte/ga_2761gxdk: Remove comment *endif*
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit c663a1f033368dc78131dc615bd310b9820d55f1 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Thu Jul 28 17:21:59 2016 +0200 gigabyte/ga_2761gxdk: Remove comment *endif* After the indentation is fixed in commit *mainboard: Format irq_tables.c* [1], the comment is redundant. So remove it. [1] Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Change-Id: Iebbcf10ee3cef1b4cf60ea34a6b3ad51e2208671 Reviewed-on: https://review.coreboot.org/15933 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15933 for details. -gerrit

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Patch merged into coreboot/master: mainboard: Format irq_tables.c
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 95fe8fb1e0ce2ccf2d079898c27c799e4b0db928 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Thu Jul 28 17:20:20 2016 +0200 mainboard: Format irq_tables.c Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15932 for details. -gerrit

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Patch merged into coreboot/master: build system: really disable building CrEC when not needed
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 14caed85e121ca623d0ec4b9fba6d5bb64c8c46b Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu May 12 15:13:23 2016 +0200 build system: really disable building CrEC when not needed Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively ignore anything related to EC firmware board names if enabled. BUG=none BRANCH=none CQ-DEPEND=CL:344540 TEST=emerge-samus coreboot works Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233 Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345584 Original-Reviewed-by: Aaron Durbin <adurbin(a)google.com> Original-Commit-Queue: Martin Roth <martinroth(a)chromium.org> Original-Trybot-Ready: Martin Roth <martinroth(a)chromium.org> Original-Tested-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/15938 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15938 for details. -gerrit

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Patch merged into coreboot/master: superiotool: Add Nuvoton NCT6791D
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 312e9f586a9e099bf94a5cd677ff4f14a2c58bc1 Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Sat Jun 18 15:33:43 2016 +0200 superiotool: Add Nuvoton NCT6791D This adds support for the Nuvoton NCT6791D Super I/O chip to the superiotool. The implementation is based on the Datasheet supplied by Nuvoton: Datasheet Version: January 8th, 2016 Revision 1.11 Datasheet deviation: - Defaults for control registers 0x20 and 0x21 are invalid. Datasheet: 0xc562. Actual: 0xc803. Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672 Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> Reviewed-on: https://review.coreboot.org/15252 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15252 for details. -gerrit

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Patch merged into coreboot/master: src/arch: Capitalize CPU, RAM and ROM
by gerrit＠coreboot.org July 31, 2016

July 31, 2016

the following patch was just integrated into master: commit 777ea897e80c1705230200040fe5dda4fcb065db Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Jul 29 07:40:41 2016 +0200 src/arch: Capitalize CPU, RAM and ROM Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15953 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15953 for details. -gerrit

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