March 2016 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: superiotool: Support for chip NCT6102D / NCT6106D
by Roberto Muñoz Gómez March 31, 2016

March 31, 2016

Roberto Muñoz Gómez (roberto(a)gul.es) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14206 -gerrit commit 1741a521b7cfc6efe769c6fbc10cb2dfdba89ef8 Author: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> Date: Thu Mar 31 17:03:53 2016 +0200 superiotool: Support for chip NCT6102D / NCT6106D Added support of chip NCT6102D / NCT6106D in superiotool Change-Id: I689ff8e796f43a5aac144e9898df750407588b1f Signed-off-by: Roberto Muñoz Gómez <munoz.roberto(a)gmail.com> --- util/superiotool/nuvoton.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 7135f25..83f461d 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -464,6 +464,74 @@ static const struct superio_registers reg_table[] = { {0x30,0xe0,0xe1,0xe2,EOT}, {0x20,0x20,0x04,0x05,EOT}}, {EOT}}}, + {0xc452, "NCT6102D / NCT6106D", { + {NOLDN, NULL, + {0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2f,EOT}, + {0x00,0xff,0xff,0x00,0x00,0xcc,0x03,0x10,0x61,0x7F,0x00,0x00,MISC,0x00,0x00,0xf0,0x00,MISC,EOT}}, + {0x00, "FDC", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00,EOT}}, + {0x01, "PRT", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x02, "UART A", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x03,0xf8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x03, "UART B", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x05, "Keyboard Controller (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x06, "CIR", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}}, + {0x07, "GPIO", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xdf,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x02,0x00,0x00,0x00,EOT}}, + {0x08, "GPIO,WDT1", + {0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,EOT}}, + {0x09, "GPIO", + {0xe0,0xe1,0xe2,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x0a, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa,EOT}, + {0x01,0x00,0x00,0x00,0x00,0x02,0x1c,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}}, + {0x0b, "Hardware Monitor, Front Panel LED", + {0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0x00,0x00,0x00,0x00,0x00,0x87,0x47,0x00,EOT}}, + {0x0d, "WDT2", + {0xe0,0xe1,0xe2,0xe3,0xe4,EOT}, + {0x00,0x32,0x14,0x00,0x00,EOT}}, + {0x0e, "CIR WAKE-UP", + {0x30,0x60,0x61,0x70,0xe0,0xe1,EOT}, + {0x00,0x00,0x00,0x00,0x25,0x00,EOT}}, + {0x0f, "GPIO Push-Pull or Open-drain", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1,0xf2,EOT}, + {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0x9d,0x00,0x00,EOT}}, + {0x10, "UARTC", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0x00,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x11, "UARTD", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0x00,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x12, "UARTE", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x03,0xe8,0x04,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x13, "UARTF", + {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x02,0xe8,0x03,0x00,0x00,0x00,0xff,0xff,0x02,0x00,0x00,EOT}}, + {0x14, "PORT80 IR", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x10,0x00,0x00,0x00,EOT}}, + {0x15, "FADING LED", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,EOT}, + {0x00,0x3f,0x01,0x11,0x11,0x02,0x00,0x00,0x01,0x00,EOT}}, + {0x16, "Deep Sleep", + {0x30,0xe0,0xe1,0xe2,EOT}, + {0x20,0x20,0x04,0x05,EOT}}, + {EOT}}}, {EOT} };

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Patch set updated for coreboot: intel/gma: Fix VBT generation
by Patrick Rudolph March 31, 2016

March 31, 2016

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14188 -gerrit commit 6ea9ee72d6f85001ec52a844a4105580c064f9e7 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Mar 30 17:59:09 2016 +0200 intel/gma: Fix VBT generation The log shows the following error on systems that use the native gfx init. The error isn't shown using the VBIOS blob: GET_VBIOS: aa55 8086 0 3 0 VBIOS not found. Don't shift the class-code, as it's already shifted by the PCI layer. Tested-on: x220 Tested-by: Alexander Couzens <lynxis(a)fe80.eu> Change-Id: I69018940dd51966b45774e0576a1380f90716dce Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/intel/gma/vbt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 1993793..e768402 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -93,9 +93,9 @@ generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf, pcir->device = dev->device; pcir->length = sizeof(*pcir); pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; + pcir->classcode[0] = dev->class; + pcir->classcode[1] = dev->class >> 8; + pcir->classcode[2] = dev->class >> 16; pcir->indicator = 0x80; vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr);

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New patch to review for coreboot: soc/intel/apollolake: Fix MMIO reserved ranges calculation
by Andrey Petrov March 30, 2016

March 30, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14203 -gerrit commit 9e90d6c02264f73a2ae5c8fc73d3f32670e3e447 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 30 18:15:30 2016 -0700 soc/intel/apollolake: Fix MMIO reserved ranges calculation mmio_resource() takes memory address in kilobytes. This patch adds resources properly. Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/northbridge.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 35c36c8..7d29c9e 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -30,13 +30,15 @@ static uint32_t get_bar(device_t dev, unsigned int index) static int mc_add_fixed_mmio_resources(device_t dev, int index) { + unsigned long addr; + /* PCI extended config region */ - mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB), - PCIEX_SIZE / KiB); + addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB; + mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB); /* Memory Controller Hub */ - mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB), - MCH_BASE_SIZE / KiB); + addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB; + mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB); return index; }

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Patch set updated for coreboot: vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment
by Martin Roth March 30, 2016

March 30, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5543 -gerrit commit ae1d364aa66a9c1b88feb775825c583a3812a1b6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 15 10:47:50 2013 +0100 vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in comment The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/AGESA.h | 2 +- src/vendorcode/amd/agesa/f12/AGESA.h | 2 +- src/vendorcode/amd/agesa/f14/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15tn/AGESA.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index a128116..a6a8d07 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -764,7 +764,7 @@ typedef enum { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index abe72b6..feb8397 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1022,7 +1022,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index d997ad1..2dc234b 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -877,7 +877,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index ffa37ae..1a0c1f6 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1145,7 +1145,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index a709274..1392810 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1244,7 +1244,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = {

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Patch set updated for coreboot: southbridge: Remove trailing space in `dump_south()` output
by Paul Menzel March 30, 2016

March 30, 2016

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5179 -gerrit commit f03f3c23029104f96263854491571fecd2671bf4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 10 11:46:52 2014 +0100 southbridge: Remove trailing space in `dump_south()` output Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/amd/cs5535/cs5535.c | 4 +- src/southbridge/via/vt8235/vt8235.c | 89 ----------------------------------- src/southbridge/via/vt8237r/vt8237r.c | 4 +- 3 files changed, 4 insertions(+), 93 deletions(-) diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 42707c0..9130a68 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -57,9 +57,9 @@ static void dump_south(struct device *dev) int i, j; for(i=0; i<256; i+=16) { - printk(BIOS_DEBUG, "0x%02x: ", i); + printk(BIOS_DEBUG, "0x%02x:", i); for(j=0; j<16; j++) - printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); + printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } } diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c deleted file mode 100644 index 4fa2784..0000000 --- a/src/southbridge/via/vt8235/vt8235.c +++ /dev/null @@ -1,89 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <pc80/keyboard.h> -#include <pc80/i8259.h> -#include "chip.h" - -static void keyboard_on(struct device *dev) -{ - u8 regval; - - regval = pci_read_config8(dev, 0x51); - regval |= 0x05; - regval &= 0xfd; - pci_write_config8(dev, 0x51, regval); - - pc_keyboard_init(0); -} - -#ifdef UNUSED_CODE -void dump_south(device_t dev0) -{ - int i,j; - - for(i = 0; i < 256; i += 16) { - printk(BIOS_DEBUG, "0x%x: ", i); - for(j = 0; j < 16; j++) { - printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev0, i+j)); - } - printk(BIOS_DEBUG, "\n"); - } -} - -void set_led(void) -{ - // set power led to steady now that coreboot has virtually done its job - device_t dev; - dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0); - pci_write_config8(dev, 0x94, 0xb0); -} -#endif - -static void vt8235_enable(struct device *dev) -{ - u8 regval; - u16 vendor,model; - - vendor = pci_read_config16(dev,0); - model = pci_read_config16(dev,0x2); - - printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model); - - /* If this is not the southbridge itself just return. - * This is necessary because USB devices are slot 10, whereas this - * device is slot 11 therefore usb devices get called first during - * the bus scan. We don't want to wait until we could do dev->init - * because that's too late. - */ - - if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235)) - return; - - printk(BIOS_DEBUG, "Initialising Devices\n"); - - /* make sure interupt controller is configured before keyboard init */ - setup_i8259(); - - /* enable RTC and ethernet */ - regval = pci_read_config8(dev, 0x51); - regval |= 0x18; - pci_write_config8(dev, 0x51, regval); - - /* turn on keyboard */ - keyboard_on(dev); - - /* enable USB 1.1 & USB 2.0 - redundant really since we've - * already been there - see note above - */ - regval = pci_read_config8(dev, 0x50); - regval &= ~(0x36); - pci_write_config8(dev, 0x50, regval); -} - -struct chip_operations southbridge_via_vt8235_ops = { - CHIP_NAME("VIA VT8235 Southbridge") - .enable_dev = vt8235_enable, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5f2449a..8848147 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -57,9 +57,9 @@ void dump_south(device_t dev) int i, j; for (i = 0; i < 256; i += 16) { - printk(BIOS_DEBUG, "%02x: ", i); + printk(BIOS_DEBUG, "%02x:", i); for (j = 0; j < 16; j++) - printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j)); + printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i + j)); printk(BIOS_DEBUG, "\n"); } }

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Patch set updated for coreboot: nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
by Timothy Pearson March 30, 2016

March 30, 2016

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192 -gerrit commit e1f2f3d1e23161e3063dd20a2b2399d496decc45 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Mar 30 13:48:24 2016 -0500 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 46 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 4 files changed, 49 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..de9f342 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include "amdfam10.h" @@ -152,6 +153,51 @@ static void misc_control_init(struct device *dev) printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); +#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + uint8_t dimm_present; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2de7521..0b88331 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8024,8 +8024,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; + pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; dword &= ~(0x1 << 30); dword &= ~(0x1 << 21); + dword &= ~(0x1 << 2); Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); pDCTstat->mca_config_backed_up = 1; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 6031239..67eb2b4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -584,6 +584,7 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t mca_config_backed_up; uint8_t sync_flood_on_dram_err; uint8_t sync_flood_on_any_uc_err; + uint8_t sync_flood_on_uc_dram_ecc_err; /* New for LB Support */ u8 NodePresent; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; - uint32_t dword; - mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }

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Patch merged into coreboot/master: util/superiotool: Register fix for Fintek F81865F/F-I
by gerrit＠coreboot.org March 30, 2016

March 30, 2016

the following patch was just integrated into master: commit 3b55602b258e04b82dbb41f3332c5fb7f1b7bd81 Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> Date: Mon Mar 24 09:50:25 2014 +0100 util/superiotool: Register fix for Fintek F81865F/F-I Datasheet: http://www.fintek.com.tw/files/productfiles/F81865_V028P.pdf There is a multi-function select register listed as 0x2a-1 and 0x2a-2. These are the original names in the datasheet, but superiotool will display register 0x29 and 0x28 and their values. This patch renames them both to 0x2a and shows both of the default values for them. They are both 0x00, so one of them could be dropped though. Change-Id: Iad91f9e4755d2d1a123e56ab0fa9257be7ea9978 Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde(a)gmail.com> Reviewed-on: https://review.coreboot.org/5404 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/5404 for details. -gerrit

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Patch set updated for coreboot: LINT TEST: Do not submit
by Martin Roth March 30, 2016

March 30, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14197 -gerrit commit 7edb90accd7609f129bcba0001630072dfa7679b Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 14:08:52 2016 -0600 LINT TEST: Do not submit This should cause all of the lint-stable tests to fail. Change-Id: I38db15c4d169bfebc443007da883e17a08fadc01 Signed-off-by: Martin Roth <martinroth(a)google.com> --- site-local/tmp.b6e9i3VnEc | 0 src/acpi/sata.c | 18 +++++++++--------- src/arch/power8/misc.c | 2 +- src/arch/x86/bootblock_romcc.S | 1 + src/arch/x86/thread.c | 18 +++++++++--------- src/lib/libgcc.c | 0 src/mainboard/aaeon/pfm-540i_revb/board_info.txt | 2 +- src/mainboard/amd/bettong/Kconfig.name | 2 -- src/mainboard/google/storm/board_info.txt | 6 ------ src/soc/nvidia/tegra124/spi.c | 4 ++-- src/superio/common/conf_mode.c | 3 +++ 11 files changed, 26 insertions(+), 30 deletions(-) diff --git a/site-local/tmp.b6e9i3VnEc b/site-local/tmp.b6e9i3VnEc new file mode 100644 index 0000000..e69de29 diff --git a/src/acpi/sata.c b/src/acpi/sata.c index ec0d505..aab9c0d 100644 --- a/src/acpi/sata.c +++ b/src/acpi/sata.c @@ -10,12 +10,12 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - + #include "sata.h" - + #include <arch/acpi.h> #include <arch/acpigen.h> - + /* e.g. * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); * generates: @@ -38,23 +38,23 @@ void generate_sata_ssdt_ports(const char *scope, uint32_t enable_map) int i; uint32_t bit; char port_name[4] = "PR00"; - + acpigen_write_scope(scope); - + /* generate a device for every enabled port */ for (i = 0; i < 32; i++) { bit = 1 << i; if (!(bit & enable_map)) continue; - + port_name[2] = '0' + i / 10; port_name[3] = '0' + i % 10; - + acpigen_write_device(port_name); - + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); acpigen_pop_len(); /* close PRT%d */ } - + acpigen_pop_len(); /* close scope */ } diff --git a/src/arch/power8/misc.c b/src/arch/power8/misc.c index 65b8ecf..fbc5678 100644 --- a/src/arch/power8/misc.c +++ b/src/arch/power8/misc.c @@ -6,7 +6,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 6c1723a..0d7d759 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -1,3 +1,4 @@ +.att_syntax noprefix /* * This file is part of the coreboot project. * diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index 993577d..f2dae2d 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -1,16 +1,16 @@ /* - * This file is part of the coreboot project. + * - * Copyright (C) 2013 Google, Inc. + * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + + + * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + + + + */ #include <thread.h> diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c old mode 100644 new mode 100755 diff --git a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt index 76246af..a8db96f 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/board_info.txt +++ b/src/mainboard/aaeon/pfm-540i_revb/board_info.txt @@ -1,3 +1,3 @@ Board name: PFM-540I Rev.B -Category: half +Category: lint Board URL: http://www.aaeonusa.com/products/details/?item_id=1043 diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name deleted file mode 100644 index 09201b5..0000000 --- a/src/mainboard/amd/bettong/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_AMD_BETTONG - bool "Bettong" diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt deleted file mode 100644 index edc4b32..0000000 --- a/src/mainboard/google/storm/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Storm Qualcomm IPQ806X board -Category: settop -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5be4a6..3d659d7 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -580,7 +580,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) } ret = 0; -done: + done: spi->dma_in = NULL; spi->dma_out = NULL; return ret; @@ -684,7 +684,7 @@ static int xfer_setup(struct tegra_spi_channel *spi, void *buf, goto done; } -done: + done: return ret; } diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index cbe1a9e..423f127 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -11,6 +11,9 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. */ #include <arch/io.h>

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Patch set updated for coreboot: src/: Fix lint style-labels warnings
by Martin Roth March 30, 2016

March 30, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14193 -gerrit commit 1403901a425dafae67adf340be3047e4635ea988 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:30:12 2016 -0600 src/: Fix lint style-labels warnings The lint-stable-004-style-labels check tries to verify that labels in c and asm files start at the first column, and don't have whitespace in front of them. - Fix 2 actual violations of the lint check. - Update a comment that was showing up as a violation. Change-Id: Ia11a90d7301e62a116c7a9ef9b4c2bc3f982b308 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/commonlib/lz4.c.inc | 64 +++++++++++----------- src/cpu/allwinner/a10/raminit.c | 2 +- src/cpu/amd/family_10h-family_15h/processor_name.c | 2 +- 3 files changed, 34 insertions(+), 34 deletions(-) diff --git a/src/commonlib/lz4.c.inc b/src/commonlib/lz4.c.inc index b3be4e5..e8f6e59 100644 --- a/src/commonlib/lz4.c.inc +++ b/src/commonlib/lz4.c.inc @@ -1,36 +1,36 @@ /* - LZ4 - Fast LZ compression algorithm - Copyright (C) 2011-2015, Yann Collet. - - BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are - met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above - copyright notice, this list of conditions and the following disclaimer - in the documentation and/or other materials provided with the - distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - You can contact the author at : - - LZ4 source repository : https://github.com/Cyan4973/lz4 - - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c -*/ + * LZ4 - Fast LZ compression algorithm + * Copyright (C) 2011-2015, Yann Collet. + * + * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You can contact the author at : + * - LZ4 source repository : https://github.com/Cyan4973/lz4 + * - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c + */ /************************************** diff --git a/src/cpu/allwinner/a10/raminit.c b/src/cpu/allwinner/a10/raminit.c index e917e6e..f3b39cb 100644 --- a/src/cpu/allwinner/a10/raminit.c +++ b/src/cpu/allwinner/a10/raminit.c @@ -317,7 +317,7 @@ static int dramc_scan_dll_para(void) return dramc_scan_readpipe(); } - fail: +fail: clrbits_le32(&dram->dllcr[0], 0x3f << 6); for (cr_i = 1; cr_i < 5; cr_i++) clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14); diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index ac0392b..3d92ee2 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -340,7 +340,7 @@ int init_processor_name(void) } } - done: +done: strcpymax(&program_string[j], processor_name_string, sizeof(program_string) - j); }

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Patch set updated for coreboot: lint/lint-stable-004-style-labels: Update script
by Martin Roth March 30, 2016

March 30, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14194 -gerrit commit 631d52d6ab1fc5edcd550047f2eeeec72ddc163e Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 30 13:56:23 2016 -0600 lint/lint-stable-004-style-labels: Update script - Look at entire tree instead of just the current commit. This was causing the test to overlook some issues that were already in the tree. - If git is on the system, and the code is in a git repo, use the 'git ls-files' command to find the files to examine. If those conditions aren't met, fall back to using the find command. - Wrap the command so it's easier to read. Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-004-style-labels | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/util/lint/lint-stable-004-style-labels b/util/lint/lint-stable-004-style-labels index f024ca1..7b68b4a 100755 --- a/util/lint/lint-stable-004-style-labels +++ b/util/lint/lint-stable-004-style-labels @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> +# Copyright (C) 2016 Google Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,4 +16,15 @@ # DESCR: Check that C labels begin at start-of-line LC_ALL=C export LC_ALL -git diff --name-status |grep -v "^D" |cut -c3- |grep "^src/.*\.[csS]" | xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' |grep -v "[^a-z_]default:" + +# Use git ls-files if the code is in a git repo, otherwise use find. +if [ -n "$(command -v git)" ] && [ -d .git ]; then + FIND_FILES="git ls-files" +else + FIND_FILES="find src" +fi + +${FIND_FILES} | \ + grep "^src/.*\.[csS]$" | \ + xargs grep -Hn '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' | \ + grep -v "[^a-z_]default:"

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