March 2016 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: drivers/intel/fsp2_0: Add SiliconInit API
by Andrey Petrov March 1, 2016

March 1, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13799 -gerrit commit e0f1f98f6d05e4a020326823819645f6a8ddc8e5 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:17:45 2016 -0800 drivers/intel/fsp2_0: Add SiliconInit API This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/silicon_init.c | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c new file mode 100644 index 0000000..e1089c7 --- /dev/null +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> + +#define FSPS_OFFSET_S_CONFIG 0x40 + +struct fsp_header fsps_hdr; + +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static enum fsp_status do_silicon_init(struct fsp_header *hdr) +{ + uint8_t *silicon_upd; + struct FSP_S_CONFIG *fsp_s_config; + fsp_silicon_init_fn silicon_init; + enum fsp_status status; + + silicon_upd = (uint8_t *) (hdr->cfg_region_offset + hdr->image_base); + /* UPD region is in RW memory, so it can be modified directly */ + fsp_s_config = (struct FSP_S_CONFIG *) (silicon_upd + + FSPS_OFFSET_S_CONFIG); + + /* Give SoC/mainboard a chance to populate entries */ + platform_fsp_silicon_init_params_cb(fsp_s_config); + + silicon_init = (void *) (hdr->image_base + + hdr->silicon_init_entry_offset); + + status = silicon_init(silicon_upd); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + return status; +} + +enum fsp_status fsp_silicon_init(struct range_entry *range) +{ + /* Load FSP-S and save FSP header. We will need it for Notify */ + if (fsp_load_binary(&fsps_hdr, CONFIG_FSP_S_FILE, range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_silicon_init(&fsps_hdr); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add MemoryInit API
by Andrey Petrov March 1, 2016

March 1, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13798 -gerrit commit ba1da8e5629cc01c27c11c4d13e099c0a4a491a9 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:16:33 2016 -0800 drivers/intel/fsp2_0: Add MemoryInit API This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/memory_init.c | 125 +++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..ff5d54d --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +/* offsets for fields in ARCH UPD from the beginning of FSP-M config region */ +#define FSPM_UPD_OFFSET_REVISION 0x20 +#define FSPM_UPD_OFFSET_NVSBUFFER 0x24 +#define FSPM_UPD_OFFSET_STACKBASE 0x28 +#define FSPM_UPD_OFFSET_STACKSIZE 0x2c +#define FSPM_UPD_OFFSET_BLSZ 0x30 +#define FSPM_UPD_OFFSET_BOOTMODE 0x34 +/* + * FSP_M_CONFIG structure start. + * FSP_M_CONFIG contains all SoC-specific parameters. + */ +#define FSPM_UPD_OFFSET_MCONFIG 0x40 + +struct fsp_memory_init_params { + void *nvs_buffer; + void *raminit_upd; + void **hob_list; +} __attribute__ ((__packed__)); + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (struct fsp_memory_init_params *); + +static struct FSP_M_CONFIG *fspm_parse_upd(void *cfg_region, + struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + arch_upd->revision = read8(raw_hdr + FSPM_UPD_OFFSET_REVISION); + arch_upd->nvs_buffer = read32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER); + arch_upd->stack_base = read32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE); + arch_upd->stack_size = read32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE); + arch_upd->bootloader_tolumsz = read32(raw_hdr + FSPM_UPD_OFFSET_BLSZ); + arch_upd->boot_mode = read32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE); + + return (struct FSP_M_CONFIG *) (raw_hdr + FSPM_UPD_OFFSET_MCONFIG); +} + +static void fspm_update_cfg(void *cfg_region, struct fsp_m_arch_upd *arch_upd) +{ + uint8_t *raw_hdr = (uint8_t*) cfg_region; + + write8(raw_hdr + FSPM_UPD_OFFSET_REVISION, arch_upd->revision); + write32(raw_hdr + FSPM_UPD_OFFSET_NVSBUFFER, arch_upd->nvs_buffer); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKBASE, arch_upd->stack_base); + write32(raw_hdr + FSPM_UPD_OFFSET_STACKSIZE, arch_upd->stack_size); + write32(raw_hdr + FSPM_UPD_OFFSET_BLSZ, arch_upd->bootloader_tolumsz); + write32(raw_hdr + FSPM_UPD_OFFSET_BOOTMODE, arch_upd->boot_mode); +} + +static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, + struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct fsp_memory_init_params raminit_params; + struct fsp_m_arch_upd arch_upd; + struct FSP_M_CONFIG *fsp_m_config; + void *mem_upd; + + post_code(0x34); + /* UPD region resides in CAR. Thus, it can be directly modified. */ + mem_upd = (void *)(hdr->cfg_region_offset + hdr->image_base); + + /* Read default values from arch_upd, perhaps they can be useful. */ + fsp_m_config = fspm_parse_upd(mem_upd, &arch_upd); + + /* Get any board specific changes */ + raminit_params.nvs_buffer = NULL; + raminit_params.raminit_upd = mem_upd; + raminit_params.hob_list = hob_list_ptr; + + /* Give SoC and mainboard a chance to update the UPD */ + platform_fsp_memory_init_params_cb(&arch_upd, fsp_m_config); + + /* Update the actual upd region */ + fspm_update_cfg(mem_upd, &arch_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); + printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); + printk(BIOS_SPEW, "\t%p: raminit_upd\n", raminit_params.raminit_upd); + printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&raminit_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *range) +{ + struct fsp_header hdr; + + if (fsp_load_binary(&hdr, CONFIG_FSP_M_FILE, range) != CB_SUCCESS) + return FSP_NOT_FOUND; + + return do_fsp_memory_init(hob_list, &hdr); +}

1 0

Patch set updated for coreboot: arch/x86: Allow soc/chipset to set linking address
by Andrey Petrov March 1, 2016

March 1, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13860 -gerrit commit 74c5455f548f61b13be332ed6bcb76b53fb89bf6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:04:51 2016 -0800 arch/x86: Allow soc/chipset to set linking address Until recently x86 romstage used to be linked at some default address. The address itself is not meaningful because the code was normally relocated at address calculated during insertion in CBFS. Since some newer SoC run romstage at CAR it became useful to link romstage code at some address in CAR and avoid relocation during build/run time altogether. Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/arch/x86/Kconfig | 10 ++++++++++ src/arch/x86/memlayout.ld | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 89e142a..2257cb6 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -161,3 +161,13 @@ config COMPILE_IN_DSDT config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 + +# Default address romstage is to be linked at +config ROMSTAGE_ADDR + hex + default 0x2000000 + +# Default address verstage is to be linked at +config VERSTAGE_ADDR + hex + default 0x2000000 diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index fb67575..56611041 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -31,14 +31,14 @@ SECTIONS #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - ROMSTAGE(32M, 1M) + ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) /* Pull in the cache-as-ram rules. */ #include "car.ld" #elif ENV_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ - VERSTAGE(32M, 1M) + VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) /* Pull in the cache-as-ram rules. */ #include "car.ld"

1 0

Patch set updated for coreboot: arch/x86: Add common assembly code for stages that run in CAR
by Andrey Petrov March 1, 2016

March 1, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13861 -gerrit commit f54d595f06dad1891b3fa294266f388ff194300f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Feb 28 22:37:15 2016 -0800 arch/x86: Add common assembly code for stages that run in CAR This adds a few assembly lines that are generic enought to be shared between romstage and verstage that are ran in CAR. Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/arch/x86/carstage_entry.S | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/src/arch/x86/carstage_entry.S b/src/arch/x86/carstage_entry.S new file mode 100644 index 0000000..4a601a7 --- /dev/null +++ b/src/arch/x86/carstage_entry.S @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +.global _start +_start: + +#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ + /* + * This code is meant to be used for stages that are ran in CAR. + * The assumption is that gdt is already loaded. So in order to + * continue with C code execution we needed to set stack pointer + * and clear CAR_GLOBAL variables that are stage-specific. + */ + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + jmp romstage_car_entry + movb $0x69, %ah + jmp .Lhlt + +.Lhlt: + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif + movl $LHLT_DELAY, %ecx +.Lhlt_Delay: + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt

1 0

New patch to review for coreboot: buildgcc: Use $(CURDIR) instead of $(PWD)
by Stefan Reinauer March 1, 2016

March 1, 2016

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13869 -gerrit commit eedfd970034ec943adc0b4d4a933af26f69b2d42 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 1 12:55:47 2016 -0800 buildgcc: Use $(CURDIR) instead of $(PWD) coreboot's top level Makefile does the same, so let's stay consistent. Change-Id: I9e995f3ecadd05d6fbfda64b45dee3a9900d9189 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index aadf316..436a2ac 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,6 +1,6 @@ # if no architecture is specified, set a default BUILD_PLATFORM ?= i386-elf -DEST ?= $(PWD)/xgcc +DEST ?= $(CURDIR)/xgcc # For the toolchain builds, use CPUS=x to use multiple processors to build # use KEEP_SOURCES=1 to keep temporary files after the build

1 0

New patch to review for coreboot: crossgcc: add 'urls' option to print urls of all packages
by Martin Roth March 1, 2016

March 1, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13867 -gerrit commit 949b05bee81a1810a53d9e1d37d2299ab74cdcf1 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 1 15:22:42 2016 -0700 crossgcc: add 'urls' option to print urls of all packages This should allow the builder to download the packages securely. Change-Id: If5feeff85bd551cbe08849421197d11cc2432d1e Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e0ef981..679c0ef 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -64,6 +64,11 @@ CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSI CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" MAKE_ARCHIVE="http://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" +ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ + $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ + $PYTHON_ARCHIVE $EXPAT_ARCHIVE $LLVM_ARCHIVE $CFE_ARCHIVE \ + $CRT_ARCHIVE $CTE_ARCHIVE $MAKE_ARCHIVE" + # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" @@ -316,6 +321,7 @@ myhelp() printf " [-t|--savetemps] don't remove temporary files after build\n" printf " [-y|--ccache] Use ccache when building cross compiler\n" printf " [--nocolor] don't print color codes in output\n" + printf " [--urls] print the urls for all packages\n" printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" printf " [-s]--supported <tool> print supported version of a tool" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" @@ -590,6 +596,7 @@ while true ; do -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; -s|--supported) shift; PRINTSTABLE="$1"; shift;; + --urls) shift; printf "%s\n" "$ALL_ARCHIVES"; exit 0;; --nocolor) shift; \ unset red RED green GREEN blue BLUE cyan CYAN NC;; --) shift; break;;

1 0

New patch to review for coreboot: buildgcc: Add 'nocolor' option to remove color codes from output
by Martin Roth March 1, 2016

March 1, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13866 -gerrit commit f261a6fa394fbc4c092f350fb96f99d8eab33fe9 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 1 15:21:07 2016 -0700 buildgcc: Add 'nocolor' option to remove color codes from output When writing to a logfile, the color codes just make things confusing. The --nocolor option will allow these to not be printed. Change-Id: I67645aac20b420ac83b828e77e0e50aab88d3d47 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/crossgcc/buildgcc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e4a6d47..e0ef981 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -315,6 +315,7 @@ myhelp() printf " [-c|--clean] remove temporary files before build\n" printf " [-t|--savetemps] don't remove temporary files after build\n" printf " [-y|--ccache] Use ccache when building cross compiler\n" + printf " [--nocolor] don't print color codes in output\n" printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" printf " [-s]--supported <tool> print supported version of a tool" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" @@ -589,6 +590,8 @@ while true ; do -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; -s|--supported) shift; PRINTSTABLE="$1"; shift;; + --nocolor) shift; \ + unset red RED green GREEN blue BLUE cyan CYAN NC;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;;

1 0

Patch merged into coreboot/master: buildgcc: Allow specifying destination directory
by gerrit＠coreboot.org March 1, 2016

March 1, 2016

the following patch was just integrated into master: commit 163506a8f609ec2763b892f27e05983ad27a98fb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:29:58 2016 -0800 buildgcc: Allow specifying destination directory With this change you can say $ make DEST=/opt/cross-1.35 to get all of the cross toolchain built and installed to /opt/cross-1.35 Change-Id: Icc3e605c4824bfa2831d030e4ed9dd0331ff722f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13847 for details. -gerrit

1 0

Patch merged into coreboot/master: buildgcc: Fix building GDB for mipsel-elf
by gerrit＠coreboot.org March 1, 2016

March 1, 2016

the following patch was just integrated into master: commit b7c40630d9fee0e1be68b1d3af330a0ec1c841ee Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:35:54 2016 -0800 buildgcc: Fix building GDB for mipsel-elf Change-Id: I31ed159b13c0da60383068832615c6e4a9608efe Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/13849 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13849 for details. -gerrit

1 0

Patch merged into coreboot/master: crosstool: add EXPAT as a dependency on the gdb build.
by gerrit＠coreboot.org March 1, 2016

March 1, 2016

the following patch was just integrated into master: commit fb944f4270d787e2e705b46698d9f9851ea8a20e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Feb 27 04:06:42 2016 +0000 crosstool: add EXPAT as a dependency on the gdb build. qemu-power8 wants to tell about itself with XML, and so we need to build gdb with EXPAT so it can understand XML. Change-Id: I460e27f883956ed5d54e6070916e2682ee0f7a1b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/13846 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13846 for details. -gerrit

1 0