December 2016 - coreboot-gerrit

New patch to review for coreboot: soc/intel/apollolake: Drop privilege level to IA_UNTRUSTED
by Andrey Petrov Nov. 30, 2016

Nov. 30, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17665 -gerrit commit dee7041a9af9c4a8c9dfac899716681d072f6e69 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 30 17:58:38 2016 -0800 soc/intel/apollolake: Drop privilege level to IA_UNTRUSTED As per guidelines CPU security level should be dropped before OS start, so that certain MSRs are locked out. Drop privilege levels on all logical CPUs. BUG=chrome-os-partner:60454 TEST=iotools rdmsr x 0x120, make sure bit 6 is set, rdmsr x 0x121 results in io error. Change-Id: I67540f6da16f58b822db9160d00b7a5e235188db Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/car.c | 2 +- src/soc/intel/apollolake/cpu.c | 9 +++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..d58dc0a 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -28,7 +28,7 @@ static void flush_l1d_to_l2(void) { msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= (1 << 8); + msr.lo |= FLUSH_DL1_L2; wrmsr(MSR_POWER_MISC, msr); } diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index fc9fa56..14d8c20 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -53,6 +53,13 @@ static const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; +static void enable_untrusted_mode(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= ENABLE_IA_UNTRUSTED; + wrmsr(MSR_POWER_MISC, msr); +} + static void soc_core_init(device_t cpu) { /* Set core MSRs */ @@ -63,6 +70,8 @@ static void soc_core_init(device_t cpu) * implemented in microcode. */ enable_pm_timer(); + /* Drop privilege level */ + enable_untrusted_mode(); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 38ce4ff..db9d3dd 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -31,6 +31,8 @@ void set_max_freq(void); #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 +#define ENABLE_IA_UNTRUSTED (1 << 6) +#define FLUSH_DL1_L2 (1 << 8) #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_EVICT_CTL 0x2e0 #define MSR_EMULATE_PM_TMR 0x121

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Patch set updated for coreboot: soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs
by Andrey Petrov Nov. 30, 2016

Nov. 30, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17663 -gerrit commit e6ae49bb98ed4aa503cc283da7043119139e83d6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 30 17:39:16 2016 -0800 soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 16 ---------------- src/soc/intel/apollolake/cpu.c | 7 +++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 ++ src/soc/intel/apollolake/pmutil.c | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..4674e8b 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -41,22 +41,6 @@ static void tpm_enable(void) gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); } -static void enable_pm_timer(void) -{ - /* ACPI PM timer emulation */ - msr_t msr; - /* - * The derived frequency is calculated as follows: - * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. - */ - msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR); - wrmsr(MSR_EMULATE_PM_TMR, msr); -} - static void enable_cmos_upper_bank(void) { uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 916d7c5..fc9fa56 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -28,6 +28,7 @@ #include <reg_script.h> #include <soc/cpu.h> #include <soc/iomap.h> +#include <soc/pm.h> #include <soc/smm.h> #include <cpu/intel/turbo.h> @@ -56,6 +57,12 @@ static void soc_core_init(device_t cpu) { /* Set core MSRs */ reg_script_run(core_msr_script); + /* + * Enable ACPI PM timer emulation, which also lets microcode know + * location of ACPI_PMIO_BASE. This also enables other features + * implemented in microcode. + */ + enable_pm_timer(); } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index dd9e526..b8af5b2 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -213,4 +213,6 @@ void global_reset_lock(void); void pch_log_state(void); +void enable_pm_timer(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c88e5ae..6363a2f 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -21,10 +21,12 @@ #include <arch/io.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/x86/msr.h> #include <rules.h> #include <device/pci_def.h> #include <halt.h> #include <soc/iomap.h> +#include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <device/device.h> @@ -551,3 +553,19 @@ void pmc_gpe_init(void) /* Set the routes in the GPIO communities as well. */ gpio_route_gpe(dw1, dw2, dw3); } + +void enable_pm_timer(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR); + wrmsr(MSR_EMULATE_PM_TMR, msr); +}

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New patch to review for coreboot: cbfs: New API to locate a file from specific region
by Pratikkumar V Prajapati Nov. 30, 2016

Nov. 30, 2016

Pratikkumar V Prajapati (pratikkumar.v.prajapati(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17664 -gerrit commit e129e8421a8f6a6318a70f18919ece2563bdbc75 Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Wed Nov 30 17:29:10 2016 -0800 cbfs: New API to locate a file from specific region method to find file by name from any specific region of fmap. Change-Id: Iabe785a6434937be6a57c7009882a0d68f6c8ad4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/include/cbfs.h | 3 +++ src/lib/cbfs.c | 27 ++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 8538b3d..b063f0e 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -34,6 +34,9 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); * leaking mappings are a no-op. Returns NULL on error, else returns * the mapping and sets the size of the file. */ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); +/* Locate file in a specific region of fmap.*/ +void *cbfs_locate_file_in_region(const char *region_name, + const char *file_name, uint32_t file_type, size_t *file_size); /* Load a struct file from CBFS into a buffer. Returns amount of loaded * bytes on success or 0 on error. File will get decompressed as necessary. * Same decompression requirements as cbfs_load_and_decompress(). */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 19737a4..9b5c7fa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -24,7 +24,7 @@ #include <lib.h> #include <symbols.h> #include <timestamp.h> - +#include <fmap.h> #include "fmap_config.h" #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) @@ -72,6 +72,31 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) return rdev_mmap(&fh.data, 0, fsize); } +void *cbfs_locate_file_in_region(const char *region_name, const char *file_name, + uint32_t file_type, size_t *file_size) +{ + struct region_device rdev; + struct cbfsf fh; + + if (file_size != NULL) + *file_size = 0; + + if (fmap_locate_area_as_rdev(region_name, &rdev) == 0) { + if (cbfs_locate(&fh, &rdev, file_name, &file_type) == 0) { + if (file_size != NULL) + *file_size = region_device_sz(&fh.data); + return rdev_mmap_full(&fh.data); + } else { + LOG("%s file not found in %s region\n", + file_name, region_name); + } + } else { + LOG("%s region not found while looking for %s\n", + region_name, file_name); + } + return NULL; +} + size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) {

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Patch set updated for coreboot: intel MMA: Enable MMA with FSP2.0
by Pratikkumar V Prajapati Nov. 30, 2016

Nov. 30, 2016

Pratikkumar V Prajapati (pratikkumar.v.prajapati(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17496 -gerrit commit 1d56cf29ace8561b118b8307afd3ebc5505197bb Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Fri Nov 18 14:36:34 2016 -0800 intel MMA: Enable MMA with FSP2.0 - Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/drivers/intel/common/Kconfig | 19 ++ src/drivers/intel/common/Makefile.inc | 19 ++ src/drivers/intel/common/include/mma.h | 55 +++++ src/drivers/intel/common/mma.c | 236 ++++++++++++++++++++ src/drivers/intel/fsp1_1/Kconfig | 6 + src/drivers/intel/fsp1_1/Makefile.inc | 2 + src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h | 25 +++ src/drivers/intel/fsp1_1/mma_core.c | 41 ++++ src/drivers/intel/fsp1_1/raminit.c | 17 +- src/drivers/intel/fsp2_0/Kconfig | 6 + src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h | 25 +++ src/drivers/intel/fsp2_0/memory_init.c | 15 ++ src/drivers/intel/fsp2_0/mma_core.c | 38 ++++ src/soc/intel/common/Kconfig | 11 - src/soc/intel/common/Makefile.inc | 2 - src/soc/intel/common/mma.c | 273 ----------------------- src/soc/intel/common/mma.h | 23 -- 18 files changed, 503 insertions(+), 312 deletions(-) diff --git a/src/drivers/intel/common/Kconfig b/src/drivers/intel/common/Kconfig new file mode 100644 index 0000000..4a57264 --- /dev/null +++ b/src/drivers/intel/common/Kconfig @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Intel Corp. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config MMA_BLOBS_PATH + string "Path to MMA blobs" + depends on MMA && ( PLATFORM_USES_FSP2_0 || PLATFORM_USES_FSP1_1 ) + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma" diff --git a/src/drivers/intel/common/Makefile.inc b/src/drivers/intel/common/Makefile.inc new file mode 100644 index 0000000..e704dcc --- /dev/null +++ b/src/drivers/intel/common/Makefile.inc @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-$(CONFIG_MMA) += mma.c +romstage-$(CONFIG_MMA) += mma.c + +CPPFLAGS_common += -I$(src)/drivers/intel/common/include diff --git a/src/drivers/intel/common/include/mma.h b/src/drivers/intel/common/include/mma.h new file mode 100644 index 0000000..9e9c96e --- /dev/null +++ b/src/drivers/intel/common/include/mma.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_H_ +#define _SOC_MMA_H_ + +#pragma pack(push, 1) + +typedef struct mma_config_param MMA_CONFIG_PARAM; +typedef struct mma_data_container MMA_DATA_CONTAINER; + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) +#include <fsp/mma_fsp20.h> +#elif IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp/mma_fsp11.h> +#else +#error "error FSP version not defined or unsupported for MMA" +#endif + +struct mma_data_container { + u32 mma_signature; // "MMAD" + u8 mma_data[0]; // Variable size, platform/run time dependent. +}; + +struct mma_config_param { + u32 MmaTestContentPtr; + u32 MmaTestContentSize; + u32 MmaTestConfigPtr; + u32 MmaTestConfigSize; + u8 MrcFastBoot; + u8 SaGv; +}; + +int find_label(const char *haystack, size_t haystack_sz, + const char *label); +int label_value(const char *haystack, size_t haystack_sz, + const char *label, char *dest, size_t dest_sz); +int setup_mma(MMA_CONFIG_PARAM *mma_cfg); +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size); + +#pragma pack(pop) + +#endif diff --git a/src/drivers/intel/common/mma.c b/src/drivers/intel/common/mma.c new file mode 100644 index 0000000..c7bcd84 --- /dev/null +++ b/src/drivers/intel/common/mma.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <mma.h> + +#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" +#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" +#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" +#define TEST_NAME_MAX_SIZE 30 +#define TEST_PARAM_MAX_SIZE 100 +#define MMA_DATA_SIGNATURE (('M' << 0) | ('M' << 8) | \ + ('A' << 16) | ('D' << 24)) +#define MMA_CBFS_REGION "COREBOOT" + +/* + * Format of the MMA test metadata file, stored under CBFS + * MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; + */ + +/* Returns index in haystack after 'LABEL=' + * string is found, < 0 on error. + */ +int find_label(const char *haystack, size_t haystack_sz, + const char *label) +{ + size_t label_sz; + size_t i; + size_t search_sz; + + label_sz = strlen(label); + + if (label_sz + 1 >= haystack_sz) + return -1; + + /* Handle '=' follow label. i.e. LABEL= */ + search_sz = haystack_sz - label_sz - 1; + for (i = 0; i < search_sz; i++) { + if (!strncmp(&haystack[i], label, label_sz)) + break; + } + + if (i == search_sz) + return -1; + + if (haystack[i + label_sz] != '=') + return -1; + + return i + label_sz + 1; +} + +/* + * Fill in value in dest field located by LABEL=. + * Returns 0 on success, < 0 on error. + */ +int label_value(const char *haystack, size_t haystack_sz, + const char *label, char *dest, size_t dest_sz) +{ + size_t val_begin; + size_t val_end; + size_t val_sz; + int val_index; + + memset(dest, 0, dest_sz); + + /* Allow for NULL termination. */ + dest_sz--; + val_index = find_label(haystack, haystack_sz, label); + if (val_index < 0) + return -1; + + val_begin = val_index; + val_end = val_begin; + val_sz = 0; + + for (val_end = val_begin; val_end < haystack_sz; val_end++) { + if (haystack[val_end] == ';') { + val_sz = val_end - val_begin; + break; + } + } + + if (val_end == haystack_sz) + return -1; + + if (dest_sz < val_sz) + return -1; + + memcpy(dest, &haystack[val_begin], val_sz); + + return 0; +} + +int setup_mma(MMA_CONFIG_PARAM *mma_cfg) +{ + void *mma_test_metadata, *mma_test_content, *mma_test_param; + size_t mma_test_metadata_file_len, mma_test_content_file_len, + mma_test_param_file_len; + char test_filename[TEST_NAME_MAX_SIZE], + test_param_filename[TEST_PARAM_MAX_SIZE]; + + printk(BIOS_DEBUG, "Entry %s\n", __func__); + + memset(&mma_cfg, 0, sizeof(mma_cfg)); + + mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION, + MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA, + &mma_test_metadata_file_len); + + if (!mma_test_metadata) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s\n", + MMA_TEST_METADATA_FILENAME); + return -1; + } + + if (label_value(mma_test_metadata, mma_test_metadata_file_len, + MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to get %s", + MMA_TEST_NAME_TAG); + return -1; + } + + if (label_value(mma_test_metadata, mma_test_metadata_file_len, + MMA_TEST_PARAM_TAG, test_param_filename, + TEST_PARAM_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to get %s", + MMA_TEST_PARAM_TAG); + return -1; + } + + printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", + test_filename, test_param_filename); + + mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION, + test_filename, CBFS_TYPE_EFI, + &mma_test_content_file_len); + if (!mma_test_content) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s.\n", + test_filename); + return -1; + } + + mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION, + test_param_filename, CBFS_TYPE_MMA, + &mma_test_param_file_len); + if (!mma_test_param) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s.\n", + test_param_filename); + return -1; + } + + mma_cfg->MmaTestContentPtr = (uintptr_t) &mma_test_content; + mma_cfg->MmaTestContentSize = mma_test_content_file_len; + mma_cfg->MmaTestConfigPtr = (uintptr_t) &mma_test_param; + mma_cfg->MmaTestConfigSize = mma_test_param_file_len; + mma_cfg->MrcFastBoot = 0x00; + mma_cfg->SaGv = 0x02; + + printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename); + printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename); + printk(BIOS_DEBUG, "MMA passing following mma_cfg\n"); + printk(BIOS_DEBUG, "mma_cfg->MmaTestContentPtr = %0x\n", + mma_cfg->MmaTestContentPtr); + printk(BIOS_DEBUG, "mma_cfg->MmaTestContentSize = %d\n", + mma_cfg->MmaTestContentSize); + printk(BIOS_DEBUG, "mma_cfg->MmaTestConfigPtr = %0x\n", + mma_cfg->MmaTestConfigPtr); + printk(BIOS_DEBUG, "mma_cfg->MmaTestConfigSize = %d\n", + mma_cfg->MmaTestConfigSize); + printk(BIOS_DEBUG, "mma_cfg->MrcFastBoot = %d\n", + mma_cfg->MrcFastBoot); + printk(BIOS_DEBUG, "mma_cfg->SaGv = %d\n", + mma_cfg->SaGv); + + return 0; +} + +static void save_mma_results_data(void *unused) +{ + const void *mma_hob = NULL; + u32 mma_hob_size; + MMA_DATA_CONTAINER *mma_data; + u32 mma_data_size = 0; + + printk(BIOS_DEBUG, "Entry %s\n", __func__); + + fsp_locate_mma_results(mma_hob, &mma_hob_size); + + if (mma_hob == NULL) { + printk(BIOS_DEBUG, + "MMA results data Hob not present\n"); + return; + } + + mma_data_size = ALIGN(mma_hob_size, 16) + + sizeof(MMA_DATA_CONTAINER); + + mma_data = cbmem_add(CBMEM_ID_MMA_DATA, mma_data_size); + + if (mma_data == NULL) { + printk(BIOS_DEBUG, + "CBMEM was not available to save the MMA data.\n"); + return; + } + + /*clear the mma_data before coping the actual data */ + memset(mma_data, 0, mma_data_size); + + printk(BIOS_DEBUG, + "Copy MMA data to CBMEM(src addr %p, dest addr %p, %u bytes)\n", + mma_hob, mma_data, mma_hob_size); + + mma_data->mma_signature = MMA_DATA_SIGNATURE; + memcpy(mma_data->mma_data, mma_hob, mma_hob_size); + + printk(BIOS_DEBUG, "Write MMA results data to cbmem success\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + save_mma_results_data, NULL); diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index cc3c0a7..38d6e23 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,10 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config MMA + bool "enable MMA (Memory Margin Analysis) support" + default n + help + Set this option to y to enable MMA (Memory Margin Analysis) support + endif #PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4ea23f3..4088293 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += romstage.c romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c @@ -39,6 +40,7 @@ ramstage-y += hob.c ramstage-y += ramstage.c ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h b/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h new file mode 100644 index 0000000..df22de7 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_FSP11_H_ +#define _SOC_MMA_FSP11_H_ + +#include <fsp/soc_binding.h> + +typedef struct mma_config_param MMA_CONFIG_PARAM; + +void update_memory_params_for_mma(MEMORY_INIT_UPD *memory_upd, + MMA_CONFIG_PARAM *mma_cfg); +#endif diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c new file mode 100644 index 0000000..8e83a00 --- /dev/null +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <mma.h> + +#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ + { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } + +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size) +{ + void *mma_hob_start; + const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; + + mma_hob_start = get_first_guid_hob(&mma_results_guid); + mma_hob = GET_GUID_HOB_DATA(mma_hob_start); + *mma_hob_size = GET_HOB_LENGTH(mma_hob); +} + +void update_memory_params_for_mma(MEMORY_INIT_UPD *memory_upd, + MMA_CONFIG_PARAM *mma_cfg) +{ + memory_upd->MmaTestContentPtr = mma_cfg->MmaTestContentPtr; + memory_upd->MmaTestContentSize = mma_cfg->MmaTestContentSize; + memory_upd->MmaTestConfigPtr = mma_cfg->MmaTestConfigPtr; + memory_upd->MmaTestConfigSize = mma_cfg->MmaTestConfigSize; + memory_upd->MrcFastBoot = 0x00; + memory_upd->SaGv = 0x02; +} diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index eca8934..019eeae 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -21,7 +21,7 @@ #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> -#include <soc/intel/common/mma.h> +#include <mma.h> #include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> @@ -55,6 +55,9 @@ void raminit(struct romstage_params *params) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif +#if IS_ENABLED(CONFIG_MMA) + MMA_CONFIG_PARAM mma_cfg; +#endif /* * Find and copy the UPD region to the stack so the platform can modify @@ -101,8 +104,16 @@ void raminit(struct romstage_params *params) soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); - if (IS_ENABLED(CONFIG_MMA)) - setup_mma(&memory_init_params); + if (IS_ENABLED(CONFIG_MMA)) { + if (setup_mma(&mma_cfg)) + printk(BIOS_DEBUG, "%s", + "MMA set up failed, not updating memory param\n"); + else { + update_memory_params_for_mma(&memory_init_params, + &mma_cfg); + printk(BIOS_DEBUG, "MMA set up successfully\n"); + } + } post_code(0x36); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4f40c3f..2667728 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -100,4 +100,10 @@ config FSP2_0_USES_TPM_MRC_HASH default n select VBOOT_HAS_REC_HASH_SPACE +config MMA + bool "Enable MMA (Memory Margin Analysis) support for Intel Core" + default n + help + Set this option to y to enable MMA (Memory Margin Analysis) support + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..ad654b9 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -24,6 +24,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c ramstage-y += graphics.c @@ -36,6 +37,7 @@ ramstage-y += silicon_init.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +ramstage-$(CONFIG_MMA) += mma_core.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h b/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h new file mode 100644 index 0000000..efaedd8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_FSP20_H_ +#define _SOC_MMA_FSP20_H_ + +#include <fsp/soc_binding.h> + +typedef struct mma_config_param MMA_CONFIG_PARAM; + +void update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + MMA_CONFIG_PARAM *mma_cfg); +#endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..56e62f7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -22,6 +22,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> +#include <mma.h> #include <program_loading.h> #include <reset.h> #include <romstage_handoff.h> @@ -293,6 +294,9 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_memory_init_fn fsp_raminit; FSPM_UPD fspm_upd, *upd; FSPM_ARCH_UPD *arch_upd; +#if IS_ENABLED(CONFIG_MMA) + MMA_CONFIG_PARAM mma_cfg; +#endif post_code(0x34); @@ -318,6 +322,17 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd); + if (IS_ENABLED(CONFIG_MMA)) { + if (setup_mma(&mma_cfg)) + printk(BIOS_DEBUG, "%s", + "MMA set up failed, not updating memory param\n"); + else { + update_memory_params_for_mma(&(fspm_upd.FspmConfig), + &mma_cfg); + printk(BIOS_DEBUG, "MMA set up successfully\n"); + } + } + /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c new file mode 100644 index 0000000..47421a9 --- /dev/null +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <mma.h> + +static const uint8_t mma_results_uuid[16] = { 0x28, 0xe9, 0xf4, 0x08, + 0x5f, 0x0f, 0xd4, 0x46, + 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 }; + +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size) +{ + mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid, + mma_hob_size); +} + +void update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + MMA_CONFIG_PARAM *mma_cfg) +{ + memory_cfg->MmaTestContentPtr = mma_cfg->MmaTestContentPtr; + memory_cfg->MmaTestContentSize = mma_cfg->MmaTestContentSize; + memory_cfg->MmaTestConfigPtr = mma_cfg->MmaTestConfigPtr; + memory_cfg->MmaTestConfigSize = mma_cfg->MmaTestConfigSize; + memory_cfg->MrcFastBoot = 0x00; + memory_cfg->SaGv = 0x02; +} diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 5d8bf66..fb4b3d4 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -78,17 +78,6 @@ config SOC_INTEL_COMMON_LPSS_I2C_DEBUG Enable debug output for I2C transactions. This can be useful when debugging I2C drivers. -config MMA - bool "enable MMA (Memory Margin Analysis) support" - default n - help - Set this option to y to enable MMA (Memory Margin Analysis) support - -config MMA_BLOBS_PATH - string "Path to MMA blobs" - depends on MMA - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma" - config ADD_VBT_DATA_FILE bool "Add a Video Bios Table (VBT) binary to CBFS" help diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..7cf32bf 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -12,7 +12,6 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c -romstage-$(CONFIG_MMA) += mma.c postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c @@ -24,7 +23,6 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c -ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c deleted file mode 100644 index 87d8e5c..0000000 --- a/src/soc/intel/common/mma.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <bootstate.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <lib.h> -#include "mma.h" -#include <soc/romstage.h> -#include <string.h> -#include <fmap.h> - -#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" -#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" -#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" -#define MMA_CBFS_REGION "COREBOOT" -#define TEST_NAME_MAX_SIZE 30 -#define TEST_PARAM_MAX_SIZE 100 -#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ - { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } -#define MMA_DATA_SIGNATURE (('M'<<0)|('M'<<8)|('A'<<16)|('D'<<24)) - -struct mma_data_container { - u32 mma_signature; // "MMAD" - u8 mma_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - -/* -Format of the MMA test metadata file, stored under CBFS -MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; -*/ - -/* Returns index in haystack after 'LABEL=' string is found, < 0 on error. */ -static int find_label(const char *haystack, size_t haystack_sz, - const char *label) -{ - size_t label_sz; - size_t i; - size_t search_sz; - - label_sz = strlen(label); - - if (label_sz + 1 >= haystack_sz) - return -1; - - /* Handle '=' follow label. i.e. LABEL= */ - search_sz = haystack_sz - label_sz - 1; - for (i = 0; i < search_sz; i++) { - if (!strncmp(&haystack[i], label, label_sz)) - break; - } - - if (i == search_sz) - return -1; - - if (haystack[i + label_sz] != '=') - return -1; - - return i + label_sz + 1; -} -/* - * Fill in value in dest field located by LABEL=. - * Returns 0 on success, < 0 on error. - */ -static int label_value(const char *haystack, size_t haystack_sz, - const char *label, char *dest, size_t dest_sz) -{ - size_t val_begin; - size_t val_end; - size_t val_sz; - int val_index; - - memset(dest, 0, dest_sz); - - /* Allow for NULL termination. */ - dest_sz--; - val_index = find_label(haystack, haystack_sz, label); - if (val_index < 0) - return -1; - - val_begin = val_index; - val_end = val_begin; - val_sz = 0; - - for (val_end = val_begin; val_end < haystack_sz; val_end++) { - if (haystack[val_end] == ';') { - val_sz = val_end - val_begin; - break; - } - } - - if (val_end == haystack_sz) - return -1; - - if (dest_sz < val_sz) - return -1; - - memcpy(dest, &haystack[val_begin], val_sz); - - return 0; -} - -static void *cbfs_locate_file_in_region(const char *region_name, const char *file_name, - uint32_t file_type, uint32_t *file_size) -{ - struct region_device rdev; - struct cbfsf fh; - - if (file_size != NULL) - *file_size = 0; - - if (fmap_locate_area_as_rdev(region_name, &rdev) == 0) { - if (cbfs_locate(&fh, &rdev, file_name, &file_type) == 0) { - if (file_size != NULL) - *file_size = region_device_sz(&fh.data); - return rdev_mmap_full(&fh.data); - } else - printk(BIOS_DEBUG, "%s file not found in %s region\n", - file_name, region_name); - } else - printk(BIOS_DEBUG,"%s region not found while looking for %s\n", region_name, - file_name); - - return NULL; -} - -void setup_mma(MEMORY_INIT_UPD *memory_params) -{ - void *mma_test_metadata, *mma_test_content, *mma_test_param; - size_t mma_test_metadata_file_len, mma_test_content_file_len, - mma_test_param_file_len; - char test_filename[TEST_NAME_MAX_SIZE], - test_param_filename[TEST_PARAM_MAX_SIZE]; - - printk(BIOS_DEBUG, "Entry setup_mma\n"); - - memory_params->MmaTestContentPtr = 0; - memory_params->MmaTestContentSize = 0; - memory_params->MmaTestConfigPtr = 0; - memory_params->MmaTestConfigSize = 0; - - mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA, - &mma_test_metadata_file_len); - - if (!mma_test_metadata) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s\n", - MMA_TEST_METADATA_FILENAME); - return; - } - - if (label_value(mma_test_metadata, mma_test_metadata_file_len, - MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", - MMA_TEST_NAME_TAG); - return; - } - - if (label_value(mma_test_metadata, mma_test_metadata_file_len, - MMA_TEST_PARAM_TAG, test_param_filename, - TEST_PARAM_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", - MMA_TEST_PARAM_TAG); - return; - } - - printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", - test_filename, test_param_filename); - - mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_filename, CBFS_TYPE_EFI, - &mma_test_content_file_len); - if (!mma_test_content) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", - test_filename); - return; - } - - mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_param_filename, CBFS_TYPE_MMA, - &mma_test_param_file_len); - if (!mma_test_param) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", - test_param_filename); - return; - } - - memory_params->MmaTestContentPtr = (uintptr_t) mma_test_content; - memory_params->MmaTestContentSize = mma_test_content_file_len; - memory_params->MmaTestConfigPtr = (uintptr_t) mma_test_param; - memory_params->MmaTestConfigSize = mma_test_param_file_len; - memory_params->MrcFastBoot = 0x00; - memory_params->SaGv = 0x02; - - printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename); - printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename); - printk(BIOS_DEBUG, "MMA passing following memory_params\n"); - printk(BIOS_DEBUG, "memory_params->MmaTestContentPtr = %0x\n", - memory_params->MmaTestContentPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestContentSize = %d\n", - memory_params->MmaTestContentSize); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigPtr = %0x\n", - memory_params->MmaTestConfigPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigSize = %d\n", - memory_params->MmaTestConfigSize); - printk(BIOS_DEBUG, "memory_params->MrcFastBoot = %d\n", - memory_params->MrcFastBoot); - printk(BIOS_DEBUG, "memory_params->SaGv = %d\n", - memory_params->SaGv); - - printk(BIOS_DEBUG, "MMA setup successfully\n"); -} - -static void save_mma_results_data(void *unused) -{ - void *mma_results_hob; - u32 mma_hob_size; - u32 *mma_hob_data; - struct mma_data_container *mma_data; - int cbmem_size; - - const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; - - printk(BIOS_DEBUG, "Entry save_mma_results_data MMA save data.\n"); - - mma_results_hob = get_first_guid_hob(&mma_results_guid); - if (mma_results_hob == NULL) { - printk(BIOS_DEBUG, - "MMA results data Hob not present\n"); - return; - } - - mma_hob_data = GET_GUID_HOB_DATA(mma_results_hob); - mma_hob_size = GET_HOB_LENGTH(mma_results_hob); - cbmem_size = ALIGN(mma_hob_size, 16) + - sizeof(struct mma_data_container); - mma_data = cbmem_add(CBMEM_ID_MMA_DATA, cbmem_size); - - if (mma_data == NULL) { - printk(BIOS_DEBUG, - "CBMEM was not available to save the MMA data.\n"); - return; - } - - /*clear the mma_data before coping the actual data */ - memset(mma_data, 0, cbmem_size); - - printk(BIOS_DEBUG, - "Copy MMA DATA to HOB(src addr %p, dest addr %p, %u bytes)\n", - mma_hob_data, mma_data, mma_hob_size); - - mma_data->mma_signature = MMA_DATA_SIGNATURE; - memcpy(mma_data->mma_data, mma_hob_data, mma_hob_size); - - printk(BIOS_DEBUG, "write MMA results data to cbmem success\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - save_mma_results_data, NULL); diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h deleted file mode 100644 index f1c91e2..0000000 --- a/src/soc/intel/common/mma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MMA_H_ -#define _SOC_MMA_H_ - -#include <fsp/soc_binding.h> - -void setup_mma(MEMORY_INIT_UPD *memory_params); - -#endif

1 0

Patch set updated for coreboot: mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake)
by Brenton Dong Nov. 30, 2016

Nov. 30, 2016

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065 -gerrit commit 329f0028256fde1b5c5e8228244affbd60575cbf Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:40:39 2016 -0700 mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake) Leaf Hill CRB is an Intel Customer Reference Board with ApolloLake silicon and LPDDR4 Down. Verified on Intel Leaf Hill CRB and confirmed to boot using Intel UEFI Payload and Yocto Linux. Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++ src/mainboard/intel/leafhill/Kconfig.name | 3 + src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++ src/mainboard/intel/leafhill/acpi_tables.c | 14 +++ src/mainboard/intel/leafhill/board.h | 36 ++++++++ src/mainboard/intel/leafhill/board_info.txt | 6 ++ src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++ src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++ src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++ 12 files changed, 466 insertions(+) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig new file mode 100644 index 0000000..462e458 --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_LEAFHILL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/leafhill + +config MAINBOARD_PART_NUMBER + string + default "LeafHill" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config IBBL_ROM_SIZE + hex + default 0x10000 + +config IBBM_ROM_SIZE + hex + default 0x62000 + +config OBB_ROM_SIZE + hex + default 0x100000 + +config OBB_ROM_BASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name new file mode 100644 index 0000000..72664cd --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_LEAFHILL + bool "LeafHill" + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc new file mode 100644 index 0000000..271b20a --- /dev/null +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -0,0 +1,64 @@ +#Nothing here yet + +MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd + +IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE)) +IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE) +IBBL_FMAP_BIOS_BASE := 0 +IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE) +IBBL_FMAP_FMAP_BASE := 0 +IBBL_FMAP_FMAP_SIZE := 0x100 +IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE) +IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE)) + +$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbl_fmap.fmap +$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@ + + +IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE)) +IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE)) +IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE) +IBBM_FMAP_BIOS_BASE := 0 +IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE) +IBBM_FMAP_FMAP_BASE := 0 +IBBM_FMAP_FMAP_SIZE := 0x100 +IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE) +IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE)) + +$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbm_fmap.fmap +$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@ + +# brenton: changed this to headerromstage-y += brd_gpio.c diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/intel/leafhill/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h new file mode 100644 index 0000000..90e2a10 --- /dev/null +++ b/src/mainboard/intel/leafhill/board.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOARD_H_ +#define _SOC_BOARD_H_ + +typedef struct { + uint32_t VendorDeviceId; //Codec Vendor/Device ID + uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev + uint8_t SdiNo; //SDI number, 0xFF matches any SDI. + uint16_t DataDwords; //Number of data DWORDs following header + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} BL_HDA_VERB_TABLE_HEADER; + +typedef struct { + BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} BL_HDAUDIO_VERB_TABLE; + +void config_board_gpio(void); + + +#endif diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100644 index 0000000..3cd47a7 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/mmio.h> +#include <soc/gpio.h> +#include "board.h" + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..746aaf3 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,56 @@ +chip soc/intel/apollolake + + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl new file mode 100644 index 0000000..53a7b0f --- /dev/null +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd new file mode 100644 index 0000000..06e905c --- /dev/null +++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd new file mode 100644 index 0000000..d0d0720 --- /dev/null +++ b/src/mainboard/intel/leafhill/obb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@0x200000 0x100000 { + BIOS@0 0x100000 { + FMAP@0 0x100 + COREBOOT(CBFS)@0x100 1048320 + } +} \ No newline at end of file diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c new file mode 100644 index 0000000..256570a --- /dev/null +++ b/src/mainboard/intel/leafhill/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "board.h" +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + mupd->FspmConfig.Package = 0x1; + mupd->FspmConfig.Profile = 0xB; + mupd->FspmConfig.MemoryDown = 0x1; + mupd->FspmConfig.DDR3LPageSize = 0x0; + mupd->FspmConfig.DDR3LASR = 0x0; + mupd->FspmConfig.ScramblerSupport = 0x1; + mupd->FspmConfig.ChannelHashMask = 0x36; + mupd->FspmConfig.SliceHashMask = 0x9; + mupd->FspmConfig.InterleavedMode = 0x2; + mupd->FspmConfig.ChannelsSlicesEnable = 0x0; + mupd->FspmConfig.MinRefRate2xEnable = 0x0; + mupd->FspmConfig.DualRankSupportEnable = 0x1; + mupd->FspmConfig.RmtMode = 0x0; + mupd->FspmConfig.MemorySizeLimit = 0x1800; + mupd->FspmConfig.LowMemoryMaxValue = 0x0; + mupd->FspmConfig.DisableFastBoot = 0x0; + mupd->FspmConfig.HighMemoryMaxValue = 0x0; + mupd->FspmConfig.DIMM0SPDAddress = 0x0; + mupd->FspmConfig.DIMM1SPDAddress = 0x0; + mupd->FspmConfig.Ch0_RankEnable = 0x3; + mupd->FspmConfig.Ch0_DeviceWidth = 0x1; + mupd->FspmConfig.Ch0_DramDensity = 0x2; + mupd->FspmConfig.Ch0_Option = 0x3; + mupd->FspmConfig.Ch0_OdtConfig = 0x0; + mupd->FspmConfig.Ch0_TristateClk1 = 0x0; + mupd->FspmConfig.Ch0_Mode2N = 0x0; + mupd->FspmConfig.Ch0_OdtLevels = 0x0; + mupd->FspmConfig.Ch1_RankEnable = 0x3; + mupd->FspmConfig.Ch1_DeviceWidth = 0x1; + mupd->FspmConfig.Ch1_DramDensity = 0x2; + mupd->FspmConfig.Ch1_Option = 0x3; + mupd->FspmConfig.Ch1_OdtConfig = 0x0; + mupd->FspmConfig.Ch1_TristateClk1 = 0x0; + mupd->FspmConfig.Ch1_Mode2N = 0x0; + mupd->FspmConfig.Ch1_OdtLevels = 0x0; + mupd->FspmConfig.Ch2_RankEnable = 0x3; + mupd->FspmConfig.Ch2_DeviceWidth = 0x1; + mupd->FspmConfig.Ch2_DramDensity = 0x2; + mupd->FspmConfig.Ch2_Option = 0x3; + mupd->FspmConfig.Ch2_OdtConfig = 0x0; + mupd->FspmConfig.Ch2_TristateClk1 = 0x0; + mupd->FspmConfig.Ch2_Mode2N = 0x0; + mupd->FspmConfig.Ch2_OdtLevels = 0x0; + mupd->FspmConfig.Ch3_RankEnable = 0x3; + mupd->FspmConfig.Ch3_DeviceWidth = 0x1; + mupd->FspmConfig.Ch3_DramDensity = 0x2; + mupd->FspmConfig.Ch3_Option = 0x3; + mupd->FspmConfig.Ch3_OdtConfig = 0x0; + mupd->FspmConfig.Ch3_TristateClk1 = 0x0; + mupd->FspmConfig.Ch3_Mode2N = 0x0; + mupd->FspmConfig.Ch3_OdtLevels = 0x0; + mupd->FspmConfig.RmtCheckRun = 0x0; + mupd->FspmConfig.MrcDataSaving = 0x1; + mupd->FspmConfig.MrcFastBoot = 0x1; + + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + mupd->FspmConfig.MsgLevelMask = 0x0; + + /* Request FSP to load the coreboot primary CBFS */ + mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE; + strcpy((char *)mupd->FspmConfig.OemFileName, "OBB"); + +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: add Multiple FMAP build
by Brenton Dong Nov. 30, 2016

Nov. 30, 2016

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17064 -gerrit commit 7e462257bcac719c4d951978e181c23de468d1d1 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:21:12 2016 -0700 soc/intel/apollolake: add Multiple FMAP build Multiple coreboot binaries with separate FMAPs and separate CBFSs allow coreboot to run separate stages from different regions (SRAM, CAR, Mem). When enabling Multiple FMAP, 3 Coreboot Images will be created. IBBL: Contains bootblock, CAR init (FSP-T) and hands off to IBBM. IBBM: Contains romstage, mem init (FSP-M) and postcar. OBB: Contains ramstage, silicon init (FSP-S), and the rest of the components in the original single coreboot.rom file. This is the same image as the original coreboot.rom minus the components moved to the IBBL and IBBM. Add functions to select which region cbfs files will be loaded from. Verified on Intel Leaf Hill CRB and confirmed that the coreboot builds 3 separate coreboot files which can be loaded and booted. Verified that other ApolloLake projects can build correctly with this option disabled. Change-Id: Iab3c353b65e1e0fc9d04fcee6a82a330927db41e Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- Makefile.inc | 47 ++++++++++ src/arch/x86/Makefile.inc | 2 + src/drivers/intel/fsp2_0/Makefile.inc | 5 + src/soc/intel/apollolake/Kconfig | 6 ++ src/soc/intel/apollolake/Makefile.inc | 4 + src/soc/intel/apollolake/bootblock/bootblock.c | 57 ++++++++++++ src/soc/intel/apollolake/chip.c | 9 +- src/soc/intel/apollolake/include/soc/bootregion.h | 28 ++++++ src/soc/intel/apollolake/include/soc/cse.h | 30 ++++++ src/soc/intel/apollolake/include/soc/mmio.h | 35 +++++++ src/soc/intel/apollolake/mmap_boot.c | 2 + src/soc/intel/apollolake/mmap_boot_cse.c | 53 +++++++++++ src/soc/intel/apollolake/postcar.c | 44 +++++++++ src/soc/intel/apollolake/romstage.c | 108 ++++++++++++++++++++++ 14 files changed, 429 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..9e25883 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -826,11 +826,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) +endif # ifeq ($(CONFIG_MULTIPLE_FMAP),y) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -865,6 +867,49 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif + +ifeq ($(CONFIG_MULTIPLE_FMAP),y) + +.PHONY:$(obj)/coreboot_ibbl.rom +$(obj)/coreboot_ibbl.rom: $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(obj)/ibbl_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbl_fmap.fmap -r $(shell cat $(obj)/ibbl_fmap.desc) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_T_FILE)) \ + -n blobs/fspt.bin -t fsp -y -b 0xC0 + mv $@.tmp $@ + @printf "\ncoreboot IBBL image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +.PHONY:$(obj)/coreboot_ibbm.rom +$(obj)/coreboot_ibbm.rom: $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(objcbfs)/romstage.elf \ + $(objcbfs)/postcar.elf \ + $(obj)/ibbm_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbm_fmap.fmap -r $(shell cat $(obj)/ibbm_fmap.desc) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/romstage.elf \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(CBFSTOOL_PRE_OPTS) -b 0 + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_M_FILE)) \ + -n blobs/fspm.bin -t fsp -y + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/postcar.elf \ + -n $(CONFIG_CBFS_PREFIX)/postcar + mv $@.tmp $@ + @printf "\ncoreboot IBBM image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +coreboot: $(obj)/coreboot_ibbl.rom $(obj)/coreboot_ibbm.rom + +endif # ifneq ($(CONFIG_MULTIPLE_FMAP),y) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -892,6 +937,7 @@ endif @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -924,6 +970,7 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +endif # CONFIG_MULTIPLE_FMAP cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..fc7eb5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -300,10 +300,12 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ # Add postcar to CBFS +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage $(CONFIG_CBFS_PREFIX)/postcar-compression := none +endif #CONFIG_MULTIPLE_FMAP ############################################################################### # ramstage diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 175e20c..02558b4 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -46,6 +46,8 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifneq ($(CONFIG_MULTIPLE_FMAP),y) + cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(CONFIG_FSP_T_CBFS)-type := fsp @@ -53,6 +55,9 @@ $(CONFIG_FSP_T_CBFS)-type := fsp cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp + +endif #CONFIG_MULTIPLE_FMAP + ifeq ($(CONFIG_FSP_M_XIP),y) $(CONFIG_FSP_M_CBFS)-options := --xip endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c178c3..eeba42a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -81,6 +81,12 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MULTIPLE_FMAP + depends on FSP_CAR + bool + help + Enable build with mulitple coreboot images and each will has its own fmap. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9ae5569..c3b3ebf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c +bootblock-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c @@ -37,6 +38,7 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c +romstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c @@ -65,6 +67,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c +ramstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c ramstage-y += mmap_boot.c ramstage-y += p2sb.c ramstage-y += uart.c @@ -81,6 +84,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += memmap.c +postcar-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..22a4d44 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -14,6 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <string.h> #include <arch/cpu.h> #include <bootblock_common.h> #include <cpu/x86/mtrr.h> @@ -31,6 +32,53 @@ #include <spi-generic.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm0(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_num; + uint32_t state; + msr_t msr; + + /* Request data from CSE */ + host_to_cse = (ibbm_size << 4) | 0xC0000000; + CSE_HOST2CSE = host_to_cse; + + /* Wait for response */ + do { + cse_to_host = CSE_CSE2HOST; + chunk_num = (cse_to_host >> 28) & 3; + } while (!chunk_num); + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* + * The 1st 128K should have been loaded into SRAM now + * However, since the top 32K IBBL is still cached, we can only read + * (128-32)K at this moment. The remaining will be read in romstage. + */ + memcpy((void *)ibbm_base, (void *)(~CSE_IBB_SRAM_SIZE + 1), + CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE); + + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + the temporary memory */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; @@ -92,6 +140,15 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) enable_cmos_upper_bank(); +#if CONFIG_MULTIPLE_FMAP + /* Loading IBBM into CAR */ + load_ibbm0(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE, CONFIG_IBBM_ROM_SIZE); + + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); +#endif //CONFIG_MULTIPLE_FMAP + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992..0a184eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,9 +35,12 @@ #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/northbridge.h> - #include "chip.h" +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif /* CONFIG_MULTIPLE_FMAP */ + static void *vbt; static struct region_device vbt_rdev; @@ -267,6 +270,10 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_OBB); +#endif //CONFIG_MULTIPLE_FMAP + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ diff --git a/src/soc/intel/apollolake/include/soc/bootregion.h b/src/soc/intel/apollolake/include/soc/bootregion.h new file mode 100644 index 0000000..dde562a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootregion.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_BOOT_RGN_H_ +#define _SOC_LEAFHILL_BOOT_RGN_H_ + +#define BOOT_REGION_IBBL 0 +#define BOOT_REGION_IBBM 1 +#define BOOT_REGION_OBB 2 + +/* Set current active boot region */ +void set_boot_region(int region_id); + +#endif /* _SOC_LEAFHILL_BOOT_RGN_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h new file mode 100644 index 0000000..ed2b136 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_CSE_H_ +#define _SOC_LEAFHILL_CSE_H_ + +#define HOST2CSE 0x70 +#define CSE2HOST 0x60 +#define CSE_IBB_SRAM_SIZE 0x20000 + +#define CSE_CFG_BASE (CONFIG_MMCONF_BASE_ADDRESS + 0x78000) +#define CSE_VIDDID (*(volatile int32_t *)CSE_CFG_BASE) +#define CSE_HOST2CSE (*(volatile int32_t *)(CSE_CFG_BASE + HOST2CSE)) +#define CSE_CSE2HOST (*(volatile int32_t *)(CSE_CFG_BASE + CSE2HOST)) + +#endif /* _SOC_LEAFHILL_CSE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/mmio.h b/src/soc/intel/apollolake/include/soc/mmio.h new file mode 100644 index 0000000..674e071 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/mmio.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMIO_H_ +#define _SOC_MMIO_H_ + + +#define MmioRead32(x) (*(volatile uint32_t *)(unsigned int)(x)) +#define MmioWrite32(x, y) (*(volatile uint32_t *)(unsigned int)(x) = y) +#define MmioRead16(x) (*(volatile uint16_t *)(unsigned int)(x)) +#define MmioWrite16(x, y) (*(volatile uint16_t *)(unsigned int)(x) = y) +#define MmioRead8(x) (*(volatile uint8_t *)(unsigned int)(x)) +#define MmioWrite8(x, y) (*(volatile uint8_t *)(unsigned int)(x) = y) + +#define PCIE_MMIO(Bus, Device, Function, Register) \ + ((unsigned int)CONFIG_MMCONF_BASE_ADDRESS + \ + (unsigned int)(Bus << 20) + \ + (unsigned int)(Device << 15) + \ + (unsigned int)(Function << 12) + \ + (unsigned int)(Register) \ + ) + +#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..994f7b8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -113,6 +113,7 @@ static void bios_mmap_init(void) car_set_var(bios_size, size); } +#if !CONFIG_MULTIPLE_FMAP const struct region_device *boot_device_ro(void) { bios_mmap_init(); @@ -122,6 +123,7 @@ const struct region_device *boot_device_ro(void) return &real_dev_ptr->rdev; } +#endif //CONFIG_MULTIPLE_FMAP static int iafw_boot_region_properties(struct cbfs_props *props) { diff --git a/src/soc/intel/apollolake/mmap_boot_cse.c b/src/soc/intel/apollolake/mmap_boot_cse.c new file mode 100644 index 0000000..d5b4526 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot_cse.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/bootregion.h> +#include <soc/intel/common/nvm.h> +#include <arch/early_variables.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base(x) (void *)(uintptr_t)(-(int32_t)(x)) +#define IBBL_ROM_BASE rom_base(CONFIG_IBBL_ROM_SIZE) +#define IBBM_ROM_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + - CONFIG_IBBM_ROM_SIZE) + +static int curr_boot_region CAR_GLOBAL; + +static const struct mem_region_device boot_dev[] = { + MEM_REGION_DEV_RO_INIT(IBBL_ROM_BASE, CONFIG_IBBL_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(IBBM_ROM_BASE, CONFIG_IBBM_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(CONFIG_RAMTOP, CONFIG_ROM_SIZE) +}; + +#if CONFIG_MULTIPLE_FMAP +const struct region_device *boot_device_ro(void) +{ + return &boot_dev[car_get_var(curr_boot_region)].rdev; +} +#endif //CONFIG_MULTIPLE_FMAP + +void set_boot_region(int rgn_idx) +{ + if (rgn_idx < sizeof(boot_dev)/sizeof(boot_dev[0])) + car_set_var(curr_boot_region, rgn_idx); +} diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100644 index 0000000..7c24fe9 --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif + +void post_car_main(void) +{ +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_IBBM); + temp_ram_exit(); + set_boot_region(BOOT_REGION_OBB); +#else + temp_ram_exit(); +#endif + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +} diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..69d7273 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -41,6 +41,12 @@ #include <string.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <cpu/x86/msr.h> +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + static struct chipset_power_state power_state CAR_GLOBAL; /* High Performance Event Timer Configuration */ @@ -100,6 +106,92 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm1(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t state; + uint32_t size; + uint8_t ring_idx; + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_idx; + uint32_t chunk_size; + uint32_t chunk_num; + uint32_t ibb_remaining; + uint8_t *src; + uint8_t *dst; + uint8_t *ptr; + msr_t msr; + + /* Set IBBL cache to UC */ + msr = rdmsr(0x202); + msr.lo &= ~0x0f; + wrmsr(0x202, msr); + + /* Init variables */ + size = CONFIG_IBBL_ROM_SIZE; + dst = (uint8_t *)ibbm_base; + src = (uint8_t *)(~CONFIG_IBBL_ROM_SIZE + 1); + memcpy(dst, src, size); + + cse_to_host = CSE_CSE2HOST; + host_to_cse = CSE_HOST2CSE; + chunk_num = (cse_to_host >> 28) & 3; + if (chunk_num == 3) + chunk_num = 4; + chunk_size = CSE_IBB_SRAM_SIZE / chunk_num; + chunk_idx = chunk_num; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~0x0f) | (cse_to_host & 0x0f); + CSE_HOST2CSE = host_to_cse; + + ibb_remaining = ibbm_size - size; + while (ibb_remaining > 0) { + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* Calculate ring index */ + ring_idx = (uint8_t)(chunk_idx % chunk_num); + if (state & (1 << ring_idx)) { + /* Calculate source and dest. address in ring buffer */ + src += chunk_size; + dst += chunk_size; + if (src == 0) + src = (uint8_t *)(~CSE_IBB_SRAM_SIZE + 1); + if (ibb_remaining < chunk_size) + size = ibb_remaining; + else + size = chunk_size; + + /* Move data from SRAM into temporary memory */ + memcpy(dst, src, size); + ibb_remaining -= size; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~(1 << ring_idx)) | + (cse_to_host & (1 << ring_idx)); + CSE_HOST2CSE = host_to_cse; + + chunk_idx++; + } + } + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + * the temporary memory + */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -109,6 +201,10 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; +#if CONFIG_MULTIPLE_FMAP + uint32_t ibbm_base; + uint32_t ibbm_loaded; +#endif //CONFIG_MULTIPLE_FMAP timestamp_add_now(TS_START_ROMSTAGE); @@ -117,6 +213,18 @@ asmlinkage void car_stage_entry(void) console_init(); +#if CONFIG_MULTIPLE_FMAP + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); + + /* load the remaining IBBM */ + ibbm_loaded = CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE; + ibbm_base = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE; + load_ibbm1(ibbm_base + ibbm_loaded, + CONFIG_IBBM_ROM_SIZE - ibbm_loaded); +#endif //CONFIG_MULTIPLE_FMAP + s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB))

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Patch set updated for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
by Brenton Dong Nov. 30, 2016

Nov. 30, 2016

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063 -gerrit commit 50fbe9e331d0deb1736019a24ae3a1cf316dc7c7 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 13:57:54 2016 -0700 soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/arch/x86/exit_car.S | 5 +- src/arch/x86/postcar.c | 8 +- src/soc/intel/apollolake/Makefile.inc | 14 ++- .../intel/apollolake/bootblock/cache_as_ram_fsp.S | 112 +++++++++++++++++++++ src/soc/intel/apollolake/exit_car_fsp.S | 47 +++++++++ 5 files changed, 178 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 5c62c92..61287d2 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -19,7 +19,8 @@ .section ".module_parameters", "aw", @progbits /* stack_top indicates the stack to pull MTRR information from. */ -stack_top: +.global post_car_stack_top +post_car_stack_top: .long 0 .long 0 @@ -38,7 +39,7 @@ _start: invd /* Set up new stack. */ - mov stack_top, %esp + mov post_car_stack_top, %esp /* * Honor variable MTRR information pushed on the stack with the diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index c4c9cda..34a4335 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -22,15 +22,15 @@ void main(void) { + /* Call TempRamExit FSP API if enabled. */ + if (IS_ENABLED(CONFIG_FSP_CAR)) + fsp_temp_ram_exit(); + console_init(); /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); - /* Call TempRamExit FSP API if enabled. */ - if (IS_ENABLED(CONFIG_FSP_CAR)) - fsp_temp_ram_exit(); - /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..9ae5569 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_fsp.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,18 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_fsp.S +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S new file mode 100644 index 0000000..b6bdd45 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +#define FSP_HDR_OFFSET 0x94 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add FSP_HDR_OFFSET, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ + add 0x1c(%ebx), %eax /* add the FSP ImageBase */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +/* + * If the TempRamInit API is successful, then when returning, the ECX and + * EDX registers will point to the temporary but writeable memory range + * available to the bootloader where ECX is the start and EDX is the end of + * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more + * information. + * + * Return Values: + * EAX | Return Status + * ECX | Temporary Memory Start + * EDX | Temporary Memory End + * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call + */ + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S new file mode 100644 index 0000000..32c276c --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_fsp.S @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching which can be overwritten + * after the API call. More info can be found in the Apollo Lake FSP + * Integration Guide included with the FSP binary. The below + * caching settings are based on an 8MiB Flash Size given as a + * parameter to TempRamInit. + * + * TempRamExit MTRR Settings: + * 0x00000000 - 0x0009FFFF | Write Back + * 0x000C0000 - Top of Low Memory | Write Back + * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect + * 0x100000000 - Top of High Memory | Write Back + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov post_car_stack_top, %esp + + /* Call C code */ + call main

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Patch set updated for coreboot: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
by Brenton Dong Nov. 30, 2016

Nov. 30, 2016

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17062 -gerrit commit 3e443b77b91555459dba871a43c12502cea46382 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 11:35:15 2016 -0700 drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/arch/x86/postcar.c | 5 +++ src/drivers/intel/fsp2_0/Kconfig | 18 ++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 7 ++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 49 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 2 + 8 files changed, 85 insertions(+) diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index b6ae09a..c4c9cda 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -18,6 +18,7 @@ #include <main_decl.h> #include <program_loading.h> #include <soc/intel/common/util.h> +#include <fsp/util.h> void main(void) { @@ -26,6 +27,10 @@ void main(void) /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); + /* Call TempRamExit FSP API if enabled. */ + if (IS_ENABLED(CONFIG_FSP_CAR)) + fsp_temp_ram_exit(); + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3ffb402..4fa0635 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. +config FSP_T_CBFS + string "Name of FSP-T in CBFS" + depends on FSP_CAR + default "fspt.bin" + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" @@ -61,6 +66,12 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_T_FILE + string "Intel FSP-T (temp ram init) binary path and filename" + depends on FSP_CAR + help + The path and filename of the Intel FSP-M binary for this platform. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES @@ -73,6 +84,13 @@ config FSP_S_FILE help The path and filename of the Intel FSP-S binary for this platform. +config FSP_CAR + bool "Use FSP TempRamInit & TempRamExit APIs" + depends on ADD_FSP_BINARIES + default n + help + Use FSP APIs to initialize & Tear Down the Cache-As-Ram + config FSP_M_XIP bool "Is FSP-M XIP" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..175e20c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -38,11 +38,18 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +postcar-$(CONFIG_FSP_CAR) += util.c +postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS) +$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(CONFIG_FSP_T_CBFS)-type := fsp + cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 553fc52..1ba14ce 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,6 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); +void fsp_temp_ram_exit(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..c84c33e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 04f8c00..13c6ab2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(uint32_t status); +typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c new file mode 100644 index 0000000..21eb367 --- /dev/null +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> +#include <cbfs.h> + +void fsp_temp_ram_exit(void) +{ + struct fsp_header hdr; + uint32_t status; + temp_ram_exit_fn temp_ram_exit; + struct cbfsf file_desc; + struct region_device file_data; + const char *name = CONFIG_FSP_M_CBFS; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + die("FSPM not available for CAR Exit!\n"); + } + + cbfs_file_data(&file_data, &file_desc); + + if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + die("Invalid FSPM header!\n"); + + temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit); + status = temp_ram_exit(NULL); + + if (status != FSP_SUCCESS) { + printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); + die("TempRamExit returned an error!\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index e7e4f16..7453b59 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->temp_ram_init_entry = read32(raw_hdr + 48); + hdr->temp_ram_exit_entry = read32(raw_hdr + 64); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68);

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Patch set updated for coreboot: soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs
by Andrey Petrov Nov. 30, 2016

Nov. 30, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17663 -gerrit commit c031415b9ca7396a20177d334750a4f91fed31db Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 30 16:05:56 2016 -0800 soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 916d7c5..85121f0 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -49,6 +49,14 @@ static const struct reg_script core_msr_script[] = { */ REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, FEATURE_CONFIG_LOCK), + /* + * Enable ACPI PM timer emulation, which also lets microcode know + * location of ACPI_PMIO_BASE, that it turns allows other features + * to work. + */ + REG_MSR_WRITE(MSR_EMULATE_PM_TMR, + (((3579545ULL << 32) / CTC_FREQ) << 32) | EMULATE_PM_TMR_EN | + (ACPI_PMIO_BASE + R_ACPI_PM1_TMR)), REG_SCRIPT_END };

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New patch to review for coreboot: soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs
by Andrey Petrov Nov. 30, 2016

Nov. 30, 2016

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17663 -gerrit commit 2b60be5e7e3ebbb4dfe70827ed228c9ec8c27cc8 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 30 16:05:56 2016 -0800 soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUs Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 916d7c5..85121f0 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -49,6 +49,14 @@ static const struct reg_script core_msr_script[] = { */ REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, FEATURE_CONFIG_LOCK), + /* + * Enable ACPI PM timer emulation, which also lets microcode know + * location of ACPI_PMIO_BASE, that it turns allows other features + * to work. + */ + REG_MSR_WRITE(MSR_EMULATE_PM_TMR, + (((3579545ULL << 32) / CTC_FREQ) << 32) | EMULATE_PM_TMR_EN | + (ACPI_PMIO_BASE + R_ACPI_PM1_TMR)), REG_SCRIPT_END };

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