November 2016 - coreboot-gerrit

Patch set updated for coreboot: PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17546 -gerrit commit 9cd42ab7744a3541a1ee44026e9d7693a9467c9d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 20:39:56 2016 +0200 PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access Some PCI-e capability registers are located starting from 0x100, these are not accessible using the conventional PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO was selected. Thus any feature that calls pcie_ext_find_capability() depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO being enabled on the platform. In theory there can be system without MMCONF_SUPPORT, but with complete PCI Express configuration space available using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF operations here, but rely on the default PCI access method to be able to access all of the configuration space. While at it, convert to IS_ENABLED() everywhere in the source and organize Kconfig file better. With this change, AGESA and binaryPI platforms change to PCI_CFG_EXT_IO method here until MMCONF_SUPPORT_DEFAULT is activated for them. Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 33 +++++++++++++++++---------------- src/device/pciexp_device.c | 42 ++++++++++++++---------------------------- 2 files changed, 31 insertions(+), 44 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index dd31cba..fb0aaba 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -227,11 +227,6 @@ config PCIX_PLUGIN_SUPPORT depends on PCI default y -config PCIEXP_PLUGIN_SUPPORT - bool - depends on PCI - default y - config CARDBUS_PLUGIN_SUPPORT bool depends on PCI @@ -242,10 +237,16 @@ config AZALIA_PLUGIN_SUPPORT depends on PCI default n +config PCIEXP_PLUGIN_SUPPORT + bool + depends on PCI + default y + +if PCIEXP_PLUGIN_SUPPORT + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Common Clock on PCIe links. @@ -253,7 +254,6 @@ config PCIEXP_COMMON_CLOCK config PCIEXP_ASPM prompt "Enable PCIe ASPM" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable ASPM on PCIe links. @@ -261,11 +261,20 @@ config PCIEXP_ASPM config PCIEXP_CLK_PM prompt "Enable PCIe Clock Power Management" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Clock Power Management on PCIe. +config PCIEXP_L1_SUB_STATE + prompt "Enable PCIe ASPM L1 SubState" + bool + depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT) + default n + help + Detect and enable ASPM on PCIe links. + +endif # PCIEXP_PLUGIN_SUPPORT + config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI @@ -278,14 +287,6 @@ config EARLY_PCI_BRIDGE This option enables static configuration for a single pre-defined PCI bridge function on bus 0. -config PCIEXP_L1_SUB_STATE - prompt "Enable PCIe ASPM L1 SubState" - bool - depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT - default n - help - Detect and enable ASPM on PCIe links. - if EARLY_PCI_BRIDGE config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index d14ba02..7228249 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pciexp.h> -#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) { unsigned int this_cap_offset, next_cap_offset; @@ -29,10 +28,10 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) this_cap_offset = PCIE_EXT_CAP_OFFSET; do { - this_cap = pci_mmio_read_config32(dev, this_cap_offset); + this_cap = pci_read_config32(dev, this_cap_offset); next_cap_offset = this_cap >> 20; this_cap &= 0xffff; - cafe = pci_mmio_read_config32(dev, this_cap_offset + 4); + cafe = pci_read_config32(dev, this_cap_offset + 4); cafe &= 0xffff; if (this_cap == cap) return this_cap_offset; @@ -44,9 +43,7 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) return 0; } -#endif -#if CONFIG_PCIEXP_COMMON_CLOCK /* * Re-train a PCIe link */ @@ -109,9 +106,7 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, pciexp_retrain_link(root, root_cap); } } -#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ -#if CONFIG_PCIEXP_CLK_PM static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) { /* check if per port clk req is supported in device */ @@ -126,17 +121,15 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) lnkctl = lnkctl | PCI_EXP_EN_CLK_PM; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -#endif /* CONFIG_PCIEXP_CLK_PM */ -#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT) static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) { u32 reg32; - reg32 = pci_mmio_read_config32(dev, reg); + reg32 = pci_read_config32(dev, reg); reg32 &= mask; reg32 |= or; - pci_mmio_write_config32(dev, reg, reg32); + pci_write_config32(dev, reg, reg32); } static void pciexp_config_max_latency(device_t root, device_t dev) @@ -170,7 +163,7 @@ static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, unsigned int power_on_scale = (*data >> 16) & 0x3; unsigned int power_on_value = (*data >> 19) & 0x1f; - unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4); + unsigned int endp_data = pci_read_config32(dev, endp_cap + 4); unsigned int endp_L1SubStateSupport = endp_data & 0xf; unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff; unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3; @@ -200,7 +193,7 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, { device_t dev_t; unsigned char L1_ss_ok; - unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4); + unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4); unsigned int L1SubStateSupport; unsigned int comm_mode_rst_time; unsigned int power_on_scale; @@ -282,9 +275,7 @@ static void pciexp_config_L1_sub_state(device_t root, device_t dev) pciexp_L1_substate_commit(root, dev, root_cap, end_cap); } -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ -#if CONFIG_PCIEXP_ASPM /* * Determine the ASPM L0s or L1 exit latency for a link * by checking both root port and endpoint and returning @@ -371,7 +362,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap, printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } -#endif /* CONFIG_PCIEXP_ASPM */ static void pciexp_tune_dev(device_t dev) { @@ -386,25 +376,21 @@ static void pciexp_tune_dev(device_t dev) if (!root_cap) return; -#if CONFIG_PCIEXP_COMMON_CLOCK /* Check for and enable Common Clock */ - pciexp_enable_common_clock(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); -#if CONFIG_PCIEXP_CLK_PM /* Check if per port CLK req is supported by endpoint*/ - pciexp_enable_clock_power_pm(dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM)) + pciexp_enable_clock_power_pm(dev, cap); -#if CONFIG_PCIEXP_L1_SUB_STATE /* Enable L1 Sub-State when both root port and endpoint support */ - pciexp_config_L1_sub_state(root, dev); -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ + if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + pciexp_config_L1_sub_state(root, dev); -#if CONFIG_PCIEXP_ASPM /* Check for and enable ASPM */ - pciexp_enable_aspm(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) + pciexp_enable_aspm(root, root_cap, dev, cap); } void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,

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Patch set updated for coreboot: PCIEXP_ASPM: Unify code with other PCI-e tuning
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17654 -gerrit commit 9185b130d2d494ddafd37142fcd85f6318ad7a91 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:08:38 2016 +0200 PCIEXP_ASPM: Unify code with other PCI-e tuning Error reporting can be enabled together with ASPM, there is no other use for function return value. Change-Id: I58081fac0df5205a5aea65d735d34b375c2af9cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pciexp_device.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 330c7e3..d14ba02 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -325,15 +325,8 @@ static int pciexp_aspm_latency(device_t root, unsigned root_cap, /* * Enable ASPM on PCIe root port and endpoint. - * - * Returns APMC value: - * -1 = Error - * 0 = no ASPM - * 1 = L0s Enabled - * 2 = L1 Enabled - * 3 = L0s and L1 Enabled */ -static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, +static void pciexp_enable_aspm(device_t root, unsigned root_cap, device_t endp, unsigned endp_cap) { const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; @@ -369,10 +362,14 @@ static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Enable ASPM role based error reporting. */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + devcap |= PCI_EXP_DEVCAP_RBER; + pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap); } printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); - return apmc; } #endif /* CONFIG_PCIEXP_ASPM */ @@ -406,14 +403,7 @@ static void pciexp_tune_dev(device_t dev) #if CONFIG_PCIEXP_ASPM /* Check for and enable ASPM */ - enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); - - if (apmc != PCIE_ASPM_NONE) { - /* Enable ASPM role based error reporting. */ - u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); - reg32 |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); - } + pciexp_enable_aspm(root, root_cap, dev, cap); #endif }

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New patch to review for coreboot: PCIEXP_ASPM: Unify code with other PCI-e tuning
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17654 -gerrit commit 78b671035b0083ba85a6c7e3bfd83252170d4290 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:08:38 2016 +0200 PCIEXP_ASPM: Unify code with other PCI-e tuning Error reporting can be enabled together with ASPM, there is no other use for function return value. Change-Id: I58081fac0df5205a5aea65d735d34b375c2af9cd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pciexp_device.c | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 330c7e3..dcba777 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -325,15 +325,8 @@ static int pciexp_aspm_latency(device_t root, unsigned root_cap, /* * Enable ASPM on PCIe root port and endpoint. - * - * Returns APMC value: - * -1 = Error - * 0 = no ASPM - * 1 = L0s Enabled - * 2 = L1 Enabled - * 3 = L0s and L1 Enabled */ -static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, +static void pciexp_enable_aspm(device_t root, unsigned root_cap, device_t endp, unsigned endp_cap) { const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" }; @@ -369,10 +362,14 @@ static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Enable ASPM role based error reporting. */ + devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); + devcap |= PCI_EXP_DEVCAP_RBER; + write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap); } printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); - return apmc; } #endif /* CONFIG_PCIEXP_ASPM */ @@ -406,14 +403,7 @@ static void pciexp_tune_dev(device_t dev) #if CONFIG_PCIEXP_ASPM /* Check for and enable ASPM */ - enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap); - - if (apmc != PCIE_ASPM_NONE) { - /* Enable ASPM role based error reporting. */ - u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); - reg32 |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); - } + pciexp_enable_aspm(root, root_cap, dev, cap); #endif }

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New patch to review for coreboot: intel/fsp_rangeley: Fix regression on MMCONF_SUPPORT
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17653 -gerrit commit da0b00ecebe959087aa65162093e619f26c03b7e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 11:46:10 2016 +0200 intel/fsp_rangeley: Fix regression on MMCONF_SUPPORT Following commit did not move this selection to northbridge: bac0fad Remove explicit select MMCONF_SUPPORT Change-Id: I5f3c429dfd160eb439f396db2baf0ecf280022fd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/fsp_rangeley/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index bc735264..6a9dbe9 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX + select MMCONF_SUPPORT if NORTHBRIDGE_INTEL_FSP_RANGELEY

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Patch set updated for coreboot: PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17546 -gerrit commit 217ee458179cf7cd5128d861548addb93a261793 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 20:39:56 2016 +0200 PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access Some PCI-e capability registers are located starting from 0x100, these are not accessible using the conventional PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO was selected. Thus any feature that calls pcie_ext_find_capability() depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO being enabled on the platform. In theory there can be system without MMCONF_SUPPORT, but with complete PCI Express configuration space available using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF operations here, but rely on the default PCI access method to be able to access all of the configuration space. While at it, convert to IS_ENABLED() everywhere in the source and organize Kconfig file better. With this change, AGESA and binaryPI platforms change to PCI_CFG_EXT_IO method here until MMCONF_SUPPORT_DEFAULT is activated for them. Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 33 +++++++++++++++++---------------- src/device/pciexp_device.c | 42 ++++++++++++++---------------------------- 2 files changed, 31 insertions(+), 44 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index dd31cba..fb0aaba 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -227,11 +227,6 @@ config PCIX_PLUGIN_SUPPORT depends on PCI default y -config PCIEXP_PLUGIN_SUPPORT - bool - depends on PCI - default y - config CARDBUS_PLUGIN_SUPPORT bool depends on PCI @@ -242,10 +237,16 @@ config AZALIA_PLUGIN_SUPPORT depends on PCI default n +config PCIEXP_PLUGIN_SUPPORT + bool + depends on PCI + default y + +if PCIEXP_PLUGIN_SUPPORT + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Common Clock on PCIe links. @@ -253,7 +254,6 @@ config PCIEXP_COMMON_CLOCK config PCIEXP_ASPM prompt "Enable PCIe ASPM" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable ASPM on PCIe links. @@ -261,11 +261,20 @@ config PCIEXP_ASPM config PCIEXP_CLK_PM prompt "Enable PCIe Clock Power Management" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Clock Power Management on PCIe. +config PCIEXP_L1_SUB_STATE + prompt "Enable PCIe ASPM L1 SubState" + bool + depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT) + default n + help + Detect and enable ASPM on PCIe links. + +endif # PCIEXP_PLUGIN_SUPPORT + config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI @@ -278,14 +287,6 @@ config EARLY_PCI_BRIDGE This option enables static configuration for a single pre-defined PCI bridge function on bus 0. -config PCIEXP_L1_SUB_STATE - prompt "Enable PCIe ASPM L1 SubState" - bool - depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT - default n - help - Detect and enable ASPM on PCIe links. - if EARLY_PCI_BRIDGE config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index dcba777..a7e8980 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pciexp.h> -#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) { unsigned int this_cap_offset, next_cap_offset; @@ -29,10 +28,10 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) this_cap_offset = PCIE_EXT_CAP_OFFSET; do { - this_cap = pci_mmio_read_config32(dev, this_cap_offset); + this_cap = pci_read_config32(dev, this_cap_offset); next_cap_offset = this_cap >> 20; this_cap &= 0xffff; - cafe = pci_mmio_read_config32(dev, this_cap_offset + 4); + cafe = pci_read_config32(dev, this_cap_offset + 4); cafe &= 0xffff; if (this_cap == cap) return this_cap_offset; @@ -44,9 +43,7 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) return 0; } -#endif -#if CONFIG_PCIEXP_COMMON_CLOCK /* * Re-train a PCIe link */ @@ -109,9 +106,7 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, pciexp_retrain_link(root, root_cap); } } -#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ -#if CONFIG_PCIEXP_CLK_PM static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) { /* check if per port clk req is supported in device */ @@ -126,17 +121,15 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) lnkctl = lnkctl | PCI_EXP_EN_CLK_PM; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -#endif /* CONFIG_PCIEXP_CLK_PM */ -#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT) static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) { u32 reg32; - reg32 = pci_mmio_read_config32(dev, reg); + reg32 = pci_read_config32(dev, reg); reg32 &= mask; reg32 |= or; - pci_mmio_write_config32(dev, reg, reg32); + pci_write_config32(dev, reg, reg32); } static void pciexp_config_max_latency(device_t root, device_t dev) @@ -170,7 +163,7 @@ static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, unsigned int power_on_scale = (*data >> 16) & 0x3; unsigned int power_on_value = (*data >> 19) & 0x1f; - unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4); + unsigned int endp_data = pci_read_config32(dev, endp_cap + 4); unsigned int endp_L1SubStateSupport = endp_data & 0xf; unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff; unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3; @@ -200,7 +193,7 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, { device_t dev_t; unsigned char L1_ss_ok; - unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4); + unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4); unsigned int L1SubStateSupport; unsigned int comm_mode_rst_time; unsigned int power_on_scale; @@ -282,9 +275,7 @@ static void pciexp_config_L1_sub_state(device_t root, device_t dev) pciexp_L1_substate_commit(root, dev, root_cap, end_cap); } -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ -#if CONFIG_PCIEXP_ASPM /* * Determine the ASPM L0s or L1 exit latency for a link * by checking both root port and endpoint and returning @@ -371,7 +362,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap, printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } -#endif /* CONFIG_PCIEXP_ASPM */ static void pciexp_tune_dev(device_t dev) { @@ -386,25 +376,21 @@ static void pciexp_tune_dev(device_t dev) if (!root_cap) return; -#if CONFIG_PCIEXP_COMMON_CLOCK /* Check for and enable Common Clock */ - pciexp_enable_common_clock(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); -#if CONFIG_PCIEXP_CLK_PM /* Check if per port CLK req is supported by endpoint*/ - pciexp_enable_clock_power_pm(dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM)) + pciexp_enable_clock_power_pm(dev, cap); -#if CONFIG_PCIEXP_L1_SUB_STATE /* Enable L1 Sub-State when both root port and endpoint support */ - pciexp_config_L1_sub_state(root, dev); -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ + if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + pciexp_config_L1_sub_state(root, dev); -#if CONFIG_PCIEXP_ASPM /* Check for and enable ASPM */ - pciexp_enable_aspm(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) + pciexp_enable_aspm(root, root_cap, dev, cap); } void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,

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Patch set updated for coreboot: AMD binaryPI: Disable PCI_CFG_EXT_IO
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17536 -gerrit commit fa4f96c50c30976c67a08a8d18bd21dfe7430023 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 17:31:58 2016 +0200 AMD binaryPI: Disable PCI_CFG_EXT_IO We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be needed by payload or OS. Change-Id: Ib08028bda1b5226bb3b6b67e91f514480a9fc5ee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/Kconfig | 1 - src/cpu/amd/pi/00630F01/fixme.c | 7 ------- src/cpu/amd/pi/00660F01/Kconfig | 1 - src/cpu/amd/pi/00660F01/fixme.c | 7 ------- src/cpu/amd/pi/00670F00/Kconfig | 1 - src/cpu/amd/pi/00670F00/fixme.c | 7 ------- src/cpu/amd/pi/00730F01/Kconfig | 1 - src/cpu/amd/pi/00730F01/fixme.c | 7 ------- 8 files changed, 32 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 5b61a82..5c12ab6 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00630F01 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index d85f394..fcdc925 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -72,13 +72,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index a556ecc..b38ea6c 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00660F01 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 9a38bd8..6770287 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -74,13 +74,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ PciData = 0xFF03FFD5; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index 132d7e8..e47dfa3 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00670F00 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index f892af8..86f5acf 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -77,13 +77,6 @@ void amd_initmmio(void) (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended config cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ PciData = 0xFF03FFD5; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index baf7549..83af181 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00730F01 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index e16a4c4..fcdf498 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -74,13 +74,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ PciData = 0xFF03FFD5; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);

1 0

Patch set updated for coreboot: AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17534 -gerrit commit 8f49c9887016a1640ab9ab81ae34e04074a3c74b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 11:03:13 2016 +0200 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/Kconfig | 1 + src/cpu/amd/pi/00660F01/Kconfig | 1 + src/cpu/amd/pi/00670F00/Kconfig | 1 + src/cpu/amd/pi/00730F01/Kconfig | 1 + src/mainboard/amd/bettong/romstage.c | 1 + src/mainboard/amd/db-ft3b-lc/romstage.c | 5 +++-- src/mainboard/amd/lamar/romstage.c | 4 +++- src/mainboard/amd/olivehillplus/romstage.c | 5 +++-- src/mainboard/bap/ode_e21XX/romstage.c | 5 +++-- src/northbridge/amd/pi/00630F01/Kconfig | 1 - src/northbridge/amd/pi/00660F01/Kconfig | 1 - src/northbridge/amd/pi/00670F00/Kconfig | 1 - src/northbridge/amd/pi/00730F01/Kconfig | 1 - 13 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 962b829..5b61a82 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00630F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index de74d3c..a556ecc 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00660F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index d5e3abb..132d7e8 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00670F00 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00670F00 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index cfc5b75..baf7549 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_PI_00730F01 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00730F01 diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c3e2aa4..6b12afc 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void *resume_backup_memory; #endif + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 5c7796f..79cc0f9 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index f084582..58c6e42 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -52,7 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); hudson_lpc_decode(); outb(0x24, 0xCD6); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6d1e4ea..534a8e5 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,6 +37,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -48,8 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e45464e..5deeaa8 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,6 +41,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been @@ -52,8 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 293b12d..3669826 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00630F01 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index f5d234d..fdae80f 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00660F01 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index e349635..a92658a 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_PI_00670F00 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index b8dcd99..47c2323 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ ## config NORTHBRIDGE_AMD_PI_00730F01 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_PI_00730F01

1 0

Patch set updated for coreboot: AMD binaryPI: Use explicit PCI IO config access in bootblock
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17532 -gerrit commit 94b96d534f703937537e7fbcacafc897edc55f89 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:24:12 2016 +0200 AMD binaryPI: Use explicit PCI IO config access in bootblock This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I380cf483bfe4e2d64969110ae6d5d04c3ced2418 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/pi/hudson/bootblock.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index ff52199..32b1298 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -34,15 +34,15 @@ static void hudson_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -52,9 +52,9 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void)

1 0

Patch set updated for coreboot: AGESA: Switch to MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17533 -gerrit commit ac44fc860cc3cba9f2ae04fa6a0351765272ace6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 11:03:13 2016 +0200 AGESA: Switch to MMCONF_SUPPORT_DEFAULT Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 1 + src/cpu/amd/agesa/family12/Kconfig | 1 + src/cpu/amd/agesa/family14/Kconfig | 1 + src/cpu/amd/agesa/family15/Kconfig | 1 + src/cpu/amd/agesa/family15rl/Kconfig | 1 + src/cpu/amd/agesa/family15tn/Kconfig | 1 + src/cpu/amd/agesa/family16kb/Kconfig | 1 + src/mainboard/amd/dinar/romstage.c | 1 + src/mainboard/amd/inagua/romstage.c | 1 + src/mainboard/amd/olivehill/romstage.c | 5 +++-- src/mainboard/amd/parmer/romstage.c | 1 + src/mainboard/amd/persimmon/romstage.c | 1 + src/mainboard/amd/south_station/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 1 + src/mainboard/amd/torpedo/romstage.c | 4 +++- src/mainboard/amd/union_station/romstage.c | 1 + src/mainboard/asrock/e350m1/romstage.c | 1 + src/mainboard/asrock/imb-a180/romstage.c | 1 + src/mainboard/asus/f2a85-m/romstage.c | 1 + src/mainboard/bap/ode_e20XX/romstage.c | 1 + src/mainboard/biostar/am1ml/romstage.c | 4 +++- src/mainboard/elmex/pcm205400/romstage.c | 1 + src/mainboard/gizmosphere/gizmo/romstage.c | 1 + src/mainboard/gizmosphere/gizmo2/romstage.c | 5 +++-- src/mainboard/hp/abm/romstage.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 2 ++ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 1 + src/mainboard/lenovo/g505s/romstage.c | 2 ++ src/mainboard/lippert/frontrunner-af/romstage.c | 1 + src/mainboard/lippert/toucan-af/romstage.c | 1 + src/mainboard/msi/ms7721/romstage.c | 1 + src/mainboard/pcengines/apu1/romstage.c | 1 + src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8qgi/romstage.c | 3 ++- src/mainboard/supermicro/h8scm/romstage.c | 3 ++- src/mainboard/tyan/s8226/Kconfig | 1 - src/mainboard/tyan/s8226/romstage.c | 3 ++- src/northbridge/amd/agesa/family10/Kconfig | 1 - src/northbridge/amd/agesa/family10/northbridge.c | 2 -- src/northbridge/amd/agesa/family12/Kconfig | 1 - src/northbridge/amd/agesa/family12/northbridge.c | 2 -- src/northbridge/amd/agesa/family14/Kconfig | 1 - src/northbridge/amd/agesa/family14/northbridge.c | 2 -- src/northbridge/amd/agesa/family15/Kconfig | 1 - src/northbridge/amd/agesa/family15/northbridge.c | 2 -- src/northbridge/amd/agesa/family15rl/Kconfig | 1 - src/northbridge/amd/agesa/family15rl/northbridge.c | 2 -- src/northbridge/amd/agesa/family15tn/Kconfig | 1 - src/northbridge/amd/agesa/family15tn/northbridge.c | 2 -- src/northbridge/amd/agesa/family16kb/Kconfig | 1 - src/northbridge/amd/agesa/family16kb/northbridge.c | 2 -- 51 files changed, 48 insertions(+), 32 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 7bcc7fd..3127855 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -17,6 +17,7 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 4529598..b15a14b 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_AGESA_FAMILY12 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY12 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 46370bc..5ac601c 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_AGESA_FAMILY14 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index bfdbf5e..eb32b70 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_AGESA_FAMILY15 bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig index 57a2ed9..5948787 100644 --- a/src/cpu/amd/agesa/family15rl/Kconfig +++ b/src/cpu/amd/agesa/family15rl/Kconfig @@ -17,6 +17,7 @@ config CPU_AMD_AGESA_FAMILY15_RL bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_RL diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 6728153..3f8a3f0 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_AGESA_FAMILY15_TN bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 7030608..1af9561 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -16,6 +16,7 @@ config CPU_AMD_AGESA_FAMILY16_KB bool select PCI_IO_CFG_EXT + select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index bc5d312..0edc346 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3e37e03..3d0eecf 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,6 +40,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index b1addb3..bb1ad30 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index ae1c246..1f251ab 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -38,6 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 980ff3e..c8a8d74 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 4b725c0..95f6dde 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 4c9c8fa..147f31a 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 74402bf..d28608e 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -39,9 +39,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x35); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x35); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); gpioEarlyInit(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index cdc5640..7a5d348 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -39,6 +39,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7a849e4..82fbecf 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 7070e69..29d831d 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 83f6778..b5aff9f 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,6 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index c109265..a43d035 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index d7da2bb..e0afa75 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -113,6 +113,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pci_devfn_t dev; u32 *addr32; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -121,7 +124,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5); diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 980ff3e..c8a8d74 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 1335a8f..6d06621 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -41,6 +41,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index b1addb3..bb1ad30 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -38,6 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -46,8 +49,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - amd_initmmio(); - /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 6e77c57..02ebbc9 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -44,6 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 *addr32; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index e5f15b5..714743b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -34,6 +34,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 5f22aaa..85a4343 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -62,6 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index e5f15b5..714743b 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -34,6 +34,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index ccb6b39..37dc37f 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -45,6 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b2590fc..adc2987 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -46,6 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index f8565ad..4aeb1ec 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -128,6 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index f8e6318..a74d247 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -51,6 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index b259e3b..5492d47 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index bab438e..19ffbdf 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -40,8 +40,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index fecb91a..918d9ad 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -39,8 +39,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 733f1c4..4610758 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7460f20..d43c04b 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -38,8 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* For serial port. */ diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 227d1c1..51e4a9d 100644 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY10 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 449c5b4..2a54892 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1096,13 +1096,11 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_read_resources(device_t dev) { -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void cpu_bus_set_resources(device_t dev) diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index 9d49954..f967837 100644 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 9b2634c..6f2896a 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -649,13 +649,11 @@ static void cpu_bus_read_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 999b242..2e295ef 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 21978f6..f92183e 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -302,13 +302,11 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig index 7145e39..c895b5d 100644 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index daf1de7..5fc9833 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -326,13 +326,11 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15rl/Kconfig b/src/northbridge/amd/agesa/family15rl/Kconfig index 1bf81ba..2089a22 100644 --- a/src/northbridge/amd/agesa/family15rl/Kconfig +++ b/src/northbridge/amd/agesa/family15rl/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_RL bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY15_RL diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index a8c2807..b5f7690 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -326,13 +326,11 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index e6780b5..26a9984 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index ae1efb4..2353126 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -325,13 +325,11 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index b9fcc8f..bafbe2d 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -15,7 +15,6 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index c53d7d3..63e1c2e 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -325,13 +325,11 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the APIC_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid)

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Patch set updated for coreboot: AGESA: Disable PCI_CFG_EXT_IO
by Kyösti Mälkki Nov. 30, 2016

Nov. 30, 2016

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17535 -gerrit commit 3d06269b929dfbd46c23bf10f0aa50cd5d0c5386 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 17:31:58 2016 +0200 AGESA: Disable PCI_CFG_EXT_IO We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 1 - src/cpu/amd/agesa/family12/Kconfig | 1 - src/cpu/amd/agesa/family12/fixme.c | 7 ------- src/cpu/amd/agesa/family14/Kconfig | 1 - src/cpu/amd/agesa/family14/fixme.c | 7 ------- src/cpu/amd/agesa/family15/Kconfig | 1 - src/cpu/amd/agesa/family15/fixme.c | 7 ------- src/cpu/amd/agesa/family15rl/Kconfig | 1 - src/cpu/amd/agesa/family15rl/fixme.c | 7 ------- src/cpu/amd/agesa/family15tn/Kconfig | 1 - src/cpu/amd/agesa/family15tn/fixme.c | 7 ------- src/cpu/amd/agesa/family16kb/Kconfig | 1 - src/cpu/amd/agesa/family16kb/fixme.c | 7 ------- 13 files changed, 49 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 3127855..6bb8d43 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index b15a14b..8e4c7ba 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY12 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index efd004a..deeb8b9 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -76,13 +76,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000ull; - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - /* Enable Non-Post Memory in CPU */ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; PciData = (PciData >> 8) & ~0xff; diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 5ac601c..7be63f5 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY14 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 25a32bd..9a171ed 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -78,13 +78,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000ull; - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - /* Set Ontario Link Data */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); PciData = 0x01308002; diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index eb32b70..22e4d8c 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15 bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c index 5633007..7b8598d 100644 --- a/src/cpu/amd/agesa/family15/fixme.c +++ b/src/cpu/amd/agesa/family15/fixme.c @@ -269,13 +269,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - /* - * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | (1ULL << 46); - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - #if IS_ENABLED(CONFIG_BOARD_AMD_DINAR) UINT32 PciData; PCI_ADDR PciAddress; diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig index 5948787..b916e2c 100644 --- a/src/cpu/amd/agesa/family15rl/Kconfig +++ b/src/cpu/amd/agesa/family15rl/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY15_RL bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family15rl/fixme.c b/src/cpu/amd/agesa/family15rl/fixme.c index b7d8903..b35d115 100644 --- a/src/cpu/amd/agesa/family15rl/fixme.c +++ b/src/cpu/amd/agesa/family15rl/fixme.c @@ -72,13 +72,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 3f8a3f0..1f41560 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index b7d8903..b35d115 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -72,13 +72,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 1af9561..3f65055 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool - select PCI_IO_CFG_EXT select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index da2bcd9..d1bc4bc 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -72,13 +72,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

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