June 2015 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: haswell: Use _timestamp region
by Marc Jones June 30, 2015

June 30, 2015

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10737 -gerrit commit 9f259bfb6cac21332d4bd6478faab17d0e85c546 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 29 10:48:57 2014 -0700 haswell: Use _timestamp region Use timestamp region instead of storing timestamps in local variables before cbmem is up. BUG=None BRANCH=None TEST=cbmem -t reports correct timestamps on falco and peppy (for both normal boot and suspend/resume). Original-Change-Id: If5883721553090f51c0bfcb5677aad55c54f82b3 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226362 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 61dbca0b181335d187d742c4a63472f2f2cc9a1b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibb98f32f24bac1d3560eb257bf0d9f4310a5828f --- src/cpu/intel/haswell/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 779f1d6..2ed1c61 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP + select HAS_PRECBMEM_TIMESTAMP_REGION config BOOTBLOCK_CPU_INIT string

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New patch to review for coreboot: t132: Add timestamp collection support in t132
by Marc Jones June 30, 2015

June 30, 2015

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10736 -gerrit commit 25425ec066c291ffe5e25b6a613584aac6871809 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Oct 13 14:50:08 2014 -0700 t132: Add timestamp collection support in t132 Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 --- src/soc/nvidia/tegra132/Kconfig | 87 ++++++++++++++++------ src/soc/nvidia/tegra132/bootblock.c | 4 + .../tegra132/include/soc/memlayout_vboot2.ld | 3 +- src/soc/nvidia/tegra132/romstage.c | 5 ++ src/soc/nvidia/tegra132/verstage.c | 2 + 5 files changed, 79 insertions(+), 22 deletions(-) diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index a5df92a..4c77068 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -1,37 +1,27 @@ config SOC_NVIDIA_TEGRA132 bool default n - select ARCH_BOOTBLOCK_ARMV4 - select ARCH_VERSTAGE_ARMV4 - select ARCH_ROMSTAGE_ARMV4 - select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_BOOTBLOCK_ARM_V4 + select ARCH_VERSTAGE_ARM_V4 + select ARCH_ROMSTAGE_ARM_V4 + select ARCH_RAMSTAGE_ARM_V8_64 select BOOTBLOCK_CONSOLE select GIC select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_HARD_RESET select HAVE_UART_SPECIAL + select HAVE_UART_MEMORY_MAPPED + select EARLY_CONSOLE select ARM_BOOTBLOCK_CUSTOM + select DYNAMIC_CBMEM select SMP - select ARM64_USE_SECURE_MONITOR - select GENERIC_GPIO_LIB + select ARCH_USE_SECURE_MONITOR + select COLLECT_TIMESTAMPS + select HAS_PRECBMEM_TIMESTAMP_REGION if SOC_NVIDIA_TEGRA132 -config MAINBOARD_DO_DSI_INIT - bool "Use dsi graphics interface" - depends on MAINBOARD_DO_NATIVE_VGA_INIT - default n - help - Initialize dsi display - -config MAINBOARD_DO_SOR_INIT - bool "Use dp graphics interface" - depends on MAINBOARD_DO_NATIVE_VGA_INIT - default n - help - Initialize dp display - config BOOTBLOCK_CPU_INIT string default "soc/nvidia/tegra132/bootblock.c" @@ -40,13 +30,68 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + config MAX_CPUS int default 2 +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x22000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x22080 + +choice CONSOLE_SERIAL_TEGRA132_UART_CHOICES + prompt "Serial Console UART" + default CONSOLE_SERIAL_TEGRA132_UARTA + depends on CONSOLE_SERIAL_UART + +config CONSOLE_SERIAL_TEGRA132_UARTA + bool "UARTA" + help + Serial console on UART A. + +config CONSOLE_SERIAL_TEGRA132_UARTB + bool "UARTB" + help + Serial console on UART B. + +config CONSOLE_SERIAL_TEGRA132_UARTC + bool "UARTC" + help + Serial console on UART C. + +config CONSOLE_SERIAL_TEGRA132_UARTD + bool "UARTD" + help + Serial console on UART D. + +config CONSOLE_SERIAL_TEGRA132_UARTE + bool "UARTE" + help + Serial console on UART E. + +endchoice + +config CONSOLE_SERIAL_TEGRA132_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x70006000 if CONSOLE_SERIAL_TEGRA132_UARTA + default 0x70006040 if CONSOLE_SERIAL_TEGRA132_UARTB + default 0x70006200 if CONSOLE_SERIAL_TEGRA132_UARTC + default 0x70006300 if CONSOLE_SERIAL_TEGRA132_UARTD + default 0x70006400 if CONSOLE_SERIAL_TEGRA132_UARTE + help + Map the UART names to the respective MMIO addres. + config MTS_DIRECTORY string "Directory where MTS microcode files are located" - default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod" + default "." help Path to directory where MTS microcode files are located. diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index b19cf49..bb8a393 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -26,6 +26,7 @@ #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> #include <soc/power.h> +#include <timestamp.h> #define BCT_OFFSET_IN_BIT 0x50 #define ODMDATA_OFFSET_IN_BCT 0x6A8 @@ -57,6 +58,9 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) void main(void) { + timestamp_early_init(0); + timestamp_add_now(TS_START_BOOTBLOCK); + // enable JTAG at the earliest stage enable_jtag(); diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index a834f99..5f59f8d 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -36,7 +36,8 @@ SECTIONS PRERAM_CBFS_CACHE(0x40002000, 72K) VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) - BOOTBLOCK(0x40019000, 24K) + TIMESTAMP(0x40018800, 2K) + BOOTBLOCK(0x40019000, 22K) VERSTAGE(0x4001f000, 60K) ROMSTAGE(0x4002e000, 72K) SRAM_END(0x40040000) diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 6476e06..ae295c0 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -31,6 +31,7 @@ #include <soc/sdram_configs.h> #include <soc/romstage.h> #include <timer.h> +#include <timestamp.h> void __attribute__((weak)) romstage_mainboard_init(void) { @@ -39,6 +40,8 @@ void __attribute__((weak)) romstage_mainboard_init(void) void romstage(void) { + timestamp_add_now(TS_START_ROMSTAGE); + console_init(); exception_init(); @@ -52,6 +55,8 @@ void romstage(void) printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); #endif + timestamp_add_now(TS_AFTER_INITRAM); + /* * Trust Zone needs to be initialized after the DRAM initialization * because carveout registers are programmed during DRAM init. diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c index b70028a..d6eba9a 100644 --- a/src/soc/nvidia/tegra132/verstage.c +++ b/src/soc/nvidia/tegra132/verstage.c @@ -24,6 +24,7 @@ #include <console/console.h> #include <soc/verstage.h> #include <program_loading.h> +#include <timestamp.h> void __attribute__((weak)) verstage_mainboard_init(void) { @@ -33,6 +34,7 @@ void __attribute__((weak)) verstage_mainboard_init(void) static void verstage(void) { console_init(); + timestamp_add_now(TS_START_VBOOT); exception_init(); verstage_mainboard_init();

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New patch to review for coreboot: timestamp: Make timestamp library more flexible and intelligent
by Marc Jones June 30, 2015

June 30, 2015

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10735 -gerrit commit 171d1f9658bbedf0a0ef1d923960340eeaeba781 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Oct 15 15:17:49 2014 -0700 timestamp: Make timestamp library more flexible and intelligent Add support for: 1) Using timestamps in bootblock and verstage 2) Allowing the timestamps to be stashed into _timestamp region so that they can be used across multiple stages 3) Performing operations over the timestamps in _timestamp region Instead of having two separate APIs for stashing and adding timestamps, let the timestamp library decide on its own where to save depending on timestamp cache status. Now the sequence of operations would be something like: timestamp_init / timestamp_early_init : Set the base time timestamp_add / timestamp_add_now cbmem_initialize : It internally calls timestamp_sync timestamp_add / timestamp_add_now BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully for ryu and samus. cbmem -t on ryu works fine. Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/224024 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 2f6b472984f4971ece172b789aab3bc82afa8a9d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4d2ffc99277be6c248c8c70149dc14334a1f536a --- src/arch/x86/Makefile.inc | 3 +- src/arch/x86/init/romstage.ld | 5 + src/include/timestamp.h | 25 ++++ src/lib/timestamp.c | 260 +++++++++++++++++++++++++++++++----------- 4 files changed, 223 insertions(+), 70 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f502bbe..dcb9ff0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -225,7 +225,8 @@ $(objgenerated)/romstage_null.ld: $(obj)/config.h $$(filter %.ld,$$(romstage-src rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,$(^),#include "$(ldscript)"\n)' >> $@.tmp - $(CC_romstage) $(PREPROCESS_ONLY) $@.tmp > $@ + $(CC_romstage) $(PREPROCESS_ONLY) $(CPPFLAGS_common) $@.tmp > $@ + $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 7b9cb6a..db1c8ee 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -53,6 +53,11 @@ SECTIONS .car.data . (NOLOAD) : { _car_data_start = .; *(.car.global_data); +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + _timestamp = .; + . = . + 0x100; + _etimestamp = .; +#endif _car_data_end = .; /* The preram cbmem console area comes last to take advantage * of a zero-sized array to hold the memconsole contents. diff --git a/src/include/timestamp.h b/src/include/timestamp.h index a248ea4..a2301fb 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -89,10 +89,35 @@ enum timestamp_id { }; #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) +/* + * Order of usage of timestamp library is: + * Call timestamp_early_init / timestamp_init to set base time before any + * timestamp_add function is called. timestamp_early_init also ensures that the + * cache is valid in _timestamp region. + * After this, timestamp_add / timestamp_add_now can be used to record + * timestamps. Sync will be automatically taken care of by cbmem_initialize + */ +/* + * Initialize the cache to a valid state and set the base time. + * This function is used before DRAM is setup so that the timestamp cache can + * be initialized in _timestamp region. + * Both, timestamp_init and timestamp_early_init reset the cbmem state to + * timestamp table reset required. Thus, whenever a timestamp_add or + * timestamp_sync is done to add new entries into the cbmem timestamp table, it + * first resets the table to 0 entries. + */ +void timestamp_early_init(uint64_t base); +/* Initialize the base time for timestamps and mark cache as valid */ void timestamp_init(uint64_t base); +/* + * Add a new timestamp. Depending on cbmem is available or not, this timestamp + * will be stored to cbmem / timestamp cache. + */ void timestamp_add(enum timestamp_id id, uint64_t ts_time); +/* Calls timestamp_add with current timestamp. */ void timestamp_add_now(enum timestamp_id id); #else +#define timestamp_early_init(base) #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 0c41ea2..34ad5a1 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -17,10 +17,12 @@ * Foundation, Inc. */ +#include <assert.h> #include <stddef.h> #include <stdint.h> #include <console/console.h> #include <cbmem.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> @@ -29,12 +31,70 @@ #define MAX_TIMESTAMPS 60 -static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; -static uint64_t ts_basetime CAR_GLOBAL = 0; +#define MAX_TIMESTAMP_CACHE 16 -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time); +struct __attribute__((__packed__)) timestamp_cache { + uint16_t cache_state; + uint16_t cbmem_state; + struct timestamp_table table; + struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; +}; -static void timestamp_real_init(uint64_t base) +#define USE_TIMESTAMP_REGION \ + (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) && \ + defined(__PRE_RAM__)) + +#define USE_LOCAL_TIMESTAMP_CACHE (!defined(__PRE_RAM__)) + +#define HAS_CBMEM \ + (defined(__ROMSTAGE__) || defined(__RAMSTAGE__)) + +#if USE_LOCAL_TIMESTAMP_CACHE +static struct timestamp_cache timestamp_cache; +#endif + +enum { + TIMESTAMP_CACHE_UNINITIALIZED = 0, + TIMESTAMP_CACHE_INITIALIZED, + TIMESTAMP_CACHE_NOT_NEEDED, +}; + +enum { + TIMESTAMP_CBMEM_RESET_NOT_REQD = 0, + TIMESTAMP_CBMEM_RESET_REQD, +}; + +static void timestamp_cache_init(struct timestamp_cache *ts_cache, + uint64_t base, uint16_t cbmem_state) +{ + ts_cache->table.num_entries = 0; + ts_cache->table.max_entries = MAX_TIMESTAMP_CACHE; + ts_cache->table.base_time = base; + ts_cache->cache_state = TIMESTAMP_CACHE_INITIALIZED; + ts_cache->cbmem_state = cbmem_state; +} + +static struct timestamp_cache *timestamp_cache_get(void) +{ + struct timestamp_cache *ts_cache = NULL; + +#if USE_LOCAL_TIMESTAMP_CACHE + ts_cache = &timestamp_cache; +#elif IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + if (_timestamp_size < sizeof(*ts_cache)) + BUG(); + ts_cache = car_get_var_ptr((void *)_timestamp); +#endif + + if (ts_cache && ts_cache->cache_state == TIMESTAMP_CACHE_UNINITIALIZED) + timestamp_cache_init(ts_cache, 0, + TIMESTAMP_CBMEM_RESET_NOT_REQD); + + return ts_cache; +} + +#if HAS_CBMEM +static struct timestamp_table *timestamp_alloc_cbmem_table(void) { struct timestamp_table* tst; @@ -43,14 +103,15 @@ static void timestamp_real_init(uint64_t base) MAX_TIMESTAMPS * sizeof(struct timestamp_entry)); if (!tst) - return; + return NULL; - tst->base_time = base; + tst->base_time = 0; tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; - car_set_var(ts_table_p, tst); + return tst; } +#endif /* Determine if one should proceed into timestamp code. This is for protecting * systems that have multiple processors running in romstage -- namely AMD @@ -64,97 +125,165 @@ static int timestamp_should_run(void) return 1; } -void timestamp_add(enum timestamp_id id, uint64_t ts_time) +static struct timestamp_table *timestamp_table_get(void) { - struct timestamp_entry *tse; - struct timestamp_table *ts_table = NULL; + MAYBE_STATIC struct timestamp_table *ts_table = NULL; + struct timestamp_cache *ts_cache; if (!timestamp_should_run()) return; - ts_table = car_get_var(ts_table_p); - if (!ts_table) { - timestamp_stash(id, ts_time); - return; + ts_cache = timestamp_cache_get(); + + if (ts_cache == NULL) { +#if HAS_CBMEM + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + return ts_table; +} + + if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) + return &ts_cache->table; + +#if HAS_CBMEM + if (ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) { + ts_table = timestamp_alloc_cbmem_table(); + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; } - if (ts_table->num_entries == ts_table->max_entries) + + if (!ts_table) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); +#endif + + return ts_table; +} + +static void timestamp_add_table_entry(struct timestamp_table *ts_table, + enum timestamp_id id, uint64_t ts_time) +{ + struct timestamp_entry *tse; + + if (ts_table->num_entries == ts_table->max_entries) { + printk(BIOS_ERR, "ERROR: Dropped a timestamp entry\n"); return; + } tse = &ts_table->entries[ts_table->num_entries++]; tse->entry_id = id; tse->entry_stamp = ts_time - ts_table->base_time; } -void timestamp_add_now(enum timestamp_id id) +static void timestamp_sync(void) { - timestamp_add(id, timestamp_get()); + uint32_t i; + + struct timestamp_cache *ts_cache; + struct timestamp_table *ts_cache_table; + struct timestamp_table *ts_cbmem_table = NULL; + + ts_cache = timestamp_cache_get(); + + /* No timestamp cache found */ + if (ts_cache == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); + return; } -#define MAX_TIMESTAMP_CACHE 8 -struct timestamp_cache { - enum timestamp_id id; - uint64_t time; -} timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL; + ts_cache_table = &ts_cache->table; -static int timestamp_entries CAR_GLOBAL = 0; +#if HAS_CBMEM + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); -/** - * timestamp_stash() allows to temporarily cache timestamps. - * This is needed when timestamping before the CBMEM area - * is initialized. The function timestamp_do_sync() is used to - * write the timestamps to the CBMEM area and this is done as - * part of CAR migration for romstage, and in ramstage main(). - */ + if ((ts_cache->cbmem_state == TIMESTAMP_CBMEM_RESET_REQD) || + (ts_cbmem_table == NULL)) + ts_cbmem_table = timestamp_alloc_cbmem_table(); +#endif -static void timestamp_stash(enum timestamp_id id, uint64_t ts_time) -{ - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + if (ts_cbmem_table == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + return; + } - if (ts_entries >= MAX_TIMESTAMP_CACHE) { - printk(BIOS_ERR, "ERROR: failed to add timestamp to cache\n"); + if (ts_cbmem_table == ts_cache_table) { + printk(BIOS_ERR, "ERROR: Table error to sync timestamps\n"); return; } - ts_cache[ts_entries].id = id; - ts_cache[ts_entries].time = ts_time; - car_set_var(timestamp_entries, ++ts_entries); + + ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_NOT_REQD; + + /* + * There can be two cases for timestamp sync: + * 1. Newly added cbmem_table will have base_time of 0. Thus, no + * adjusments are needed for the timestamps being added from cache to + * cbmem table. + * 2. Timestamps added to cache before ramstage: In this case, the + * base_time in cache table would be 0 and add_table_entry will take + * care of subtracting the appropriate base_time. + */ + for (i = 0; i < ts_cache_table->num_entries; i++) { + struct timestamp_entry *tse = &ts_cache_table->entries[i]; + timestamp_add_table_entry(ts_cbmem_table, tse->entry_id, + tse->entry_stamp); } -static void timestamp_do_sync(void) -{ - struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); - int ts_entries = car_get_var(timestamp_entries); + ts_cache_table->num_entries = 0; + /* Freshly added cbmem table has base_time 0. Inherit cache base_time */ + if (ts_cbmem_table->base_time == 0) + ts_cbmem_table->base_time = ts_cache_table->base_time; +} - int i; - for (i = 0; i < ts_entries; i++) - timestamp_add(ts_cache[i].id, ts_cache[i].time); - car_set_var(timestamp_entries, 0); +void timestamp_early_init(uint64_t base) +{ + struct timestamp_cache *ts_cache; + ts_cache = timestamp_cache_get(); + if (ts_cache == NULL) + BUG(); + timestamp_cache_init(ts_cache, base, TIMESTAMP_CBMEM_RESET_REQD); } void timestamp_init(uint64_t base) { + struct timestamp_cache *ts_cache; + struct timestamp_table *tst; + if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - /* Copy of basetime, it is too early for CBMEM. */ - car_set_var(ts_basetime, base); -#else - struct timestamp_table *tst = NULL; + ts_cache = timestamp_cache_get(); + + ts_cache->cbmem_state = TIMESTAMP_CBMEM_RESET_REQD; - /* Locate and use an already existing table. */ - if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) - tst = cbmem_find(CBMEM_ID_TIMESTAMP); + tst = timestamp_table_get(); - if (tst) { - car_set_var(ts_table_p, tst); + if (!tst) { + printk(BIOS_ERR, "ERROR: No timestamp table to init\n"); return; } - /* Copy of basetime, may be too early for CBMEM. */ - car_set_var(ts_basetime, base); - timestamp_real_init(base); -#endif + tst->base_time = base; +} + +void timestamp_add(enum timestamp_id id, uint64_t ts_time) +{ + struct timestamp_table *ts_table; + + ts_table = timestamp_table_get(); + + if (!ts_table) { + printk(BIOS_ERR, "ERROR: No timestamp table found\n"); + return; + } + + timestamp_add_table_entry(ts_table, id, ts_time); +} + + timestamp_add_table_entry(ts_table, id, ts_time); +} + +void timestamp_add_now(enum timestamp_id id) +{ + timestamp_add(id, timestamp_get()); } static void timestamp_reinit(int is_recovery) @@ -162,14 +291,7 @@ static void timestamp_reinit(int is_recovery) if (!timestamp_should_run()) return; -#ifdef __PRE_RAM__ - timestamp_real_init(car_get_var(ts_basetime)); -#else - if (!car_get_var(ts_table_p)) - timestamp_init(car_get_var(ts_basetime)); -#endif - if (car_get_var(ts_table_p)) - timestamp_do_sync(); + timestamp_sync(); } /* Call timestamp_reinit CBMEM init hooks. */

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New patch to review for coreboot: memlayout: Add TIMESTAMP region
by Marc Jones June 30, 2015

June 30, 2015

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10734 -gerrit commit d1971748f29739cc3cfd840306754c596b2b4cc6 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Oct 14 15:26:47 2014 -0700 memlayout: Add TIMESTAMP region This region is used to store the timestamps from bootblock and verstage when cbmem is not yet initialized. Once cbmem is setup, the timestamps from this region can be retrieved and filled up properly in cbmem. In order to achieve this a new Kconfig option is introduced HAS_TIMESTAMP_REGION. This is to maintain compatbility with older boards which do not use this region. BUG=chrome-os-partner:32973 BRANCH=None TEST=cbmem -t and verified timestamps on ryu Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/223348 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 3f77e81a369d032cbb0bc072872b373533b000e9) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/Kconfig | 8 ++++++++ src/include/memlayout.h | 3 +++ src/include/symbols.h | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 94b3508..814fd23 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -200,6 +200,14 @@ config COLLECT_TIMESTAMPS Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. +config HAS_PRECBMEM_TIMESTAMP_REGION + bool "Timestamp region exists for pre-cbmem timestamps" + depends on COLLECT_TIMESTAMPS + help + A separate region is maintained to allow storing of timestamps before + cbmem comes up. This is useful for storing timestamps across different + stage boundaries. + config USE_BLOBS bool "Allow use of binary-only repository" default n diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 2771f2f..a529628 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -47,6 +47,9 @@ #define DRAM_START(addr) SYMBOL(dram, addr) +#define TIMESTAMP(addr, size) \ + REGION(timestamp, addr, size, 8) + #define PRERAM_CBMEM_CONSOLE(addr, size) \ REGION(preram_cbmem_console, addr, size, 4) diff --git a/src/include/symbols.h b/src/include/symbols.h index 9102e82..3fbf819 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -28,6 +28,10 @@ extern u8 _esram[]; extern u8 _dram[]; +extern u8 _timestamp[]; +extern u8 _etimestamp[]; +#define _timestamp_size (_etimestamp - _timestamp) + extern u8 _preram_cbmem_console[]; extern u8 _epreram_cbmem_console[]; #define _preram_cbmem_console_size \

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Patch merged into coreboot/master: nvidia/tegra210: reserve more room for the romstage in vboot builds
by gerrit＠coreboot.org June 30, 2015

June 30, 2015

the following patch was just integrated into master: commit d13fd1b013f1639521aa1a682d147db758db398f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 21:59:23 2015 +0200 nvidia/tegra210: reserve more room for the romstage in vboot builds Change-Id: I11c2e270179c54af8687435ff662a509ac714505 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10733 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10733 for details. -gerrit

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Patch merged into coreboot/master: google/foster: roll up fixes to compile with vboot
by gerrit＠coreboot.org June 30, 2015

June 30, 2015

the following patch was just integrated into master: commit e3fe4e7572a60cf7444ee87228edb509d020e0b7 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 21:58:45 2015 +0200 google/foster: roll up fixes to compile with vboot Change-Id: I796e0fa64f9a858a54b09a82fbec1f0576e7e124 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10732 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10732 for details. -gerrit

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Patch merged into coreboot/master: google/smaug: roll up fixes to compile with vboot
by gerrit＠coreboot.org June 30, 2015

June 30, 2015

the following patch was just integrated into master: commit 84a124de6b776ea8eb81f1a09801fe802d06fc33 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 21:58:45 2015 +0200 google/smaug: roll up fixes to compile with vboot Change-Id: I256410ff6c0107bbbaaf49b909d63ca61e88a22c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10731 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10731 for details. -gerrit

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Patch set updated for coreboot: coreinfo: Use IS_ENABLED() to query Kconfig variables
by Stefan Reinauer June 30, 2015

June 30, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10713 -gerrit commit 349e03e2e7a00e130abc2353e432672c58c7a398 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Jun 29 16:08:39 2015 -0700 coreinfo: Use IS_ENABLED() to query Kconfig variables This will make the code work with the different styles of Kconfig (emit unset bools vs don't emit unset bools) Roughly, the patch does this, and a little bit of fixing up: perl -pi -e 's,ifdef (CONFIG_.+?)\b,if IS_ENABLED$$1$,g' `find . -name *.[ch]` perl -pi -e 's,ifndef (CONFIG_.+?)\b,if !IS_ENABLED$$1$,g' `find . -name *.[ch]` Change-Id: Ia461a33541f58ff39e984119c44ece7e6c05608a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/bootlog_module.c | 2 +- payloads/coreinfo/cbfs_module.c | 2 +- payloads/coreinfo/coreboot_module.c | 2 +- payloads/coreinfo/coreinfo.c | 26 +++++++++++++------------- payloads/coreinfo/cpuinfo_module.c | 2 +- payloads/coreinfo/lar_module.c | 2 +- payloads/coreinfo/multiboot_module.c | 2 +- payloads/coreinfo/nvram_module.c | 2 +- payloads/coreinfo/pci_module.c | 2 +- payloads/coreinfo/ramdump_module.c | 2 +- 10 files changed, 22 insertions(+), 22 deletions(-) diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c index ca5b040..791446b 100644 --- a/payloads/coreinfo/bootlog_module.c +++ b/payloads/coreinfo/bootlog_module.c @@ -19,7 +19,7 @@ #include "coreinfo.h" -#ifdef CONFIG_MODULE_BOOTLOG +#if IS_ENABLED(CONFIG_MODULE_BOOTLOG) #define CONFIG_COREBOOT_PRINTK_BUFFER_ADDR 0x90000 #define CONFIG_COREBOOT_PRINTK_BUFFER_SIZE 65536 diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 98b6160..2e6db28 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -20,7 +20,7 @@ #include "coreinfo.h" #include "endian.h" -#ifdef CONFIG_MODULE_CBFS +#if IS_ENABLED(CONFIG_MODULE_CBFS) #define ALIGN(_v, _a) (((_v) + ((_a) - 1)) & ~((_a) - 1)) diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index f232d6b..00b6faf 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -20,7 +20,7 @@ #include "coreinfo.h" #include <coreboot_tables.h> -#ifdef CONFIG_MODULE_COREBOOT +#if IS_ENABLED(CONFIG_MODULE_COREBOOT) #define MAX_MEMORY_COUNT 5 diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 5766be4..5bd1068 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -35,34 +35,34 @@ extern struct coreinfo_module lar_module; extern struct coreinfo_module cbfs_module; struct coreinfo_module *system_modules[] = { -#ifdef CONFIG_MODULE_CPUINFO +#if IS_ENABLED(CONFIG_MODULE_CPUINFO) &cpuinfo_module, #endif -#ifdef CONFIG_MODULE_PCI +#if IS_ENABLED(CONFIG_MODULE_PCI) &pci_module, #endif -#ifdef CONFIG_MODULE_NVRAM +#if IS_ENABLED(CONFIG_MODULE_NVRAM) &nvram_module, #endif -#ifdef CONFIG_MODULE_RAMDUMP +#if IS_ENABLED(CONFIG_MODULE_RAMDUMP) &ramdump_module, #endif }; struct coreinfo_module *firmware_modules[] = { -#ifdef CONFIG_MODULE_COREBOOT +#if IS_ENABLED(CONFIG_MODULE_COREBOOT) &coreboot_module, #endif -#ifdef CONFIG_MODULE_MULTIBOOT +#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT) &multiboot_module, #endif -#ifdef CONFIG_MODULE_BOOTLOG +#if IS_ENABLED(CONFIG_MODULE_BOOTLOG) &bootlog_module, #endif -#ifdef CONFIG_MODULE_LAR +#if IS_ENABLED(CONFIG_MODULE_LAR) &lar_module, #endif -#ifdef CONFIG_MODULE_CBFS +#if IS_ENABLED(CONFIG_MODULE_CBFS) &cbfs_module, #endif }; @@ -121,7 +121,7 @@ static void print_submenu(struct coreinfo_cat *cat) mvwprintw(menuwin, 0, 0, menu); } -#ifdef CONFIG_SHOW_DATE_TIME +#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) static void print_time_and_date(void) { struct tm tm; @@ -156,7 +156,7 @@ static void print_menu(void) mvwprintw(menuwin, 1, 0, menu); -#ifdef CONFIG_SHOW_DATE_TIME +#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) print_time_and_date(); #endif } @@ -234,7 +234,7 @@ static void loop(void) halfdelay(10); while (1) { -#ifdef CONFIG_SHOW_DATE_TIME +#if IS_ENABLED(CONFIG_SHOW_DATE_TIME) print_time_and_date(); wrefresh(menuwin); #endif @@ -271,7 +271,7 @@ int main(void) { int i, j; -#if defined(CONFIG_USB) +#if IS_ENABLED(CONFIG_LP_USB) usb_initialize(); #endif diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c index cd42eb3..a209141 100644 --- a/payloads/coreinfo/cpuinfo_module.c +++ b/payloads/coreinfo/cpuinfo_module.c @@ -22,7 +22,7 @@ #include "coreinfo.h" -#ifdef CONFIG_MODULE_CPUINFO +#if IS_ENABLED(CONFIG_MODULE_CPUINFO) #include <arch/rdtsc.h> #define VENDOR_INTEL 0x756e6547 diff --git a/payloads/coreinfo/lar_module.c b/payloads/coreinfo/lar_module.c index 8404efa..e50d98f 100644 --- a/payloads/coreinfo/lar_module.c +++ b/payloads/coreinfo/lar_module.c @@ -19,7 +19,7 @@ #include "coreinfo.h" -#ifdef CONFIG_MODULE_LAR +#if IS_ENABLED(CONFIG_MODULE_LAR) static struct LAR *lar; static int lcount, selected; diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index 86206c2..225b401 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -20,7 +20,7 @@ #include <multiboot_tables.h> #include "coreinfo.h" -#ifdef CONFIG_MODULE_MULTIBOOT +#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT) #define MAX_MEMORY_COUNT 10 diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c index 50cc3e6..8d9eefe 100644 --- a/payloads/coreinfo/nvram_module.c +++ b/payloads/coreinfo/nvram_module.c @@ -19,7 +19,7 @@ #include "coreinfo.h" -#ifdef CONFIG_MODULE_NVRAM +#if IS_ENABLED(CONFIG_MODULE_NVRAM) /** * Dump 256 bytes of NVRAM. diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c index b864d1a..d3d037c 100644 --- a/payloads/coreinfo/pci_module.c +++ b/payloads/coreinfo/pci_module.c @@ -22,7 +22,7 @@ #include <libpayload.h> #include "coreinfo.h" -#ifdef CONFIG_MODULE_PCI +#if IS_ENABLED(CONFIG_MODULE_PCI) struct pci_devices { pcidev_t device; diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c index f1ac043..6a691b3 100644 --- a/payloads/coreinfo/ramdump_module.c +++ b/payloads/coreinfo/ramdump_module.c @@ -19,7 +19,7 @@ #include "coreinfo.h" -#ifdef CONFIG_MODULE_RAMDUMP +#if IS_ENABLED(CONFIG_MODULE_RAMDUMP) static s64 cursor = 0; static s64 cursor_max = (1 * 1024 * 1024 * 1024); /* Max. 1 GB RAM for now. */

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New patch to review for coreboot: nvidia/tegra210: reserve more room for the romstage in vboot builds
by Patrick Georgi June 30, 2015

June 30, 2015

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10733 -gerrit commit 76783ef86b8dacaac1693d9adb6a6fa88c8b505a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 21:59:23 2015 +0200 nvidia/tegra210: reserve more room for the romstage in vboot builds Change-Id: I11c2e270179c54af8687435ff662a509ac714505 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index 7aa98e0..5c8f346 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -37,8 +37,8 @@ SECTIONS VBOOT2_WORK(0x40014000, 16K) STACK(0x40018000, 2K) BOOTBLOCK(0x40019000, 24K) - VERSTAGE(0x4001F000, 56K) - ROMSTAGE(0x4002D000, 76K) + VERSTAGE(0x4001F000, 52K) + ROMSTAGE(0x4002C000, 80K) SRAM_END(0x40040000) DRAM_START(0x80000000)

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New patch to review for coreboot: google/foster: roll up fixes to compile with vboot
by Patrick Georgi June 30, 2015

June 30, 2015

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10732 -gerrit commit 12b2c582abf75ddd3a7f159a3a8baa42fd82dee4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 30 21:58:45 2015 +0200 google/foster: roll up fixes to compile with vboot Change-Id: I796e0fa64f9a858a54b09a82fbec1f0576e7e124 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/foster/Makefile.inc | 1 + src/mainboard/google/foster/memlayout.ld | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/foster/Makefile.inc b/src/mainboard/google/foster/Makefile.inc index 29478c0..f9fd32b 100644 --- a/src/mainboard/google/foster/Makefile.inc +++ b/src/mainboard/google/foster/Makefile.inc @@ -43,6 +43,7 @@ romstage-y += chromeos.c ramstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += reset.c +ramstage-y += chromeos.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/mainboard/google/foster/memlayout.ld b/src/mainboard/google/foster/memlayout.ld index a71dcb8..c53f744 100644 --- a/src/mainboard/google/foster/memlayout.ld +++ b/src/mainboard/google/foster/memlayout.ld @@ -1,4 +1,4 @@ -#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) +#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) #include <soc/memlayout_vboot2.ld> #else #include <soc/memlayout.ld>

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