July 2013 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: 45c5008 ARM: Define custom ELF headers for ARM.
by Gabe Black July 1, 2013

July 1, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3580 -gerrit commit 45c50082ca4c68b3bea0fcb7f639279848e52dda Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 05:03:47 2013 -0700 ARM: Define custom ELF headers for ARM. At least when building with the gnu toolchain, the headers the linker automatically generate save space for the actual ELF headers in one of the loadable segments. This creates two problems. First, the data you intended to be at the start of the image doesn't actually show up there, it's actually the ELF headers. Second, the ELF headers are essentially useless for firmware since there's currently nothing to tell you where they are, and even if there was, there isn't much of a reason to look at them. They're useful in userspace for, for instance, the dynamic linker, but not really in firmware. This change adds a PHDRS construct to each of the linker scripts used on ARM which define a single segment called to_load which does not have the flag set which would tell the linker to put headers in it. The first section defined in the script has ": to_load" to tell the linker which segment to put it in, and from that point on the other sections go in there by default. Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/bootblock.lds | 7 ++++++- src/arch/armv7/coreboot_ram.ld | 7 ++++++- src/arch/armv7/romstage.ld | 7 ++++++- 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 6f6040d..2003ce4 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -22,6 +22,11 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) +PHDRS +{ + to_load PT_LOAD; +} + TARGET(binary) SECTIONS { @@ -40,7 +45,7 @@ SECTIONS *(.rom.data.*); *(.rodata.*); _erom = .; - } = 0xff + } : to_load = 0xff /DISCARD/ : { *(.comment) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 487f610..38eaca3 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -24,6 +24,11 @@ INCLUDE ldoptions ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { . = CONFIG_SYS_SDRAM_BASE; @@ -38,7 +43,7 @@ SECTIONS *(.text.*); . = ALIGN(16); _etext = .; - } + } : to_load .ctors : { . = ALIGN(0x100); diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 568ac1a..0555fc4 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -30,6 +30,11 @@ OUTPUT_ARCH(arm) ENTRY(stage_entry) +PHDRS +{ + to_load PT_LOAD; +} + SECTIONS { /* TODO make this a configurable option (per chipset). */ @@ -41,7 +46,7 @@ SECTIONS *(.text.stage_entry.armv7); *(.text.startup); *(.text); - } + } : to_load .romdata . : { *(.rodata);

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Patch set updated for coreboot: a39ced3 am335x: Fix the address of the pinmux registers.
by Gabe Black July 1, 2013

July 1, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3574 -gerrit commit a39ced39afbbb03a406ed5f7a725f029a38f5477 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the control module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/pinmux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 69c1459..1b488e8 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -54,7 +54,7 @@ void am335x_pinmux_mii1(void); void am335x_pinmux_nand(void); -#define AM335X_PINMUX_REG_ADDR 0x44e10000 +#define AM335X_PINMUX_REG_ADDR 0x44e10800 struct am335x_pinmux_regs { uint32_t gpmc_ad0;

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New patch to review for coreboot: 2bcc54c CBFS: Use memmove instead of memcpy when loading a file from CBFS.
by Gabe Black July 1, 2013

July 1, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3577 -gerrit commit 2bcc54c6b01a3a9853d1e0e5f542951d9ee56519 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:28:23 2013 -0700 CBFS: Use memmove instead of memcpy when loading a file from CBFS. It might be the case that a file is being loaded from a portion of CBFS which has already been loaded into a limitted bit of memory somewhere, and we want to load that file in place, effectively, so that it's original location in CBFS overlaps with its new location. That's only guaranteed to work if you use memmove instead of memcpy. One significant downside of this change is that there aren't yet architecture optimized (aka not horribly performing) implementations of memmove available for either x86 or ARM. It's not clear whether the performance difference would be significant enough to notice in practice since the things in CBFS are probably not that big. It might still be a good idea to hold off on this change until optimized versions are available to avoid any potential performance hit. This also means that memmove needs to be built into the bootblock. Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/cbfs_core.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d44f4a7..50092b6 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -26,6 +26,7 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) bootblock-y += memcpy.c endif bootblock-y += memcmp.c +bootblock-y += memmove.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) romstage-y += memset.c diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 852b37f..39c1ff6 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -195,7 +195,7 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) { switch (algo) { case CBFS_COMPRESS_NONE: - memcpy(dst, src, len); + memmove(dst, src, len); return 0; #ifdef CBFS_CORE_WITH_LZMA case CBFS_COMPRESS_LZMA:

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New patch to review for coreboot: 54510a7 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki July 1, 2013

July 1, 2013

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3576 -gerrit commit 54510a73fb3904dc468130ec2ca4bbe86878f1cf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/google/stout/Kconfig | 1 - src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 8 ++++++++ src/northbridge/intel/sandybridge/bootblock.c | 26 ++++++++++++++++++++++++++ src/northbridge/intel/sandybridge/early_init.c | 2 -- 11 files changed, 34 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index d41a9f5..be585c7 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 4bddc5f..f62d690 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 3081b5a..dbdb5fa 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index a15d933..a5b7962 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select CHROMEOS diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 20685f3..786e9a8 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select GFXUMA #select CHROMEOS select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index dafc959..97d8e5c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select GFXUMA select EXTERNAL_MRC_BLOB diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index a169726..1c18ec2 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select MMCONF_SUPPORT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index fa7d03d..f4df8a9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select MMCONF_SUPPORT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3a65782..59b6187 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,11 +20,15 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX if NORTHBRIDGE_INTEL_SANDYBRIDGE @@ -103,6 +107,10 @@ endif if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/sandybridge/bootblock.c" + config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c new file mode 100644 index 0000000..1c1d492 --- /dev/null +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -0,0 +1,26 @@ +#include <arch/io.h> + +/* Just re-define this instead of including sandybridge.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..583385b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -49,8 +49,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);

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Patch set updated for coreboot: 1e23cd1 am335x: Implement support for the UART.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490 -gerrit commit 1e23cd167c89fb5fa1ef44bf729589d57cfae36e Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Jun 11 21:58:18 2013 -0400 am335x: Implement support for the UART. This patch was started by Dave Hendricks and implements the procedure for setting up the UART as described in the manual. Some unused code was removed. Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/uart.c | 178 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 123 insertions(+), 55 deletions(-) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index fdf5c05..395ed86 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,9 +1,5 @@ /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * based on drivers/serial/s3c64xx.c + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ +#include <config.h> #include <types.h> #include <uart.h> #include <arch/io.h> @@ -29,9 +25,14 @@ #include <cpu/ti/am335x/uart.h> -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define EFR_ENHANCED_EN (1 << 4) +#define FCR_FIFO_EN (1 << 0) +#define MCR_TCR_TLR (1 << 6) +#define SYSC_SOFTRESET (1 << 1) +#define SYSS_RESETDONE (1 << 0) + +#define LSR_RXFIFOE (1 << 0) +#define LSR_TXFIFOE (1 << 5) /* * Initialise the serial port with the given baudrate. The settings @@ -39,28 +40,109 @@ */ static void am335x_uart_init_dev(void) { - /* FIXME: implement this - * ref: section 19.4.1.1.1 for reset - * ref: section 19.4.1.1.2 for FIFO, skip DMA - * ref: section 19.4.1.1.3 for baud rate, skip - * interrupts and protocol stuff. - * */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(); -#endif + struct am335x_uart *uart = (struct am335x_uart *) + CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + uint16_t lcr_orig, efr_orig, mcr_orig; + + /* reset the UART */ + write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + while (!(read16(&uart->syss) & SYSS_RESETDONE)) + ; + + /* 1. switch to register config mode B */ + lcr_orig = read16(&uart->lcr); + write16(0xbf, &uart->lcr); + + /* + * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must + * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. + */ + efr_orig = read16(&uart->efr); + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 3. Switch to register config mode A */ + write16(0x80, &uart->lcr); + + /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ + mcr_orig = read16(&uart->mcr); + write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + + /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ + write16(FCR_FIFO_EN, &uart->fcr); + + /* 6. Switch to configuration mode B */ + write16(0xbf, &uart->lcr); + /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ + + /* 9. Restore original EFR value */ + write16(efr_orig, &uart->efr); + + /* 10. Switch to config mode A */ + write16(0x80, &uart->lcr); + + /* 11. Restore original MCR value */ + write16(mcr_orig, &uart->mcr); + + /* 12. Restore original LCR value */ + write16(lcr_orig, &uart->lcr); + + /* Protocol, baud rate and interrupt settings */ + + /* 1. Disable UART access to DLL and DLH registers */ + write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + + /* 2. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 3. Enable access to IER[7:4] */ + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 4. Switch to operational mode */ + write16(0x0, &uart->lcr); + + /* 5. Clear IER */ + write16(0x0, &uart->ier); + + /* 6. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 7. Set dll and dlh to the desired values (table 19-25) */ + if (CONFIG_CONSOLE_SERIAL_9600) { + write16(0x01, &uart->dlh); + write16(0x38, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_19200) { + write16(0x00, &uart->dlh); + write16(0x9c, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_38400) { + write16(0x00, &uart->dlh); + write16(0x4e, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_57600) { + write16(0x00, &uart->dlh); + write16(0x34, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_115200) { + write16(0x00, &uart->dlh); + write16(0x1a, &uart->dll); + } else { + /* Unrecognized baud rate? */ + } + + /* 8. Switch to operational mode to access ier */ + write16(0x0, &uart->lcr); + + /* 9. Clear ier to disable all interrupts */ + write16(0x0, &uart->ier); + + /* 10. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 11. Restore efr */ + write16(efr_orig, &uart->efr); + + /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ + write16(0x3, &uart->lcr); + + /* 13. Load the new UART mode */ + write16(0x0, &uart->mdr1); } /* @@ -70,20 +152,12 @@ static void am335x_uart_init_dev(void) */ static unsigned char am335x_uart_rx_byte(void) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - return readb(&uart->urxh) & 0xff; -#endif - return 0xaa; + while (!(read16(&uart->lsr) & LSR_RXFIFOE)); + + return read8(&uart->rhr); } /* @@ -91,18 +165,12 @@ static unsigned char am335x_uart_rx_byte(void) */ static void am335x_uart_tx_byte(unsigned char data) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - writeb(data, &uart->utxh); -#endif + while (!(read16(&uart->lsr) & LSR_TXFIFOE)); + + return write8(data, &uart->thr); } uint32_t uartmem_getbaseaddr(void)

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Patch set updated for coreboot: 5edc866 beaglebone: Enable the clocks and pins for the configured UART.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3573 -gerrit commit 5edc86659f561d314fa42373293fe37340b7717c Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 23:20:14 2013 -0700 beaglebone: Enable the clocks and pins for the configured UART. Set up the pinmux to enable the pins and the clocks for whichever UART is currently configured. Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index fbe73ea..6c7d132 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,10 +21,13 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/pinmux.h> void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + void *uart_clock_ctrl = NULL; + /* Enable the GPIO module */ writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); @@ -38,6 +41,29 @@ void bootblock_mainboard_init(void) clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + /* Set up the UART we're going to use */ + if (CONFIG_CONSOLE_SERIAL_UART0) { + am335x_pinmux_uart0(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + } else if (CONFIG_CONSOLE_SERIAL_UART1) { + am335x_pinmux_uart1(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + } else if (CONFIG_CONSOLE_SERIAL_UART2) { + am335x_pinmux_uart2(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + } else if (CONFIG_CONSOLE_SERIAL_UART3) { + am335x_pinmux_uart3(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + } else if (CONFIG_CONSOLE_SERIAL_UART4) { + am335x_pinmux_uart4(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + } else if (CONFIG_CONSOLE_SERIAL_UART5) { + am335x_pinmux_uart5(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + } + if (uart_clock_ctrl) + writel(0x2, uart_clock_ctrl); + /* Start monotonic timer */ //rtc_start();

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Patch set updated for coreboot: a5de8d4 am335x: Fix the address of the pinmux registers.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3574 -gerrit commit a5de8d4db2fca79f074dbbc23fe5b297ba906324 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the cotrnol module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/pinmux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 69c1459..1b488e8 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -54,7 +54,7 @@ void am335x_pinmux_mii1(void); void am335x_pinmux_nand(void); -#define AM335X_PINMUX_REG_ADDR 0x44e10000 +#define AM335X_PINMUX_REG_ADDR 0x44e10800 struct am335x_pinmux_regs { uint32_t gpmc_ad0;

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Patch set updated for coreboot: e0c6259 am335x: Implement support for the Uart.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490 -gerrit commit e0c62592c9b792092cab40cce95de0028675e145 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Jun 11 21:58:18 2013 -0400 am335x: Implement support for the Uart. This patch was started by Dave Hendricks and implements the procedure for setting up the UART as described in the manual. Some unused code was removed. Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/uart.c | 178 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 123 insertions(+), 55 deletions(-) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index fdf5c05..395ed86 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,9 +1,5 @@ /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * based on drivers/serial/s3c64xx.c + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ +#include <config.h> #include <types.h> #include <uart.h> #include <arch/io.h> @@ -29,9 +25,14 @@ #include <cpu/ti/am335x/uart.h> -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define EFR_ENHANCED_EN (1 << 4) +#define FCR_FIFO_EN (1 << 0) +#define MCR_TCR_TLR (1 << 6) +#define SYSC_SOFTRESET (1 << 1) +#define SYSS_RESETDONE (1 << 0) + +#define LSR_RXFIFOE (1 << 0) +#define LSR_TXFIFOE (1 << 5) /* * Initialise the serial port with the given baudrate. The settings @@ -39,28 +40,109 @@ */ static void am335x_uart_init_dev(void) { - /* FIXME: implement this - * ref: section 19.4.1.1.1 for reset - * ref: section 19.4.1.1.2 for FIFO, skip DMA - * ref: section 19.4.1.1.3 for baud rate, skip - * interrupts and protocol stuff. - * */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(); -#endif + struct am335x_uart *uart = (struct am335x_uart *) + CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + uint16_t lcr_orig, efr_orig, mcr_orig; + + /* reset the UART */ + write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + while (!(read16(&uart->syss) & SYSS_RESETDONE)) + ; + + /* 1. switch to register config mode B */ + lcr_orig = read16(&uart->lcr); + write16(0xbf, &uart->lcr); + + /* + * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must + * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. + */ + efr_orig = read16(&uart->efr); + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 3. Switch to register config mode A */ + write16(0x80, &uart->lcr); + + /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ + mcr_orig = read16(&uart->mcr); + write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + + /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ + write16(FCR_FIFO_EN, &uart->fcr); + + /* 6. Switch to configuration mode B */ + write16(0xbf, &uart->lcr); + /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ + + /* 9. Restore original EFR value */ + write16(efr_orig, &uart->efr); + + /* 10. Switch to config mode A */ + write16(0x80, &uart->lcr); + + /* 11. Restore original MCR value */ + write16(mcr_orig, &uart->mcr); + + /* 12. Restore original LCR value */ + write16(lcr_orig, &uart->lcr); + + /* Protocol, baud rate and interrupt settings */ + + /* 1. Disable UART access to DLL and DLH registers */ + write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + + /* 2. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 3. Enable access to IER[7:4] */ + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 4. Switch to operational mode */ + write16(0x0, &uart->lcr); + + /* 5. Clear IER */ + write16(0x0, &uart->ier); + + /* 6. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 7. Set dll and dlh to the desired values (table 19-25) */ + if (CONFIG_CONSOLE_SERIAL_9600) { + write16(0x01, &uart->dlh); + write16(0x38, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_19200) { + write16(0x00, &uart->dlh); + write16(0x9c, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_38400) { + write16(0x00, &uart->dlh); + write16(0x4e, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_57600) { + write16(0x00, &uart->dlh); + write16(0x34, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_115200) { + write16(0x00, &uart->dlh); + write16(0x1a, &uart->dll); + } else { + /* Unrecognized baud rate? */ + } + + /* 8. Switch to operational mode to access ier */ + write16(0x0, &uart->lcr); + + /* 9. Clear ier to disable all interrupts */ + write16(0x0, &uart->ier); + + /* 10. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 11. Restore efr */ + write16(efr_orig, &uart->efr); + + /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ + write16(0x3, &uart->lcr); + + /* 13. Load the new UART mode */ + write16(0x0, &uart->mdr1); } /* @@ -70,20 +152,12 @@ static void am335x_uart_init_dev(void) */ static unsigned char am335x_uart_rx_byte(void) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - return readb(&uart->urxh) & 0xff; -#endif - return 0xaa; + while (!(read16(&uart->lsr) & LSR_RXFIFOE)); + + return read8(&uart->rhr); } /* @@ -91,18 +165,12 @@ static unsigned char am335x_uart_rx_byte(void) */ static void am335x_uart_tx_byte(unsigned char data) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - writeb(data, &uart->utxh); -#endif + while (!(read16(&uart->lsr) & LSR_TXFIFOE)); + + return write8(data, &uart->thr); } uint32_t uartmem_getbaseaddr(void)

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Patch set updated for coreboot: e2e6b1c beaglebone: Enable the clocks and pins for the configured UART.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3573 -gerrit commit e2e6b1ccbec079161e85de78f2dc8a9bc02fc3ca Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 23:20:14 2013 -0700 beaglebone: Enable the clocks and pins for the configured UART. Set up the pinmux to enable the pins and the clocks for whichever UART is currently configured. Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index fbe73ea..6c7d132 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,10 +21,13 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/pinmux.h> void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + void *uart_clock_ctrl = NULL; + /* Enable the GPIO module */ writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); @@ -38,6 +41,29 @@ void bootblock_mainboard_init(void) clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + /* Set up the UART we're going to use */ + if (CONFIG_CONSOLE_SERIAL_UART0) { + am335x_pinmux_uart0(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + } else if (CONFIG_CONSOLE_SERIAL_UART1) { + am335x_pinmux_uart1(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + } else if (CONFIG_CONSOLE_SERIAL_UART2) { + am335x_pinmux_uart2(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + } else if (CONFIG_CONSOLE_SERIAL_UART3) { + am335x_pinmux_uart3(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + } else if (CONFIG_CONSOLE_SERIAL_UART4) { + am335x_pinmux_uart4(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + } else if (CONFIG_CONSOLE_SERIAL_UART5) { + am335x_pinmux_uart5(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + } + if (uart_clock_ctrl) + writel(0x2, uart_clock_ctrl); + /* Start monotonic timer */ //rtc_start();

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Patch set updated for coreboot: 32ee748 am335x: Fix the address of the pinmux registers.
by Gabe Black June 30, 2013

June 30, 2013

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3574 -gerrit commit 32ee748da1be7f9ca079e10ddd013b589a96a545 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the cotrnol module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/pinmux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 69c1459..1b488e8 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -54,7 +54,7 @@ void am335x_pinmux_mii1(void); void am335x_pinmux_nand(void); -#define AM335X_PINMUX_REG_ADDR 0x44e10000 +#define AM335X_PINMUX_REG_ADDR 0x44e10800 struct am335x_pinmux_regs { uint32_t gpmc_ad0;

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