[SerialICE] Patch set updated for serialice: 134be6c southbridge/amd-sbxxx.c: Init clock to 48 MHz on AMD SB800
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Fri Feb 14 09:57:04 CET 2014
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5213
-gerrit
commit 134be6c775289fa124141d5c9de0b240155cce8c
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Mon Jul 15 13:31:51 2013 +0200
southbridge/amd-sbxxx.c: Init clock to 48 MHz on AMD SB800
Copy the init from coreboot’s `src/southbridge/amd/cimx/sb800/bootblock.c`.
Daniel Gröber showed my error in forgetting to actually enable the
clock of 48 MHz so it did not work for me with 14 MHz.
The Super I/O SMSC SCH311x needs 14 MHz so the Kconfig option is
ported over.
Change-Id: I9146d2c0620c2bb338130f55ead0704fa82075c7
Signed-off-by: Daniel Gröber <dxld at darkboxed.org>
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
SerialICE/southbridge/amd-sbxxx.c | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c
index 27b6b3b..d246a04 100644
--- a/SerialICE/southbridge/amd-sbxxx.c
+++ b/SerialICE/southbridge/amd-sbxxx.c
@@ -30,17 +30,22 @@
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+
static void sbxxx_enable_48mhzout(void)
{
- /* most likely programming to 48MHz out signal */
u32 reg32;
- reg32 = SB_MMIO_MISC32(0x28);
- reg32 &= 0xffc7ffff;
- reg32 |= 0x00100000;
- SB_MMIO_MISC32(0x28) = reg32;
+ // Program SB800 MiscClkCntrl register to configure clock output on the
+ // 14M_25M_48M_OSC ball usually used for the Super-I/O.
+ // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz,
+ // which is the SB800's power up default. We could switch back to 14
+ // in the mainboard's romstage.c, but then the clock frequency would
+ // change twice.
reg32 = SB_MMIO_MISC32(0x40);
- reg32 &= ~0x80u;
+ reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)
+#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK
+ reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz
+#endif
SB_MMIO_MISC32(0x40) = reg32;
}
@@ -59,9 +64,12 @@ static void southbridge_init(void)
pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc4), 0x0000f000);
pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc0), 0x00000003);
- /* SB MMIO range decode enable */
+ // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ reg8 = inb(0xcd7);
+ reg8 |= 1;
+ reg8 &= ~(1 << 1);
+ outb(reg8, 0xcd7);
/* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8 */
pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6));
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