[SerialICE] New patch to review for serialice: 2a38b3e [RFC] Ugly hack to enable code sharing of common code
Stefan Tauner (stefan.tauner@gmx.at)
gerrit at coreboot.org
Sun Oct 14 08:10:23 CEST 2012
Stefan Tauner (stefan.tauner at gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1580
-gerrit
commit 2a38b3e647cbd64342b5eaa12bc169bca8afd701
Author: Stefan Tauner <stefan.tauner at gmx.at>
Date: Sun Oct 14 08:04:00 2012 +0200
[RFC] Ugly hack to enable code sharing of common code
I have tried it in the usual and sane way with prototypes, but...
romcc spits this in my face: Function prototypes not supported
But obviously something like this has to be done... maybe even
merge serialice with coreboot and use its code?
Change-Id: I09f9194b1101cb0f1d16b8e32cc276dc77022ab2
Signed-off-by: Stefan Tauner <stefan.tauner at gmx.at>
---
SerialICE/mainboard/intel_d945gclf.c | 39 +------------------
SerialICE/southbridge/intel-ich7.c | 73 ------------------------------------
SerialICE/southbridge/intel-ich7.h | 71 +++++++++++++++++++++++++++++++++++
3 files changed, 73 insertions(+), 110 deletions(-)
diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c
index 2b10266..e90c995 100644
--- a/SerialICE/mainboard/intel_d945gclf.c
+++ b/SerialICE/mainboard/intel_d945gclf.c
@@ -19,6 +19,8 @@
/* This is a chipset init file for the Intel D945GCLF/D945GNT mainboards */
+#include "intel-ich7.h"
+
#if defined(CONFIG_BOARD_INTEL_D945GCLF)
const char boardname[33]="Intel D945GCLF ";
#elif defined(CONFIG_BOARD_INTEL_D945GNT)
@@ -35,43 +37,6 @@ const char boardname[33]="Intel D946GZIS ";
#define GCS 0x3410
#define RCBA32(x) *((volatile u32 *)(RCBA + x))
-static void southbridge_init(void)
-{
- u16 reg16;
- u32 reg32;
-
- // Set up RCBA
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
-
-#if 0
- // port80 writes go to LPC:
- reg32 = RCBA32(GCS);
- reg32 = reg32 & ~0x04;
- RCBA32(GCS) = reg32;
- outb(0x23, 0x80);
-#endif
-
- // Enable Serial IRQ
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0);
- // Set COM1 decode range
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
- // Enable COM1
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x140d);
- // Enable SIO PM Events at 0x680
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x007c0681);
-
- // Disable watchdog
-#define PMBASE 0x500
-#define TCOBASE (PMBASE + 0x60)
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
- reg16 = inw(TCOBASE + 0x08);
- reg16 |= (1 << 11);
- outw(reg16, TCOBASE + 0x08);
- outw(0x0008, TCOBASE + 0x04);
- outw(0x0002, TCOBASE + 0x06);
-}
-
static void superio_init(u8 cfg_port, u8 com_port, u8 pm)
{
pnp_enter_ext_func_mode_alt(cfg_port);
diff --git a/SerialICE/southbridge/intel-ich7.c b/SerialICE/southbridge/intel-ich7.c
deleted file mode 100644
index 3688084..0000000
--- a/SerialICE/southbridge/intel-ich7.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * SerialICE
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This initializes Intel's ICH7 that
- * o the Super IO is accessible,
- * o legacy serial port I/O ports are decoded,
- * o the watchdog is turned off
- */
-
-#define RCBA 0xfed1c000
-#define GCS 0x3410
-#define RCBA32(x) *((volatile u32 *)(RCBA + x))
-
-static void southbridge_init(void)
-{
- u16 reg16;
- u32 reg32;
-
- // Set up RCBA
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
-
-#if 0
- // port80 writes go to LPC:
- reg32 = RCBA32(GCS);
- reg32 = reg32 & ~0x04;
- RCBA32(GCS) = reg32;
- outb(0x23, 0x80);
-#endif
-
- // Enable Serial IRQ
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0);
- // Set COM1/COM2 decode range
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
- // Enable COM1/COM2/KBD/SuperIO1+2
- pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b);
- // Enable HWM at 0xa00
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01);
- // COM3 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9);
- // COM4 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9);
- // io 0x300 decode
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301);
-
- // Disable watchdog
-#define PMBASE 0x500
-#define TCOBASE (PMBASE + 0x60)
- pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
- pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
- reg16 = inw(TCOBASE + 0x08);
- reg16 |= (1 << 11);
- outw(reg16, TCOBASE + 0x08);
- outw(0x0008, TCOBASE + 0x04);
- outw(0x0002, TCOBASE + 0x06);
-}
-
-
diff --git a/SerialICE/southbridge/intel-ich7.h b/SerialICE/southbridge/intel-ich7.h
new file mode 100644
index 0000000..f3782a8
--- /dev/null
+++ b/SerialICE/southbridge/intel-ich7.h
@@ -0,0 +1,71 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This initializes Intel's ICH7 that
+ * o the Super IO is accessible,
+ * o legacy serial port I/O ports are decoded,
+ * o the watchdog is turned off
+ */
+
+#define RCBA 0xfed1c000
+#define GCS 0x3410
+#define RCBA32(x) *((volatile u32 *)(RCBA + x))
+
+void southbridge_init(void)
+{
+ u16 reg16;
+ u32 reg32;
+
+ // Set up RCBA
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0xf0), RCBA | 1);
+
+#if 0
+ // port80 writes go to LPC:
+ reg32 = RCBA32(GCS);
+ reg32 = reg32 & ~0x04;
+ RCBA32(GCS) = reg32;
+ outb(0x23, 0x80);
+#endif
+
+ // Enable Serial IRQ
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x64), 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x80), 0x0010);
+ // Enable COM1/COM2/KBD/SuperIO1+2
+ pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0x82), 0x340b);
+ // Enable HWM at 0xa00
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x84), 0x00fc0a01);
+ // COM3 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x88), 0x000403e9);
+ // COM4 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x8c), 0x000402e9);
+ // io 0x300 decode
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x90), 0x00000301);
+
+ // Disable watchdog
+#define PMBASE 0x500
+#define TCOBASE (PMBASE + 0x60)
+ pci_write_config32(PCI_ADDR(0, 0x1f, 0, 0x40), PMBASE | 1);
+ pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0x44), 0x80);
+ reg16 = inw(TCOBASE + 0x08);
+ reg16 |= (1 << 11);
+ outw(reg16, TCOBASE + 0x08);
+ outw(0x0008, TCOBASE + 0x04);
+ outw(0x0002, TCOBASE + 0x06);
+}
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