[SerialICE] New patch to review for serialice: e5ded32 Add SerialICE support for ASRock P4i65GV.

[Idwer Vollering (vidwer@gmail.com)]

Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/419

-gerrit

commit e5ded32a903c7b283702080df0acd26d332ca791
Author: Idwer Vollering <vidwer at gmail.com>
Date:   Sun Nov 6 01:05:40 2011 +0100

    Add SerialICE support for ASRock P4i65GV.
    
    Change-Id: I67c5e999675d0bd29fab890f905407b0259f9c2c
    Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
 SerialICE/Kconfig                    |   12 ++-----
 SerialICE/mainboard/asrock_p4i65gv.c |   57 ++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 655e3f4..111a12f 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -50,11 +50,6 @@ config BOARD_ASUS_M2V_MX_SE
 	select VIA_ROMSTRAP
 	select BUILD_XMMSTACK
 
-config BOARD_ASUS_K8V_X
-	bool "ASUS K8V-X"
-	select VIA_ROMSTRAP
-	select BUILD_XMMSTACK
-
 config BOARD_ASUS_M4A77TD_PRO
 	bool "ASUS M4A77TD-PRO"
 	select BUILD_XMMSTACK
@@ -96,6 +91,9 @@ config BOARD_HP_DL165_G6
 config BOARD_WYSE_S50
 	bool "WYSE S50"
 
+config BOARD_ASROCK_P4I65GV
+	bool "ASRock P4i65GV"
+
 endchoice
 
 config BOARD_INIT
@@ -107,7 +105,6 @@ config BOARD_INIT
 	default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF
 	default "dell_s1850.c" if BOARD_DELL_S1850
 	default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE
-	default "asus_k8v-x.c" if BOARD_ASUS_K8V_X
 	default "msi_ms6178.c" if BOARD_MSI_MS6178
 	default "rca_rm4100.c" if BOARD_RCA_RM4100
 	default "thomson_ip1000.c" if BOARD_THOMSON_IP1000
@@ -120,6 +117,7 @@ config BOARD_INIT
 	default "tyan_s2912.c" if BOARD_TYAN_S2912
 	default "hp_dl165_g6.c" if BOARD_HP_DL165_G6
 	default "wyse_s50.c" if BOARD_WYSE_S50
+	default "asrock_p4i65gv.c" if BOARD_ASROCK_P4I65GV
 choice
 	prompt "Target communication"
 
@@ -309,5 +307,3 @@ config BUILD_XMMSTACK
 	bool
 	select HAVE_SSE
 	depends on !EXPERT
-
-
diff --git a/SerialICE/mainboard/asrock_p4i65gv.c b/SerialICE/mainboard/asrock_p4i65gv.c
new file mode 100644
index 0000000..d0f46f4
--- /dev/null
+++ b/SerialICE/mainboard/asrock_p4i65gv.c
@@ -0,0 +1,57 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2011 Idwer Vollering <vidwer at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+const char boardname[33]="ASRock P4i65GV                  ";
+
+#define SUPERIO_CONFIG_PORT 0x2e
+
+/* Hardware specific functions */
+static void mainboard_set_ich5(void)
+{
+	/* COM_DEC */ /* COMA at 0x3f8, COMB at 0x3f8 */
+        pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe0), 0x0);
+	/* LPC_EN */ /* FDD_LPC_EN=1, KBC_LPC_EN=1, CNF1_LPC_EN=1 */
+        pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xe6), 0x1408);
+	/* FB_DEC_EN1 */ /* FN_F8_EN=1, decode two 512 kilobyte flash ranges */
+        pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xe3), 0x80);
+	/* FB_DEC_EN2 */ /* don't decode two 1 megabyte ranges */
+        pci_write_config8(PCI_ADDR(0, 0x1f, 0, 0xf0), 0x0);
+	/* FUNC_DIS */ /* D31_F6_DISABLE=1 (AC97 modem) */
+        pci_write_config16(PCI_ADDR(0, 0x1f, 0, 0xf2), 0x0040);
+}
+
+/* Winbond W83627HG */
+static void superio_init(void)
+{
+        pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT);
+	/* Set the clock to 48MHz */
+        pnp_write_register(SUPERIO_CONFIG_PORT, 0x24, 0xc0);
+        pnp_set_logical_device(SUPERIO_CONFIG_PORT, 2);
+        pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
+        pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
+        pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
+        pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
+        pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT);
+}
+
+static void chipset_init(void)
+{
+        mainboard_set_ich5();
+        superio_init();
+}