[SeaBIOS] [Qemu-devel] [RESEND PATCH v2 1/2] seabios q35: Enable all PIRQn IRQs at startup
Kevin O'Connor
kevin at koconnor.net
Thu Feb 21 05:23:00 CET 2013
On Fri, Feb 15, 2013 at 02:11:35PM -0700, Alex Williamson wrote:
> We seem to use the IRQEN bit of the PIRQn registers interchangeably
> to select APIC mode or to disable an IRQ. I can't decide if we're
> intending to disable the IRQ or select APIC mode here, but in either
> case it prevents PIC mode assigned devices from working. When seabios
> writes IRQEN to these registers, qemu interprets that as APIC mode,
> so while the boot ROM driver is waiting for an interrupt on ISA
> compatible IRQ 10 or 11, KVM is injecting interrupts to APIC pins
> 16 - 23. Devices on the root bus use PIRQE:H while the root ports
> use PIRQA:D. Enable them all so we don't limit where we support boot
> ROMs. The guest will later disable unused IRQs with the ACPI _DIS
> method.
Thanks. I committed this change.
-Kevin
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