[SeaBIOS] [RFC PATCH v4 18/30] Introduce paravirt interface QEMU_CFG_PCI_WINDOW
Vasilis Liaskovitis
vasilis.liaskovitis at profitbricks.com
Tue Dec 18 13:41:46 CET 2012
Qemu calculates the 32-bit and 64-bit PCI starting offsets based on
initial memory and hotplug-able dimms. This info needs to be passed to Seabios
for PCI initialization.
Signed-off-by: Vasilis Liaskovitis <vasilis.liaskovitis at profitbricks.com>
---
hw/fw_cfg.h | 1 +
hw/pc_piix.c | 10 ++++++++++
hw/pc_q35.c | 9 +++++++++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index 619a394..8b48493 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -27,6 +27,7 @@
#define FW_CFG_SETUP_SIZE 0x17
#define FW_CFG_SETUP_DATA 0x18
#define FW_CFG_FILE_DIR 0x19
+#define FW_CFG_PCI_WINDOW 0x1a
#define FW_CFG_FILE_FIRST 0x20
#define FW_CFG_FILE_SLOTS 0x10
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 1a99852..b6633e8 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -48,6 +48,7 @@
# include <xen/hvm/hvm_info_table.h>
#endif
#include "piix_pci.h"
+#include "fw_cfg.h"
#define MAX_IDE_BUS 2
@@ -86,6 +87,7 @@ static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
void *fw_cfg = NULL;
+ uint64_t *pci_window_fw_cfg;
I440FXState *i440fx_host;
PIIX3State *piix3;
@@ -141,6 +143,14 @@ static void pc_init1(MemoryRegion *system_memory,
qdev_init_nofail(DEVICE(i440fx_host));
bochs_meminfo_bios_init(fw_cfg);
+
+ pci_window_fw_cfg = g_malloc0(2 * 8);
+ pci_window_fw_cfg[0] = cpu_to_le64(i440fx_host->mch.below_4g_mem_size);
+ pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL +
+ i440fx_host->mch.above_4g_mem_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW,
+ (uint8_t *)pci_window_fw_cfg, 2 * 8);
+
i440fx_state = &i440fx_host->mch;
pci_bus = i440fx_host->parent_obj.bus;
/* Xen supports additional interrupt routes from the PCI devices to
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 7ce0b53..e35814a 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -87,6 +87,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
PCIDevice *ahci;
qemu_irq *cmos_s3;
void *fw_cfg = NULL;
+ uint64_t *pci_window_fw_cfg;
pc_cpus_init(cpu_model);
@@ -139,6 +140,14 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
/* pci */
qdev_init_nofail(DEVICE(q35_host));
bochs_meminfo_bios_init(fw_cfg);
+
+ pci_window_fw_cfg = g_malloc0(2 * 8);
+ pci_window_fw_cfg[0] = cpu_to_le64(MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+ pci_window_fw_cfg[1] = cpu_to_le64(0x100000000ULL +
+ q35_host->mch.above_4g_mem_size);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_PCI_WINDOW,
+ (uint8_t *)pci_window_fw_cfg, 2 * 8);
+
host_bus = q35_host->host.pci.bus;
/* create ISA bus */
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
--
1.7.9
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