<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><br class=""><div><br class=""><blockquote type="cite" class=""><div class="">On Jan 26, 2018, at 8:00 PM, Segher Boessenkool <<a href="mailto:segher@kernel.crashing.org" class="">segher@kernel.crashing.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">On Fri, Jan 26, 2018 at 05:04:02AM -0500, Jd Lyons wrote:<br class=""><blockquote type="cite" class=""><blockquote type="cite" class="">On Jan 25, 2018, at 1:38 PM, Segher Boessenkool <<a href="mailto:segher@kernel.crashing.org" class="">segher@kernel.crashing.org</a>> wrote:<br class=""><br class="">On Thu, Jan 25, 2018 at 11:09:31AM -0500, Jd Lyons wrote:<br class=""><blockquote type="cite" class="">Segher, if you have some of the old White Papers on the CPU’s that shipped in Mac’s, or the upgrades offered by third parties, I’d like to get a look at them, if your not under NDA.<br class=""></blockquote><br class="">You can download this CPU documentation from NPX (who bought it from<br class="">FSL, and before it was Motorola). Those are good docs.<br class=""></blockquote><br class="">Thanks, I did a few half hearted google searches, that didn’t yield the docs, I figured they we still around somewhere. Sometimes goole is obtuse, it’s like the computer from the Hitchhikers Guide, it matters how you ask the question.<br class=""></blockquote><br class="">(It probably does not help that is mistyped NXP).<br class=""><br class="">7447a filetype:pdf is an easy way to find it (you want the "reference<br class="">manual" most).<br class=""><br class=""><blockquote type="cite" class="">I wonder, in specific to emulating caches if that yields any performance increase.<br class=""></blockquote><br class="">Probably not. Your host's memory access do not get any faster, and the<br class="">increased bookkeeping will not help.<br class=""><br class=""><blockquote type="cite" class="">32 bit PPC is never going to get any faster,<br class=""></blockquote><br class="">Most (all?) 64-bit PowerPC cores can run 32-bit code just fine.<br class=""><br class=""><blockquote type="cite" class="">With qemu-ppc I find the integer performance very well maintained, it seems to scale well with the host cpu, tho the FPU and the Vec units are woeful and need a lot of work.<br class=""></blockquote><br class="">The FPU can not be cheaply emulated at all on x86 (probably not on Arm<br class="">either, not sure). The most obvious thing that cannot be cheaply emulated<br class="">is fmadd (fused multiply add).<br class=""><br class="">Some vector operations are hard to do, too (in addition to the float ones).<br class=""><br class=""><blockquote type="cite" class="">It seems like it could be a challenge to emulate caches, I’ll have to dig deeper into qemu and see how the issue is dealt with. <br class=""></blockquote><br class="">Well, it probably should at least make the L2CR etc. registers work as<br class="">expected; they do not necessarily actually have to *do* anything, esp. not<br class="">if you only want to emulate the architectural state (so don't care about<br class="">for example emulating cache invalidate correctly where that is undefined<br class="">behaviour in the architecture, etc.)<br class=""><br class=""><br class="">Segher<br class=""></div></div></blockquote></div><br class=""><div class="">Seems I’m back to this, for some reason BootX or mach_kernel is:</div><div class=""><b class=""><br class=""></b></div><div class=""><blockquote type="cite" class=""><b class="">When I try to boot OS X in qemu-system-ppc with -enable-kvm -cpu host Apple’s BootX hangs at Call Kernel!<br class=""><br class="">I’m using a PowerBook6,8 with a 7447a v1.5 and Kernel 4.4.111.<br class=""><br class="">When BootX hangs, I get this in dmesg:<br class=""><br class="">kvmppc_handle_exit_pr: emulation at 92808 failed ( 7dbafaa6 )<br class=""></b></blockquote><b class=""><br class="">7dbaffa6 is mfspr r13,1018, and SPR 1018 on the 7447A is L3CR, the<br class="">level 3 cache control register. The boot code is presumably wanting<br class="">to do something to the L3 cache configuration.<br class=""><br class=""></b><blockquote type="cite" class=""><b class="">Can anyone help explain what this error means, so I can figure out what it triggering it, and hopefully fix the issue.<br class=""></b></blockquote><b class=""><br class="">You could try adding code to kvmppc_core_emulate_mfspr_pr() and<br class="">kvmppc_core_emulate_mtspr_pr() to implement it as a dummy SPR that<br class="">ignores writes and returns zero when read. That should work unless<br class="">the BootX code does something like waiting for some bit to come back<br class="">as a 1.<br class=""><br class="">Paul.</b></div><div class=""><b class=""><br class=""></b></div><div class="">I’m not really sure, meaning I have no idea to do what Paul is suggesting, but I assume it means recompiling my kernel, as I didn’t build KVM as a module. Even then, I just don’t know how to do create a dummy SPR.</div><div class=""><br class=""></div><div class="">I was hoping I could take a shortcut, with some Openbios hacks.</div><div class=""><br class=""></div><div class="">To start with I want to create a child to the CPU, the L2 cache, and see if that is enough to get OS X to stop trying to access an L3 cache that doesn’t exist. I checked the L3CR, and it is, of course not writable.</div><div class=""><br class=""></div><div class="">So the properties of the L2 I need to add are:</div><div class=""><br class=""></div><div class="">Under the CPU:</div><div class=""><br class=""></div><div class="">l2-cache /cpus/PowerPC,G4@0/l2-cache</div><div class="">l2cr 80000000</div><div class=""><br class=""></div><div class="">I tried:</div><div class=""><br class=""></div><div class="">dev /cpus/@0</div><div class="">“ /cpus/PowerPC,G4@0/l2-cache” encode-string “ l2-cache” property</div><div class="">80000000 encode-int “ l2cr” property</div><div class=""><br class=""></div><div class="">Segher, this doesn’t seem quite right, as it does create the l2-cache property, but it’s in quotes. I think what I need to do here is create and alias rather than a string? </div><div class=""><br class=""></div><div class="">The l2cr property seems correct.</div><div class=""><br class=""></div><div class="">The I need to create a child to the CPU, but I’m not sure how to do that, Segher?</div><div class=""><br class=""></div><div class="">The child needs to have these properties:</div><div class=""><br class=""></div><div class="">name l2-cache</div><div class="">device-type cache</div><div class="">i-cache-size 00080000</div><div class="">d-cache-size 00080000</div><div class="">i-cache-sets 00000200</div><div class="">d-cache-sets 00000200</div><div class="">i-cache-line-size 00000040</div><div class="">d-cache-line-size 00000040</div><div class="">cache-unified</div><div class="">clock-frequency 59682efa</div><div class=""><br class=""></div><div class="">I’m pretty sure I know how to create these properties, I just don’t know how to create the l2-cache node as a child to the cpu@0.</div><div class=""><br class=""></div><div class=""> </div></body></html>