Begin FIDVID MSR 0xc0010071 0x52c6009e 0x42024e0c End FIDVIDMSR 0xc0010071 0x52c6009e 0x42024e0c sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode ...WARM RESET... soft_reset() called! coreboot-4.8-2309-g8f6af1cc52 Tue Nov 27 12:42:33 UTC 2018 romstage starting... CPU APICID 00 start flag set BSP Family_Model: 00600f20 *sysinfo range: [000c2e40,000cd3ac] bsp_apicid = 00 cpu_init_detectedx = 00000000 sb700 reset flags: 0004 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 85180 size 318c CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 2de40 size 1ec4 [microcode] patch id to apply = 0x06000852 [microcode] updated to patch id = 0x06000852 success cpuSetAMDMSR done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 Forcing HT links to isochronous mode due to enabled IOMMU Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 0) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 0) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1c F3xD8: 03000016 F3xDC: 05475637 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1c F3xD8: 03000016 F3xDC: 05475637 setup_remote_node: 01 done Start node 01 done. core0 started: 01 sr5650_early_setup() get_cpu_rev EAX=0x600f20. CPU Rev is Fam 15. NB Revision is A12. fam10_optimization() sr5650_por_init Enabling IOMMU sb700_early_setup() sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A15 sb700_devices_por_init: Disabling ISA DMA support sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 sb700_pmio_por_init() start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 07 pass 1 Start other core - nodeid: 00 cores: 07 get_boot_apic_id: using 2 as APIC ID for node 0, core 2 get_boot_apic_id: using 4 as APIC ID for node 0, core 4 get_boot_apic_id: using 6 as APIC ID for node 0, core 6 init node: 01 cores: 07 pass 1 Start other core - nodeid: 01 cores: 07 get_boot_apic_id: using 10 as APIC ID for node 1, core 2 get_boot_apic_id: using 12 as APIC ID for node 1, core 4 get_boot_apic_id: using 14 as APIC ID for node 1, core 6 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02started get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03started get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04started get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05started get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06started get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07started get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09started get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astarted get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstarted get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstarted get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstarted get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estarted get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstarted Begin FIDVID MSR 0xc0010071 0x52c6009e 0x42024e0c End FIDVIDMSR 0xc0010071 0x52c6009e 0x42024e0c sr5650_htinit: Node 0 Link 1, HT freq=e. sr5650_htinit: HT3 mode Node 00 DIMM voltage set to index 00 Node 01 DIMM voltage set to index 00 stopped ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01stopped get_boot_apic_id: using 2 as APIC ID for node 0, core 2 * AP 02stopped get_boot_apic_id: using 3 as APIC ID for node 0, core 3 * AP 03stopped get_boot_apic_id: using 4 as APIC ID for node 0, core 4 * AP 04stopped get_boot_apic_id: using 5 as APIC ID for node 0, core 5 * AP 05stopped get_boot_apic_id: using 6 as APIC ID for node 0, core 6 * AP 06stopped get_boot_apic_id: using 7 as APIC ID for node 0, core 7 * AP 07stopped get_boot_apic_id: using 9 as APIC ID for node 1, core 1 * AP 09stopped get_boot_apic_id: using 10 as APIC ID for node 1, core 2 * AP 0astopped get_boot_apic_id: using 11 as APIC ID for node 1, core 3 * AP 0bstopped get_boot_apic_id: using 12 as APIC ID for node 1, core 4 * AP 0cstopped get_boot_apic_id: using 13 as APIC ID for node 1, core 5 * AP 0dstopped get_boot_apic_id: using 14 as APIC ID for node 1, core 6 * AP 0estopped get_boot_apic_id: using 15 as APIC ID for node 1, core 7 * AP 0fstopped fill_mem_ctrl() detected 2 nodes raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 0 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=c DIMMPresence: DIMMPresent=c DIMMPresence: RegDIMMPresent=c DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=c DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=c DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=c DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=2 DIMMPresence: MAload[0]=20 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=2 DIMMPresence: MAload[1]=20 DIMMPresence: MAdimms[1]=1 DIMMPresence: Status 2005 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence: Done DCTPreInit_D: mct_DIMMPresence Done CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 's3nv' CBFS: Found @ offset 2fdc0 size 10000 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 's3nv' CBFS: Found @ offset 2fdc0 size 10000 mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_preInitDCT DIMMPresence: DIMMValid=0 DIMMPresence: DIMMPresent=0 DIMMPresence: RegDIMMPresent=0 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=0 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=0 DIMMPresence: MAload[0]=0 DIMMPresence: MAdimms[0]=0 DIMMPresence: DATAload[1]=0 DIMMPresence: MAload[1]=0 DIMMPresence: MAdimms[1]=0 DIMMPresence: Status 2000 DIMMPresence: ErrStatus 1 DIMMPresence: ErrCode 2 DIMMPresence: Done CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 's3nv' CBFS: Found @ offset 2fdc0 size 10000 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 's3nv' CBFS: Found @ offset 2fdc0 size 10000 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 mctAutoInitMCT_D: DIMMSetVoltage Node 00 DIMM voltage set to index 01 mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 00 enable_spd_node0() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start mct_MaxLoadFreq: 1 registered DIMM on 1350mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 5 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 3ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done SPDCalcWidth: Status 2005 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done DCTInit_D: enabling intra-channel clock skew SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffffe StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: mctSMBhub_Init activate_spd_rom() for node 01 enable_spd_node1() mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2000 SPDCalcWidth: ErrStatus 1 SPDCalcWidth: ErrCode 2 SPDCalcWidth: Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 7ffffff BottomIO: c00000 Node: 00 base: 03 limit: 83fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 activate_spd_rom() for node 01 enable_spd_node1() fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0012 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 1: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 1: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 3 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 3 DIMM 1 RttNom: 3 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 activate_spd_rom() for node 01 enable_spd_node1() fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 0054 fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d fam15_receiver_enable_training_seed: using seed: 004d TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 4000 TrainDQSReceiverEnCyc: ErrStatus 4000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done TrainMaxRdLatency: Status 2205 TrainMaxRdLatency: ErrStatus 4000 TrainMaxRdLatency: ErrCode 0 TrainMaxRdLatency: Done mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 2205 InterleaveNodes_D: ErrStatus 4000 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2205 InterleaveChannels_D: ErrStatus 4000 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 1 InterleaveChannels_D: ErrCode 2 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECC enabled on node: 00 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete............................................................................................................................................................. . DCTMemClr_Sync_D: Done ECCInit: Node 00 ECCInit: Status 2205 ECCInit: ErrStatus 4000 ECCInit: ErrCode 0 ECCInit: Done ECCInit: Node 01 ECCInit: Status 2000 ECCInit: ErrStatus 1 ECCInit: ErrCode 2 ECCInit: Done mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:8400000 mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15 mctAutoInitMCT_D Done: Global Status: 12 raminit_amdmct end: CBMEM: IMD: root @ bffff000 254 entries. IMD: root @ bfffec00 62 entries. amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM disable_spd() CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3fe00 size 15a43 coreboot-4.8-2309-g8f6af1cc52 Tue Nov 27 12:42:33 UTC 2018 ramstage starting... Moving GDT to bfffe9e0...ok Normal boot. BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0 Enumerating buses... Mainboard KGPE-D16 Enable. dev=0x00e2d260 mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000008 setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000008 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled PCI: 00:18.5 siblings=7 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: 00:19.5 siblings=7 CPU: APIC: 08 enabled CPU: APIC: 09 enabled CPU: APIC: 0a enabled CPU: APIC: 0b enabled CPU: APIC: 0c enabled CPU: APIC: 0d enabled CPU: APIC: 0e enabled CPU: APIC: 0f enabled scan_bus: scanning of bus CPU_CLUSTER: 0 took 29681 usecs PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1600] enabled PCI: 00:18.1 [1022/1601] enabled PCI: 00:18.2 [1022/1602] enabled PCI: 00:18.3 [1022/1603] enabled PCI: 00:18.4 [1022/1604] enabled PCI: 00:18.5 [1022/1605] enabled PCI: 00:19.0 [1022/1600] enabled PCI: 00:19.1 [1022/1601] enabled PCI: 00:19.2 [1022/1602] enabled PCI: 00:19.3 [1022/1603] enabled PCI: 00:19.4 [1022/1604] enabled PCI: 00:19.5 [1022/1605] enabled PCI: Static device PCI: 00:1a.0 not found, disabling it. PCI: Static device PCI: 00:1a.1 not found, disabling it. PCI: Static device PCI: 00:1a.2 not found, disabling it. PCI: Static device PCI: 00:1a.3 not found, disabling it. PCI: Static device PCI: 00:1a.4 not found, disabling it. PCI: Static device PCI: 00:1a.5 not found, disabling it. PCI: Static device PCI: 00:1b.0 not found, disabling it. PCI: Static device PCI: 00:1b.1 not found, disabling it. PCI: Static device PCI: 00:1b.2 not found, disabling it. PCI: Static device PCI: 00:1b.3 not found, disabling it. PCI: Static device PCI: 00:1b.4 not found, disabling it. PCI: Static device PCI: 00:1b.5 not found, disabling it. sr5650_enable: dev=00e2fb80, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f5e0, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] enabled PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 sr5650_enable: dev=00e2fb80, VID_DID=0x5a101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f5e0, port=0x8 PciePowerOffGppPorts() port 8 NB_PCI_REG04 = 2. NB_PCI_REG84 = 3000010. NB_PCI_REG4C = 52042. Sysmem TOM = 0_c0000000 Sysmem TOM2 = 8_40000000 PCI: 00:00.0 [1002/5a10] enabled sr5650_enable: dev=00e2fae0, VID_DID=0xffffffff Bus-0, Dev-0, Fun-1. PCI: Static device PCI: 00:00.1 not found, disabling it. sr5650_enable: dev=00e2fa40, VID_DID=0x5a231002 Bus-0, Dev-0, Fun-2. PCI: 00:00.2 [1002/5a23] enabled sr5650_enable: dev=00e2f9a0, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f9a0, port=0x2 PcieLinkTraining port=2:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=10 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=1 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [1002/5a16] enabled sr5650_enable: dev=00e2f900, VID_DID=0xffffffff Bus-0, Dev-2,3, Fun-0. enable=0 sr5650_enable: dev=00e2f860, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f860, port=0x4 PcieLinkTraining port=4:lc current state=2030400 sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0 PciePowerOffGppPorts() port 4 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1002/5a18] enabled sr5650_enable: dev=00e2f7c0, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=00e2f720, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=00e2f680, VID_DID=0xffffffff enable_pcie_bar3 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 sr5650_enable: dev=00e2f5e0, VID_DID=0xffffffff Bus-0, Dev-8, Fun-0. enable=0 disable_pcie_bar3 sr5650_enable: dev=00e2f540, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f540, port=0x9 PcieLinkTraining port=5:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=48 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1 PCI: 00:09.0 subordinate bus PCI Express PCI: 00:09.0 [1002/5a1c] enabled sr5650_enable: dev=00e2f4a0, VID_DID=0xffffffff Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f4a0, port=0xa PcieLinkTraining port=6:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=50 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1002/5a1d] enabled sr5650_enable: dev=00e2f400, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f400, port=0xb PcieLinkTraining port=b:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=58 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xb hw_port=0xb result=1 PCI: 00:0b.0 subordinate bus PCI Express PCI: 00:0b.0 [1002/5a1f] enabled sr5650_enable: dev=00e2f360, VID_DID=0xffffffff Bus-0, Dev-11,12, Fun-0. enable=1 sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f360, port=0xc PcieLinkTraining port=c:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=60 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xc hw_port=0xc result=1 PCI: 00:0c.0 subordinate bus PCI Express PCI: 00:0c.0 [1002/5a20] enabled sr5650_enable: dev=00e2f2c0, VID_DID=0xffffffff sr5650_gpp_sb_init: nb_dev=0x00e2fb80, dev=0x00e2f2c0, port=0xd PcieLinkTraining port=d:lc current state=a0b0f10 addr=c0000000,bus=0,devfn=68 PcieTrainPort reg=0x10000 sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1 PCI: 00:0d.0 subordinate bus PCI Express PCI: 00:0d.0 [1002/5a1e] enabled sb7xx_51xx_enable() PCI: 00:11.0 [1002/4390] enabled sb7xx_51xx_enable() PCI: 00:12.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:12.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:12.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:13.0 [1002/4397] enabled sb7xx_51xx_enable() PCI: 00:13.1 [1002/4398] enabled sb7xx_51xx_enable() PCI: 00:13.2 [1002/4396] enabled sb7xx_51xx_enable() PCI: 00:14.0 [1002/4385] enabled sb7xx_51xx_enable() PCI: 00:14.1 [1002/439c] enabled sb7xx_51xx_enable() PCI: 00:14.2 [1002/4383] enabled sb7xx_51xx_enable() PCI: 00:14.3 [1002/439d] enabled sb7xx_51xx_enable() PCI: 00:14.4 [1002/4384] enabled sb7xx_51xx_enable() PCI: 00:14.5 [1002/4399] enabled PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/6779] enabled PCI: 01:00.1 [1002/aa98] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s and L1 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s and L1 Failed to enable LTR for dev = PCI: 01:00.0 Failed to enable LTR for dev = PCI: 01:00.1 scan_bus: scanning of bus PCI: 00:02.0 took 27940 usecs PCI: pci_scan_bus for bus 02 scan_bus: scanning of bus PCI: 00:04.0 took 2120 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/10d3] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None Failed to enable LTR for dev = PCI: 03:00.0 scan_bus: scanning of bus PCI: 00:09.0 took 14628 usecs PCI: pci_scan_bus for bus 04 PCI: 04:00.0 [8086/10d3] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled None Failed to enable LTR for dev = PCI: 04:00.0 scan_bus: scanning of bus PCI: 00:0a.0 took 14628 usecs PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [1002/6779] enabled PCI: 05:00.1 [1002/aa98] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s and L1 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s and L1 Failed to enable LTR for dev = PCI: 05:00.0 Failed to enable LTR for dev = PCI: 05:00.1 scan_bus: scanning of bus PCI: 00:0b.0 took 27941 usecs PCI: pci_scan_bus for bus 06 PCI: 06:00.0 [1912/0014] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 scan_bus: scanning of bus PCI: 00:0c.0 took 9066 usecs PCI: pci_scan_bus for bus 07 PCI: 07:00.0 [8086/2700] enabled Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L0s Failed to enable LTR for dev = PCI: 07:00.0 scan_bus: scanning of bus PCI: 00:0d.0 took 16134 usecs bus: PCI: 00:14.0[0]->I2C: 01:50 enabled bus: PCI: 00:14.0[0]->I2C: 01:51 enabled bus: PCI: 00:14.0[0]->I2C: 01:52 enabled bus: PCI: 00:14.0[0]->I2C: 01:53 enabled bus: PCI: 00:14.0[0]->I2C: 01:54 enabled bus: PCI: 00:14.0[0]->I2C: 01:55 enabled bus: PCI: 00:14.0[0]->I2C: 01:56 enabled bus: PCI: 00:14.0[0]->I2C: 01:57 enabled bus: PCI: 00:14.0[0]->I2C: 01:2f enabled scan_bus: scanning of bus PCI: 00:14.0 took 26458 usecs PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.106 disabled PNP: 002e.107 disabled PNP: 002e.207 disabled PNP: 002e.307 disabled PNP: 002e.407 disabled PNP: 002e.8 disabled PNP: 002e.108 disabled PNP: 002e.9 disabled PNP: 002e.109 disabled PNP: 002e.209 disabled PNP: 002e.309 disabled PNP: 002e.a enabled PNP: 002e.b enabled PNP: 002e.c disabled PNP: 002e.d disabled PNP: 002e.f disabled PNP: 004e.0 enabled scan_bus: scanning of bus PCI: 00:14.3 took 34937 usecs PCI: pci_scan_bus for bus 08 sb7xx_51xx_enable() PCI: Static device PCI: 08:01.0 not found, disabling it. sb7xx_51xx_enable() PCI: 08:02.0 [11c1/5811] enabled sb7xx_51xx_enable() PCI: Static device PCI: 08:03.0 not found, disabling it. scan_bus: scanning of bus PCI: 00:14.4 took 16991 usecs scan_bus: scanning of bus PCI: 00:18.0 took 1601244 usecs scan_bus: scanning of bus PCI: 00:19.0 took 1 usecs scan_bus: scanning of bus DOMAIN: 0000 took 1688136 usecs scan_bus: scanning of bus Root Device took 1738905 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 1757883 exit 0 found VGA at PCI: 01:00.0 found VGA at PCI: 05:00.0 Setting up VGA for PCI: 05:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0b.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000. sr5690_read_resource: PCI: 00:00.0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources I2C: 01:54 missing read_resources I2C: 01:55 missing read_resources I2C: 01:56 missing read_resources I2C: 01:57 missing read_resources Done reading resources. Setting resources... 0: mmio_basek=00300000, basek=00400000, limitk=02100000 VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 110b0 <- [0x00d0000000 - 0x00f00fffff] size 0x20100000 gran 0x14 prefmem PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00f87fffff] size 0x00800000 gran 0x14 mem PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io PCI: 00:00.0 sr5690_set_resources sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90 PCI: 00:00.0 fc <- [0x00f0000000 - 0x00f00000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:00.2 44 <- [0x00f8700000 - 0x00f8703fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 01:00.0 18 <- [0x00f8000000 - 0x00f801ffff] size 0x00020000 gran 0x11 mem64 PCI: 01:00.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 30 <- [0x00f8020000 - 0x00f803ffff] size 0x00020000 gran 0x11 romem PCI: 01:00.1 10 <- [0x00f8040000 - 0x00f8043fff] size 0x00004000 gran 0x0e mem64 PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00f87fffff - 0x00f87ffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00f8100000 - 0x00f81fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00f8100000 - 0x00f811ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00f8120000 - 0x00f8123fff] size 0x00004000 gran 0x0e mem PCI: 00:0a.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00f8200000 - 0x00f82fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 04:00.0 10 <- [0x00f8200000 - 0x00f821ffff] size 0x00020000 gran 0x11 mem PCI: 04:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 04:00.0 1c <- [0x00f8220000 - 0x00f8223fff] size 0x00004000 gran 0x0e mem PCI: 00:0b.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00f8300000 - 0x00f83fffff] size 0x00100000 gran 0x14 bus 05 mem PCI: 05:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 05:00.0 18 <- [0x00f8300000 - 0x00f831ffff] size 0x00020000 gran 0x11 mem64 PCI: 05:00.0 20 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io PCI: 05:00.0 30 <- [0x00f8320000 - 0x00f833ffff] size 0x00020000 gran 0x11 romem PCI: 05:00.1 10 <- [0x00f8340000 - 0x00f8343fff] size 0x00004000 gran 0x0e mem64 PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00f8400000 - 0x00f84fffff] size 0x00100000 gran 0x14 bus 06 mem PCI: 06:00.0 10 <- [0x00f8400000 - 0x00f8401fff] size 0x00002000 gran 0x0d mem64 PCI: 00:0d.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00f8500000 - 0x00f85fffff] size 0x00100000 gran 0x14 bus 07 mem PCI: 07:00.0 10 <- [0x00f8510000 - 0x00f8513fff] size 0x00004000 gran 0x0e mem64 PCI: 07:00.0 30 <- [0x00f8500000 - 0x00f850ffff] size 0x00010000 gran 0x10 romem PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00f870d000 - 0x00f870d3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00f8708000 - 0x00f8708fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00f8709000 - 0x00f8709fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00f870e000 - 0x00f870e0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00f870a000 - 0x00f870afff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00f870b000 - 0x00f870bfff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00f870f000 - 0x00f870f0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00f8704000 - 0x00f8707fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00f8710000 - 0x00f8710000] size 0x00000001 gran 0x00 mem PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:14.4 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 08 io PCI: 00:14.4 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:14.4 20 <- [0x00f8600000 - 0x00f86fffff] size 0x00100000 gran 0x14 bus 08 mem PCI: 08:02.0 10 <- [0x00f8600000 - 0x00f8600fff] size 0x00001000 gran 0x0c mem PCI: 00:14.5 10 <- [0x00f870c000 - 0x00f870cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 561065 exit 0 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8163 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8163 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 1043/8163 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 1043/8163 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 PCI: 00:19.5 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/8163 PCI: 00:00.0 cmd <- 02 Initializing IOMMU PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 07 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 07 PCI: 00:0b.0 bridge ctrl <- 000b PCI: 00:0b.0 cmd <- 07 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 06 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 06 PCI: 00:11.0 subsystem <- 1043/8163 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1043/8163 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1043/8163 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1043/8163 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1043/8163 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1043/8163 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1043/8163 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1043/8163 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1043/8163 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1043/8163 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1043/8163 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291 PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 00:14.5 subsystem <- 1043/8163 PCI: 00:14.5 cmd <- 02 PCI: 01:00.0 cmd <- 03 PCI: 01:00.1 cmd <- 02 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 cmd <- 03 PCI: 05:00.0 cmd <- 03 PCI: 05:00.1 cmd <- 02 PCI: 06:00.0 cmd <- 02 PCI: 07:00.0 cmd <- 02 PCI: 08:02.0 subsystem <- 1043/8163 PCI: 08:02.0 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 161583 exit 0 Initializing devices... Root Device init ... Root Device init finished in 1538 usecs CPU_CLUSTER: 0 init ... Enabling probe filter Enabling ATM mode start_eip=0x00001000, code_size=0x00000031 Initializing CPU #1 Initializing CPU #2 CPU: vendor AMD device 600f20 Initializing CPU #7 CPU: family 15, model 02, stepping 00 Initializing CPU #5 nodeid = 00, coreid = 01 Initializing CPU #0 Enabling cache CPU: vendor AMD device 600f20 CPU: family 15, model 02, stepping 00 CPU: vendor AMD device 600f20 nodeid = 00, coreid = 00 Initializing CPU #4 Enabling cache Initializing CPU #12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Initializing CPU #8 MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 1 0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0 0x0000000100000000 - 0x0000000840000000 size 0x740000000 type 6 Initializing CPU #11 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Initializing CPU #9 MTRR: default type WB/UC MTRR counts: 4/4. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000d0000000 mask 0x0000fffff0000000 type 1 MTRR: 3 base 0x00000000e0000000 mask 0x0000fffff0000000 type 1 Initializing CPU #10 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU: vendor AMD device 600f20 Setting up local APIC...Initializing CPU #6 apic_id: 0x00 done. CPU: vendor AMD device 600f20 CPU model: AMD Opteron(tm) Processor 6386 SE Initializing CPU #14 siblings = 15, CPU: family 15, model 02, stepping 00 Disabling SMM ASeg memory Initializing CPU #3 MTRR check CPU #0 initialized Fixed MTRRs : Enabled Variable MTRRs: Waiting for 15 CPUS to stop Enabled Initializing CPU #15 Setting up local APIC...CPU: vendor AMD device 600f20 apic_id: 0x01 done. nodeid = 01, coreid = 00 CPU model: AMD Opteron(tm) Processor 6386 SE CPU: vendor AMD device 600f20 siblings = 15, CPU: vendor AMD device 600f20 Disabling SMM ASeg memory Enabling cache CPU #1 initialized CPU: family 15, model 02, stepping 00 Waiting for 14 CPUS to stop CPU: vendor AMD device 600f20 CPU: family 15, model 02, stepping 00 CPU: vendor AMD device 600f20 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB CPU: family 15, model 02, stepping 00 CPU: family 15, model 02, stepping 00 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e CPU: vendor AMD device 600f20 CPU: vendor AMD device 600f20 CPU: family 15, model 02, stepping 00 nodeid = 01, coreid = 01 MTRR check nodeid = 00, coreid = 07 Enabling cache CPU: vendor AMD device 600f20 Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU: family 15, model 02, stepping 00 Setting up local APIC...nodeid = 01, coreid = 02 apic_id: 0x08 done. CPU: vendor AMD device 600f20 CPU model: AMD Opteron(tm) Processor 6386 SE CPU: family 15, model 02, stepping 00 siblings = 15, nodeid = 01, coreid = 07 Disabling SMM ASeg memory MTRR check CPU #8 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for 13 CPUS to stop Setting up local APIC...nodeid = 00, coreid = 05 apic_id: 0x09 done. Enabling cache CPU model: AMD Opteron(tm) Processor 6386 SE CPU: family 15, model 02, stepping 00 siblings = 15, nodeid = 01, coreid = 06 Disabling SMM ASeg memory Enabling cache CPU #9 initialized CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Waiting for 12 CPUS to stop MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e CPU: family 15, model 02, stepping 00 Enabling cache nodeid = 00, coreid = 06 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled nodeid = 01, coreid = 04 Setting up local APIC...CPU: vendor AMD device 600f20 apic_id: 0x0e done. Enabling cache CPU model: AMD Opteron(tm) Processor 6386 SE CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB siblings = 15, Enabling cache MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Disabling SMM ASeg memory Enabling cache CPU #14 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU: family 15, model 02, stepping 00 Waiting for 11 CPUS to stop Setting up local APIC... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled apic_id: 0x06 done. Setting up local APIC...CPU model: AMD Opteron(tm) Processor 6386 SE apic_id: 0x0f done. siblings = 15, CPU model: AMD Opteron(tm) Processor 6386 SE Disabling SMM ASeg memory nodeid = 00, coreid = 03 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled siblings = 15, Enabling cache Setting up local APIC...Disabling SMM ASeg memory CPU #6 initialized apic_id: 0x07 done. CPU #15 initialized CPU model: AMD Opteron(tm) Processor 6386 SE Waiting for 10 CPUS to stop siblings = 15, Waiting for 9 CPUS to stop Disabling SMM ASeg memory Initializing CPU #13 CPU #7 initialized CPU: family 15, model 02, stepping 00 Waiting for 8 CPUS to stop nodeid = 01, coreid = 03 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB nodeid = 00, coreid = 02 CPU: family 15, model 02, stepping 00 Enabling cache nodeid = 00, coreid = 04 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB Enabling cache MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC...Setting up local APIC... apic_id: 0x0a done. apic_id: 0x02 done. CPU model: AMD Opteron(tm) Processor 6386 SE CPU model: AMD Opteron(tm) Processor 6386 SE siblings = 15, siblings = 15, Disabling SMM ASeg memory Disabling SMM ASeg memory CPU #10 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for 7 CPUS to stop Setting up local APIC...CPU #2 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for 6 CPUS to stop Setting up local APIC... apic_id: 0x0b done. apic_id: 0x03 done. CPU model: AMD Opteron(tm) Processor 6386 SE CPU model: AMD Opteron(tm) Processor 6386 SE siblings = 15, siblings = 15, Disabling SMM ASeg memory Disabling SMM ASeg memory CPU #11 initialized CPU #3 initialized Waiting for 5 CPUS to stop Enabling cache Waiting for 4 CPUS to stop Enabling cache CPU: vendor AMD device 600f20 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB CPU: family 15, model 02, stepping 00 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR check MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e Fixed MTRRs : Enabled Variable MTRRs: Enabled nodeid = 01, coreid = 05 MTRR check Fixed MTRRs : Setting up local APIC...Enabled Variable MTRRs: apic_id: 0x0c done. Enabled CPU model: AMD Opteron(tm) Processor 6386 SE Setting up local APIC...siblings = 15, apic_id: 0x04 done. Disabling SMM ASeg memory CPU model: AMD Opteron(tm) Processor 6386 SE Enabling cache siblings = 15, MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling SMM ASeg memory Setting up local APIC...CPU #12 initialized apic_id: 0x0d done. MTRR check CPU model: AMD Opteron(tm) Processor 6386 SE Fixed MTRRs : siblings = 15, Waiting for 3 CPUS to stop Disabling SMM ASeg memory CPU #4 initialized CPU #13 initialized Enabled Waiting for 2 CPUS to stop Variable MTRRs: Enabled Waiting for 1 CPUS to stop Setting up local APIC... apic_id: 0x05 done. CPU model: AMD Opteron(tm) Processor 6386 SE siblings = 15, Disabling SMM ASeg memory CPU #5 initialized All AP CPUs stopped (66777 loops) CPU_CLUSTER: 0 init finished in 795742 usecs PCI: 00:18.0 init ... PCI: 00:18.0 init finished in 1604 usecs PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 1607 usecs PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 1607 usecs PCI: 00:18.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:18.3 init finished in 4200 usecs PCI: 00:18.4 init ... NB: Function 4 Link Control.. done. PCI: 00:18.4 init finished in 4201 usecs PCI: 00:18.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:18.5 init finished in 4686 usecs PCI: 00:19.0 init ... PCI: 00:19.0 init finished in 1608 usecs PCI: 00:19.1 init ... PCI: 00:19.1 init finished in 1607 usecs PCI: 00:19.2 init ... PCI: 00:19.2 init finished in 1606 usecs PCI: 00:19.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:19.3 init finished in 4200 usecs PCI: 00:19.4 init ... NB: Function 4 Link Control.. done. PCI: 00:19.4 init finished in 4200 usecs PCI: 00:19.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:19.5 init finished in 4685 usecs PCI: 00:00.0 init ... pcie_init in sr5650_ht.c IOAPIC: Initializing IOAPIC at 0xf0000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB PCI: 00:00.0 init finished in 15137 usecs PCI: 00:11.0 init ... No Primary Master SATA drive on Slot0 No Primary Slave SATA drive on Slot1 No Secondary Master SATA drive on Slot2 No Secondary Slave SATA drive on Slot3 PCI: 00:11.0 init finished in 19068 usecs PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 1631 usecs PCI: 00:12.1 init ... PCI: 00:12.1 init finished in 1631 usecs PCI: 00:12.2 init ... usb2_bar0=0xf870e000 rpr 6.23, final dword=809e03c8 PCI: 00:12.2 init finished in 5386 usecs PCI: 00:13.0 init ... PCI: 00:13.0 init finished in 1631 usecs PCI: 00:13.1 init ... PCI: 00:13.1 init finished in 1631 usecs PCI: 00:13.2 init ... usb2_bar0=0xf870f000 rpr 6.23, final dword=809e03c8 PCI: 00:13.2 init finished in 5393 usecs PCI: 00:14.0 init ... sm_init(). IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB set power "on" after power fail ++++++++++no set NMI+++++ RTC Init sm_init() end PCI: 00:14.0 init finished in 19028 usecs PCI: 00:14.1 init ... PCI: 00:14.1 init finished in 1610 usecs PCI: 00:14.2 init ... base = 0xf8704000 No codec! PCI: 00:14.2 init finished in 6925 usecs PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 1631 usecs PCI: 00:14.4 init ... PCI: 00:14.4 init finished in 1626 usecs PCI: 00:14.5 init ... PCI: 00:14.5 init finished in 1631 usecs PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 1607 usecs PCI: 01:00.1 init ... PCI: 01:00.1 init finished in 1608 usecs PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 1607 usecs PCI: 04:00.0 init ... PCI: 04:00.0 init finished in 1608 usecs PCI: 05:00.0 init ... PCI: 05:00.0 init finished in 1607 usecs PCI: 05:00.1 init ... PCI: 05:00.1 init finished in 1607 usecs PCI: 06:00.0 init ... PCI: 06:00.0 init finished in 1608 usecs PCI: 07:00.0 init ... PCI: 07:00.0 init finished in 1607 usecs smbus: PCI: 00:14.0[0]->I2C: 01:2f init ... Set SMBUS controller to channel 1 Found 64 pin W83795G Nuvoton H/W Monitor W83795G/ADG work in Thermal Cruise Mode Fan CTFS(celsius) TTTI(celsius) 1 80 80 2 80 80 3 80 80 4 80 80 5 80 80 6 80 80 DTS1 current value: 12 DTS2 current value: 0 DTS3 current value: 0 DTS4 current value: 0 DTS5 current value: 0 DTS6 current value: 0 DTS7 current value: 0 DTS8 current value: 0 Set SMBUS controller to channel 0 I2C: 01:2f init finished in 312029 usecs PNP: 002e.2 init ... PNP: 002e.2 init finished in 1537 usecs PNP: 002e.3 init ... PNP: 002e.3 init finished in 1538 usecs PNP: 002e.5 init ... w83667hg_a_init: Disable mouse controller.PNP: 002e.5 init finished in 4480 usecs PNP: 002e.a init ... set power on after power fail PNP: 002e.a init finished in 3703 usecs PNP: 002e.b init ... PNP: 002e.b init finished in 1538 usecs PCI: 08:02.0 init ... PCI: 08:02.0 init finished in 1609 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 0 run 1385489 exit 0 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 2801 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0xbfdbe000...done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f076c Wrote the mp table end at: bfdbd010 - bfdbd36c MP table: 876 bytes. CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 2af00 size 26a7 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at bfd99000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT pm_base: 0x0800 ACPI: added table 1/32, length now 40 ACPI: * SSDT processor_brand=AMD Opteron(tm) Processor 6386 SE Pstates algorithm ... Pstate_freq[0] = 2800MHz Pstate_power[0] = 7437mw Pstate_latency[0] = 5us Pstate_freq[1] = 2500MHz Pstate_power[1] = 6457mw Pstate_latency[1] = 5us Pstate_freq[2] = 2200MHz Pstate_power[2] = 5530mw Pstate_latency[2] = 5us Pstate_freq[3] = 1800MHz Pstate_power[3] = 4255mw Pstate_latency[3] = 5us Pstate_freq[4] = 1400MHz Pstate_power[4] = 3191mw Pstate_latency[4] = 5us PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 PSS: 2800MHz power 7437 control 0x0 status 0x0 PSS: 2500MHz power 6457 control 0x1 status 0x1 PSS: 2200MHz power 5530 control 0x2 status 0x2 PSS: 1800MHz power 4255 control 0x3 status 0x3 PSS: 1400MHz power 3191 control 0x4 status 0x4 \_SB.PCI0.LPC.TPM: LPC TPM PNP: 004e.0 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'pci1002,6779.rom' CBFS: 'pci1002,6779.rom' not found. PCI Option ROM loading disabled for PCI: 01:00.0 PCI: 01:00.0: Missing PCI Option ROM CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'pci1002,6779.rom' CBFS: 'pci1002,6779.rom' not found. PCI Option ROM loading disabled for PCI: 05:00.0 PCI: 05:00.0: Missing PCI Option ROM ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * MADT ACPI: added table 4/32, length now 52 current = bfd9d630 ACPI: * SRAT at bfd9d630 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=01d00000 ACPI: added table 5/32, length now 56 ACPI: * SLIT at bfd9d7d8 ACPI: added table 6/32, length now 60 ACPI: * SRAT at bfd9d810 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=01d00000 ACPI: added table 7/32, length now 64 ACPI: * SLIT at bfd9d9b8 ACPI: added table 8/32, length now 68 ACPI: * IVRS at bfd9d9f0 ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'pci1002,6779.rom' CBFS: 'pci1002,6779.rom' not found. PCI Option ROM loading disabled for PCI: 01:00.0 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'pci1002,6779.rom' CBFS: 'pci1002,6779.rom' not found. PCI Option ROM loading disabled for PCI: 05:00.0 ACPI: done. ACPI tables: 19184 bytes. smbios_write_tables: bfd98000 DOMAIN: 0000 (AMD Family 10h/15h Root Complex) SMBIOS tables: 543 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5002 Writing coreboot table at 0xbfdbf000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-0000000000dfffff: RAM 2. 0000000000e00000-0000000000f17fff: RAMSTAGE 3. 0000000000f18000-00000000bfd97fff: RAM 4. 00000000bfd98000-00000000bfffffff: CONFIGURATION TABLES 5. 00000000c0000000-00000000cfffffff: RESERVED 6. 00000000f8700000-00000000f8703fff: RESERVED 7. 00000000feb00000-00000000feb00fff: RESERVED 8. 00000000fec00000-00000000fec00fff: RESERVED 9. 00000000fed00000-00000000fed00fff: RESERVED 10. 00000000fed40000-00000000fed44fff: RESERVED 11. 0000000100000000-000000083fffffff: RAM Manufacturer: c2 SF: Detected MX25L1605D with sector size 0x1000, total 0x200000 CBFS: 'Master Header Locator' located CBFS at [200:200000) FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ffe00000 size = 200000 #areas = 3 Wrote coreboot table at: bfdbf000, 0x32c bytes, checksum afe7 coreboot table: 836 bytes. IMD ROOT 0. bffff000 00001000 IMD SMALL 1. bfffe000 00001000 CAR GLOBALS 2. bfff3000 0000a7c0 CONSOLE 3. bffd3000 00020000 TIME STAMP 4. bffd2000 00000910 AMDMEM INFO 5. bffc8000 000093fc ACPI RESUME 6. bfdc7000 00201000 COREBOOT 7. bfdbf000 00008000 IRQ TABLE 8. bfdbe000 00001000 SMP TABLE 9. bfdbd000 00001000 ACPI 10. bfd99000 00024000 SMBIOS 11. bfd98000 00000800 IMD small region: IMD ROOT 0. bfffec00 00000400 ROMSTAGE 1. bfffebe0 00000004 GDT 2. bfffe9e0 00000200 COREBOOTFWD 3. bfffe9a0 00000028 Writing AMD DCT configuration to Flash CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 's3nv' CBFS: Found @ offset 2fdc0 size 10000 Manufacturer: c2 SF: Detected MX25L1605D with sector size 0x1000, total 0x200000 SF: Successfully erased 32768 bytes @ 0x38000 BS: BS_WRITE_TABLES times (us): entry 0 run 1651241 exit 0 CBFS: 'Master Header Locator' located CBFS at [200:200000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 68d00 size 10a17 Checking segment from ROM address 0xffe68f38 Checking segment from ROM address 0xffe68f54 Loading segment from ROM address 0xffe68f38 code (compression=1) New segment dstaddr 0x000e0700 memsize 0x1f900 srcaddr 0xffe68f70 filesize 0x109df Loading Segment: addr: 0x000e0700 memsz: 0x000000000001f900 filesz: 0x00000000000109df using LZMA Loading segment from ROM address 0xffe68f54 Entry Point 0x000fd258 BS: BS_PAYLOAD_LOAD times (us): entry 0 run 69819 exit 0 Jumping to boot code at 000fd258(bfdbf000) SeaBIOS (version rel-1.12.0-0-ga698c89) BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 SeaBIOS (version rel-1.12.0-0-ga698c89) BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 Found coreboot cbmem console @ bffd3000 Found mainboard ASUS KGPE-D16 Relocating init from 0x000e1d60 to 0xbfd4b560 (size 51712) Found CBFS header at 0xffe00238 multiboot: eax=e31240, ebx=e311f4 Found 43 PCI devices (max PCI bus is 08) Copying SMBIOS entry point from 0xbfd98000 to 0x000f6280 Copying ACPI RSDP from 0xbfd99000 to 0x000f6250 Skipping MPTABLE copy due to large size (876 bytes) Copying PIR from 0xbfdbe000 to 0x000f6220 Using pmtimer, ioport 0x820 WARNING - Timeout at wait_reg8:81! Scan for VGA option rom Running option rom at c000:0003 Running option rom at d000:0003 Start SeaVGABIOS (version rel-1.12.0-0-ga698c89) VGABUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30 enter vga_post: a=00000000 b=0000ffff c=00000000 d=0000ffff ds=0000 es=f000 ss=0000 si=00000000 di=000066a0 bp=00000000 sp=00006dda cs=f000 ip=d031 f=0000 coreboot vga init Did not find coreboot framebuffer - assuming EGA text Attempting to allocate 512 bytes lowmem via pmm call to f000:d0ac pmm call arg1=0 VGA stack allocated at edca0 Hooking hardware timer irq (old=f000fea5 new=d0003e44) Turning on vga text mode console set VGA mode 3 SeaBIOS (version rel-1.12.0-0-ga698c89) XHCI init on dev 06:00.0: regs @ 0xf8400000, 8 ports, 32 slots, 64 byte contexts XHCI extcap 0x1 @ 0xf8400500 XHCI protocol USB 3.00, 4 ports (offset 1), def 0 XHCI protocol USB 2.00, 4 ports (offset 5), def 0 XHCI extcap 0xc0 @ 0xf8400540 XHCI extcap 0xa @ 0xf8400550 EHCI init on dev 00:12.2 (regs=0xf870e020) EHCI init on dev 00:13.2 (regs=0xf870f020) OHCI init on dev 00:12.0 (regs=0xf8708000) OHCI init on dev 00:12.1 (regs=0xf8709000) OHCI init on dev 00:13.0 (regs=0xf870a000) OHCI init on dev 00:13.1 (regs=0xf870b000) OHCI init on dev 00:14.5 (regs=0xf870c000) ATA controller 1 at 5020/5040/0 (irq 0 dev 88) ATA controller 2 at 5028/5044/0 (irq 0 dev 88) ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1) ATA controller 4 at 170/374/0 (irq 15 dev a1) Got ps2 nak (status=51) Found 0 lpt ports Found 2 serial ports Searching bootorder for: /rom@img/memtest Searching bootorder for: /rom@img/coreinfo Searching bootorder for: /pci@i0cf8/pci-bridge@d/*@0 XHCI no devices found USB keyboard initialized Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f6160: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=547002288 Space available for UMB: d7000-ed800, f5aa0-f6160 Returned 200704 bytes of ZoneHigh e820 map has 11 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 00000000bfd89000 = 1 RAM 4: 00000000bfd89000 - 00000000d0000000 = 2 RESERVED 5: 00000000f8700000 - 00000000f8704000 = 2 RESERVED 6: 00000000feb00000 - 00000000feb01000 = 2 RESERVED 7: 00000000fec00000 - 00000000fec01000 = 2 RESERVED 8: 00000000fed00000 - 00000000fed01000 = 2 RESERVED 9: 00000000fed40000 - 00000000fed45000 = 2 RESERVED 10: 0000000100000000 - 0000000840000000 = 1 RAM enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00 VBE current mode=3 stub vbe_104fXX:406: a=00004f15 b=00000000 c=00000000 d=00000000 ds=0000 es=0000 ss=edca si=00000000 di=00000000 bp=00001ff0 sp=000001f6 cs=0000 ip=9104 f=0202 stub vbe_104fXX:406: a=00004f11 b=00000001 c=bfd1b220 d=00000004 ds=bfd1 es=6000 ss=edca si=0007fbcc di=00008080 bp=00001ff0 sp=000001f6 cs=0000 ip=9104 f=0202 set VGA mode 12 set VGA mode 3 VBE current mode=3 stub vbe_104f0a:379: a=00004f0a b=00000000 c=0000004f d=00000003 ds=0000 es=0200 ss=edca si=00070202 di=bfd20b82 bp=00001ff0 sp=000001f6 cs=0000 ip=9104 f=0202 set VGA mode 3 stub vbe_104fXX:406: a=4a034f15 b=00000000 c=00000000 d=002f0081 ds=8f00 es=0000 ss=edca si=00000dd2 di=00000000 bp=00000000 sp=000001f6 cs=8f00 ip=15dc f=0246