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<DIV>Ok, there is no spd on the board. Four memory chips are soldered on the
board (Micron DDR3L 4х512MB 1333Mhz). I understand that I need to set the
correct memory parameters in the fsp configurator. Even if it works, replacing
the memory chips may lead to a stop working of the coreboot.rom. It is necessary
to change the parameters of the fsp again and rebuild coreboot.rom. </DIV>
<DIV>How does the proprietary BIOS (TianoCore) work in case of replacing the
memory chips on board? </DIV>
<DIV>Are there universal parameters for this memory types and what should I take
note for when configuring FSP?</DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>
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<DIV> </DIV>
<DIV style="BACKGROUND: #f5f5f5">
<DIV style="font-color: black"><B>From:</B> <A title=rene.shuster@bcsemail.org
href="mailto:rene.shuster@bcsemail.org">R S</A> </DIV>
<DIV><B>Sent:</B> Tuesday, November 06, 2018 8:30 PM</DIV>
<DIV><B>To:</B> <A title=alexfeinman@hotmail.com
href="mailto:alexfeinman@hotmail.com">alexfeinman@hotmail.com</A> </DIV>
<DIV><B>Cc:</B> <A title=coreboot@coreboot.org
href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</A> ; <A
title=alexey_bau@mail.ru href="mailto:alexey_bau@mail.ru">alexey_bau@mail.ru</A>
</DIV>
<DIV><B>Subject:</B> Re: [coreboot] How to get correct memory params for
FSP</DIV></DIV></DIV>
<DIV> </DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>
<DIV dir=ltr>Faint memories... are you the ISO recorder author from 15 years
ago?<BR></DIV>
<DIV> </DIV>
<DIV class=gmail_quote>
<DIV dir=ltr>On Tue, Nov 6, 2018 at 12:23 PM Alex Feinman <<A
href="mailto:alexfeinman@hotmail.com">alexfeinman@hotmail.com</A>>
wrote:<BR></DIV>
<BLOCKQUOTE class=gmail_quote
style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid">
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<DIV
style="FONT-SIZE: 12pt; FONT-FAMILY: calibri,helvetica,sans-serif; COLOR: rgb(0,0,0)">The
two major issues with bringing up the memory subsystem on a new board are SPD
parameters and DQ/DQS layout</DIV>
<DIV
style="FONT-SIZE: 12pt; FONT-FAMILY: calibri,helvetica,sans-serif; COLOR: rgb(0,0,0)">Specifically,
if you look at the apollolake rvp subtree, you can see a whole bunch of
parameters being set in romstage.c. Some of it is fairly straightforward.
Swizzling tables are not and require you to be able to read schematic (and
have access to it in the first place)</DIV>
<DIV
style="FONT-SIZE: 12pt; FONT-FAMILY: calibri,helvetica,sans-serif; COLOR: rgb(0,0,0)">Obviously,
the problem could be elsewhere. I would start with enabling MRC debug and
perhaps posting the MRC output</DIV>
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style="FONT-SIZE: 12pt; FONT-FAMILY: calibri,helvetica,sans-serif; COLOR: rgb(0,0,0)">
</DIV>
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style="FONT-SIZE: 12pt; FONT-FAMILY: calibri,helvetica,sans-serif; COLOR: rgb(0,0,0)"></DIV>
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<DIV id=m_5162750830031364199divRplyFwdMsg dir=ltr><FONT
style="FONT-SIZE: 11pt" color=#000000 face="Calibri, sans-serif"><B>From:</B>
coreboot <<A href="mailto:coreboot-bounces@coreboot.org"
target=_blank>coreboot-bounces@coreboot.org</A>> on behalf of Alexey
Borovikov via coreboot <<A href="mailto:coreboot@coreboot.org"
target=_blank>coreboot@coreboot.org</A>><BR><B>Sent:</B> Saturday, November
3, 2018 5:38 AM<BR><B>To:</B> <A href="mailto:coreboot@coreboot.org"
target=_blank>coreboot@coreboot.org</A><BR><B>Subject:</B> [coreboot] How to
get correct memory params for FSP</FONT>
<DIV> </DIV></DIV>
<DIV dir=ltr>
<DIV dir=ltr>
<DIV style="FONT-SIZE: 12pt; FONT-FAMILY: 'Calibri'; COLOR: #000000">
<DIV>
<DIV
style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>Hi.
</DIV></DIV>
<DIV>
<DIV
style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>I
port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for the
Baytrail family. The result - postcode is 0x2A. From the descriptions on the
Internet, I understand that the problem is in the incorrect memory
parameters.</DIV>
<DIV dir=ltr>
<DIV style="FONT-SIZE: 12pt; FONT-FAMILY: 'Calibri'; COLOR: #000000">
<DIV>Question: are there any utilities or methods that will help to get the
correct memory parameters when working a regular BIOS from Linux or Windows
systems?</DIV>
<DIV>Many thanks!</DIV></DIV></DIV></DIV></DIV></DIV></DIV></DIV>--
<BR>coreboot mailing list: <A href="mailto:coreboot@coreboot.org"
target=_blank>coreboot@coreboot.org</A><BR><A
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target=_blank>https://mail.coreboot.org/mailman/listinfo/coreboot</A><BR></BLOCKQUOTE></DIV><BR
clear=all><BR>-- <BR>
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<DIV>
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