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This tells us nothing about swizzling - the order in which DQ/DQS lines of the memory address bus are connected to the CPU. Memory connections to the CPU are flexible to simplify PCB routing. As a result in order for the memory controller to be able to use
memory you need to provide board-specific mapping. You cannot glean this from looking at the PCB - you need the schematic. And no, off the shelf Tianocore will not automatically do this either - it's a customizable part of the build</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Alexey Borovikov <alexey_bau@mail.ru><br>
<b>Sent:</b> Tuesday, November 6, 2018 11:06 AM<br>
<b>To:</b> R S; alexfeinman@hotmail.com<br>
<b>Cc:</b> coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] How to get correct memory params for FSP</font>
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<div>Ok, there is no spd on the board. Four memory chips are soldered on the board (Micron DDR3L 4È512MB 1333Mhz). I understand that I need to set the correct memory parameters in the fsp configurator. Even if it works, replacing the memory chips may lead to
a stop working of the coreboot.rom. It is necessary to change the parameters of the fsp again and rebuild coreboot.rom.
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<div>How does the proprietary BIOS (TianoCore) work in case of replacing the memory chips on board?
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<div>Are there universal parameters for this memory types and what should I take note for when configuring FSP?</div>
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<div style=""><b>From:</b> <a title="rene.shuster@bcsemail.org" href="mailto:rene.shuster@bcsemail.org">
R S</a> </div>
<div><b>Sent:</b> Tuesday, November 06, 2018 8:30 PM</div>
<div><b>To:</b> <a title="alexfeinman@hotmail.com" href="mailto:alexfeinman@hotmail.com">
alexfeinman@hotmail.com</a> </div>
<div><b>Cc:</b> <a title="coreboot@coreboot.org" href="mailto:coreboot@coreboot.org">
coreboot@coreboot.org</a> ; <a title="alexey_bau@mail.ru" href="mailto:alexey_bau@mail.ru">
alexey_bau@mail.ru</a> </div>
<div><b>Subject:</b> Re: [coreboot] How to get correct memory params for FSP</div>
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<div dir="ltr">Faint memories... are you the ISO recorder author from 15 years ago?<br>
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<div dir="ltr">On Tue, Nov 6, 2018 at 12:23 PM Alex Feinman <<a href="mailto:alexfeinman@hotmail.com">alexfeinman@hotmail.com</a>> wrote:<br>
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The two major issues with bringing up the memory subsystem on a new board are SPD parameters and DQ/DQS layout</div>
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Specifically, if you look at the apollolake rvp subtree, you can see a whole bunch of parameters being set in romstage.c. Some of it is fairly straightforward. Swizzling tables are not and require you to be able to read schematic (and have access to it in the
first place)</div>
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Obviously, the problem could be elsewhere. I would start with enabling MRC debug and perhaps posting the MRC output</div>
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<div id="x_m_5162750830031364199divRplyFwdMsg" dir="ltr"><font color="#000000" face="Calibri, sans-serif" style="font-size:11pt"><b>From:</b> coreboot <<a href="mailto:coreboot-bounces@coreboot.org" target="_blank">coreboot-bounces@coreboot.org</a>> on behalf
of Alexey Borovikov via coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><br>
<b>Sent:</b> Saturday, November 3, 2018 5:38 AM<br>
<b>To:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<b>Subject:</b> [coreboot] How to get correct memory params for FSP</font>
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Hi. </div>
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I port the Coreboot to a board with an SOC Intel Atom E3845 and use FSP for the Baytrail family. The result - postcode is 0x2A. From the descriptions on the Internet, I understand that the problem is in the incorrect memory parameters.</div>
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<div>Question: are there any utilities or methods that will help to get the correct memory parameters when working a regular BIOS from Linux or Windows systems?</div>
<div>Many thanks!</div>
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