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<p class="MsoNormal">Hi Aron, <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I am not able to get the cbmem timestamps. I am using cbmem utility to find the timestamps.<o:p></o:p></p>
<p class="MsoNormal" style="text-indent:.5in"><b><o:p> </o:p></b></p>
<p class="MsoNormal" style="text-indent:.5in"><b>$ . /cbmem -t<o:p></o:p></b></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The above command gives the following error.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><i>Failed to mmap /dev/mem : Operation not permitted<o:p></o:p></i></p>
<p class="MsoNormal"><i><o:p> </o:p></i></p>
<p class="MsoNormal">Could you please help on this?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks & Regards,<o:p></o:p></p>
<p class="MsoNormal">Antony<o:p></o:p></p>
<p class="MsoNormal"><b>From:</b> Aaron Durbin [mailto:adurbin@google.com] <br>
<b>Sent:</b> Thursday, October 11, 2018 9:44 PM<br>
<b>To:</b> Antony AbeePrakash X V <AntonyAbee.PrakashXV@LntTechservices.com><br>
<b>Cc:</b> Coreboot <coreboot@coreboot.org>; Dinesh Kumar <DINESHKUMAR.VARADARAJAN@LNTTECHSERVICES.COM><br>
<b>Subject:</b> Re: [coreboot] MRC in coreboot<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-family:"Tahoma",sans-serif">cbmem timstamps will be needed.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Tahoma",sans-serif"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-family:"Tahoma",sans-serif">Looks like FSP is manipulating the tsc:<o:p></o:p></span></p>
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<pre style="white-space:pre-wrap"><span style="font-size:10.5pt;color:black">BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 exit 0<o:p></o:p></span></pre>
<pre style="white-space:pre-wrap"><span style="font-size:10.5pt;color:black"><o:p> </o:p></span></pre>
<pre style="white-space:pre-wrap"><span style="font-size:10.5pt;color:black">I have a hard time believing that took 4291 seconds. <o:p></o:p></span></pre>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Thu, Oct 11, 2018 at 10:11 AM Antony AbeePrakash X V <<a href="mailto:AntonyAbee.PrakashXV@lnttechservices.com">AntonyAbee.PrakashXV@lnttechservices.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Hi Aaron,<br>
<br>
PFA the console log for your reference.<br>
<br>
Please look into this and provide feedback.<br>
<br>
Thanks,<br>
Antony<br>
<br>
-----Original Message-----<br>
From: Aaron Durbin [mailto:<a href="mailto:adurbin@google.com" target="_blank">adurbin@google.com</a>]<br>
Sent: Thursday, October 11, 2018 7:27 PM<br>
To: Antony AbeePrakash X V <<a href="mailto:AntonyAbee.PrakashXV@LntTechservices.com">AntonyAbee.PrakashXV@LntTechservices.com</a>><br>
Cc: Coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>>; Dinesh Kumar <<a href="mailto:DINESHKUMAR.VARADARAJAN@LNTTECHSERVICES.COM" target="_blank">DINESHKUMAR.VARADARAJAN@LNTTECHSERVICES.COM</a>><br>
Subject: Re: [coreboot] MRC in coreboot<br>
<br>
On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <<a href="mailto:AntonyAbee.PrakashXV@lnttechservices.com" target="_blank">AntonyAbee.PrakashXV@lnttechservices.com</a>> wrote:<br>
><br>
> Hi All,<br>
><br>
> We are able to achieve the memory initialization time reduction. Now we have achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot).<br>
><br>
> We have reduced the unwanted codes. We would like to reduce the boot time to less than 2sec.<br>
><br>
> Could anyone please tell what can be done further ?<br>
<br>
You're going to need to post more information (cbmem timings and console logs).<br>
<br>
><br>
> Thanks,<br>
> Antony<br>
><br>
> -----Original Message-----<br>
> From: Aaron Durbin [mailto:<a href="mailto:adurbin@google.com" target="_blank">adurbin@google.com</a>]<br>
> Sent: Wednesday, September 05, 2018 7:39 PM<br>
> To: Antony AbeePrakash X V <<a href="mailto:AntonyAbee.PrakashXV@LntTechservices.com">AntonyAbee.PrakashXV@LntTechservices.com</a>><br>
> Cc: Coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>><br>
> Subject: Re: [coreboot] MRC in coreboot<br>
><br>
> On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V <<a href="mailto:AntonyAbee.PrakashXV@lnttechservices.com" target="_blank">AntonyAbee.PrakashXV@lnttechservices.com</a>> wrote:<br>
> ><br>
> > Hi,<br>
> ><br>
> ><br>
> ><br>
> > We are developing coreboot for Apollo lake custom board. MRC training data save is enabled in FSP using Binary configuration tool.<br>
> ><br>
> ><br>
> ><br>
> > But we are getting logs like,<br>
> ><br>
> ><br>
> ><br>
> > No MRC cache found.<br>
> ><br>
> > MRC SeCUmaSize memory size from SeC ... 0<br>
> ><br>
> > MRC Parameters not valid. Status is Success<br>
> ><br>
> > MRC:CpuMemoryTest Successful!<br>
> ><br>
> > Saving MRC data using CSE through HECI interface<br>
><br>
> I have never seen this path used in coreboot. This line above is saying CSE is responsible for saving and retrieving training data. In coreboot we use the main processor to save and restore. I suggest reading over the UPD parameters and ensure they match
with our typical use cases. BCT tool enabling 'training data save' sounds like it's enabling CSE path.<br>
><br>
> ><br>
> > Try to find MRC training data HOB.<br>
> ><br>
> > No MRC training data found, perform data save via HECI.<br>
> ><br>
> > Saved MRC training data with status (0x80000003)<br>
> ><br>
> ><br>
> ><br>
> > It seems that MRC data is not found and saved. Also I found that there are options to add MRC file path and mrc.bin in menuconfig. The only option I have is save cached MRC settings.<br>
> ><br>
> ><br>
> ><br>
> > What this mrc.bin will do?<br>
> ><br>
> > How to add the mrc.bin in coreboot?<br>
> ><br>
> ><br>
> ><br>
> > Please explain on this.<br>
> ><br>
> ><br>
> ><br>
> > Thanks & Regards,<br>
> ><br>
> > Antony<br>
> ><br>
> ><br>
> ><br>
> > L&T Technology Services Ltd<br>
> ><br>
> > <a href="http://www.LntTechservices.com" target="_blank">www.LntTechservices.com</a><br>
> ><br>
> > This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.<br>
> ><br>
> > --<br>
> > coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">
coreboot@coreboot.org</a><br>
> > <a href="https://mail.coreboot.org/mailman/listinfo/coreboot" target="_blank">
https://mail.coreboot.org/mailman/listinfo/coreboot</a><br>
> L&T Technology Services Ltd<br>
><br>
> <a href="http://www.LntTechservices.com" target="_blank">www.LntTechservices.com</a><<a href="http://www.lnttechservices.com/" target="_blank">http://www.lnttechservices.com/</a>><br>
><br>
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L&T Technology Services Ltd<br>
<br>
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This Email may contain confidential or privileged information for the intended recipient (s). If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.<o:p></o:p></p>
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