<div dir="auto"><div dir="ltr">Hi Mariusz, Jose, All,<div><br></div><div>Mariusz - Thank you very much for the solution. </div><div>Jose - You wrote "I have never done this way...". </div><div>Can you please suggest a better alternative ?</div><div><br></div><div>Thank you,</div><div>Zvika </div><div><br></div></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Oct 3, 2018 at 8:39 PM Mariusz Szafrański via coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank" rel="noreferrer">coreboot@coreboot.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<div>Hi Jose,</div>
<div><br>
</div>
<div>In your case set:<br>
</div>
<div>ROM chip size = 8MB (your case)<br>
</div>
<div>CBFS_SIZE <= 5MB (your specific case)</div>
<div><br>
</div>
<div>This will build 8M file. After that just cut last 5M of this 8M
file (using any hexeditor) or use something like below from
command line:</div>
<div><br>
</div>
<div>dd if=coreboot.rom of=corebootout.rom bs=1M skip=3</div>
<div><br>
</div>
<div>(before doing that double check if original vendor`s rom file
size is 5242880 bytes long)</div>
<div><br>
</div>
<div>Mariusz<br>
</div>
<div><br>
</div>
<div><br>
</div>
<div class="m_8707496854103654800m_6854870651451811036moz-cite-prefix">W dniu 03.10.2018 o 08:53, Jose
Trujillo via coreboot pisze:<br>
</div>
<blockquote type="cite">
<div>You can do that but I have never done this way and I cannot
help you with that.<br>
</div>
<div><br>
</div>
<div>Someone else can advise on this?<br>
</div>
<div><br>
</div>
<div>‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐<br>
</div>
<div> On Tuesday, October 2, 2018 9:39 PM, Zvi Vered
<a class="m_8707496854103654800m_6854870651451811036moz-txt-link-rfc2396E" href="mailto:veredz72@gmail.com" target="_blank" rel="noreferrer"><veredz72@gmail.com></a> wrote:<br>
</div>
<div> <br>
</div>
<blockquote type="cite" class="m_8707496854103654800m_6854870651451811036protonmail_quote">
<div dir="ltr">
<div dir="ltr">
<div>Hi Jose, All,<br>
</div>
<div><br>
</div>
<div>Highly appreciate your answers. <br>
</div>
<div>It seems the vital information in your replies are not
documented.<br>
</div>
<div><br>
</div>
<div>The original vendor's rom file size is 5MB. <br>
</div>
<div>Do you think I can create a 5MB coreboot.rom ?<br>
</div>
<div><br>
</div>
<div>It seems that AfuEfix64.efi supplied by vendor is
looking for 5MB rom file like the original one. For any
other file size, AfuEfix64 fails. <br>
</div>
<div><br>
</div>
<div>Thank you,<br>
</div>
<div>Zvika <br>
</div>
</div>
</div>
<div><br>
</div>
<div class="gmail_quote">
<div dir="ltr">On Mon, Oct 1, 2018 at 2:08 PM Jose Trujillo
<<a href="mailto:ce.autom@protonmail.com" target="_blank" rel="noreferrer">ce.autom@protonmail.com</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>Zvika:<br>
</div>
<div><br>
</div>
<div>There are 2 ways to build coreboot: (choose one).... <br>
</div>
<div>1.- Including IFD, TXE, GBE etc.... inside coreboot
CBFS.<br>
</div>
<div>2.- Using the original firmware(FW) with IFD, TXE, GBE
already in flash and just rewrite coreboot on top of the
BIOS block.<br>
</div>
<div><br>
</div>
<div>Your original computer Firmware = Intel FW + "BIOS"<br>
</div>
<div class="m_8707496854103654800m_6854870651451811036m_-330431905977586621protonmail_signature_block">
<div class="m_8707496854103654800m_6854870651451811036m_-330431905977586621protonmail_signature_block-user m_8707496854103654800m_6854870651451811036m_-330431905977586621protonmail_signature_block-empty"><br>
</div>
</div>
<div>Intel FW = IFD +PD+ME/TXE+GBE<br>
</div>
<div>BIOS=AMI-Phoenix etc...<br>
</div>
<div><br>
</div>
<div>IFD=Intel Firmware Descriptor Table.<br>
</div>
<div>PD=Parameters<br>
</div>
<div>ME=Management Engine (For "Core" kind of processors).<br>
</div>
<div>TXE=Trusted Execution Engine (For "Atom" kind of
processors).<br>
</div>
<div>GBE=Network card firmware.<br>
</div>
<div><br>
</div>
<div>Zvika said:<br>
</div>
<div>"After creating coreboot.rom should I always use the
original BIOS with ifdtool to convert rom to bin ?"<br>
</div>
<div>Answer:<br>
</div>
<div>No, there are other methods and tools that can do the
merge.... (ifdtool and Intel's FIT are working fine for
me)<br>
</div>
<div><br>
</div>
<div>After the creation of the coreboot build you have 2
ways of doing the flashing for your case: (with fpt).<br>
</div>
<div>1.- Flash the full 8MB (Intel FW+coreboot) if the SPI
flash is blank or have unknown firmware.<br>
</div>
<div> Use IFDTool in this case to inject coreboot to
Intel FW..... then flash it with fpt .<br>
</div>
<div>2.- Flash only the BIOS block (5MB your specific case)
in this case ask someone else how to do it with fpt....<br>
</div>
<div><br>
</div>
<div>I hope this answered your questions.<br>
</div>
<div>Jose..<br>
</div>
<div><br>
</div>
<div>‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐<br>
</div>
<div>On Saturday, September 29, 2018 12:24 AM, Zvi Vered
<<a href="mailto:veredz72@gmail.com" target="_blank" rel="noreferrer">veredz72@gmail.com</a>> wrote:<br>
</div>
<div><br>
</div>
<blockquote type="cite" class="m_8707496854103654800m_6854870651451811036m_-330431905977586621protonmail_quote">
<div dir="ltr">
<div>Hi Jose, <br>
</div>
<div><br>
</div>
<div>You wrote:<br>
</div>
<div>"My recommended approach is using the original
Intel FW with already included the FD, TXE". <br>
</div>
<div><br>
</div>
<div>What is "original intel FW" ? <br>
</div>
<div>What is FD, TXE ?<br>
</div>
<div><br>
</div>
<div>After creating coreboot.rom should I always use the
original BIOS with ifdtool to convert rom to bin ?<br>
</div>
<div><br>
</div>
<div>Thank you,<br>
</div>
<div>Zvika <br>
</div>
</div>
<div><br>
</div>
<div class="gmail_quote">
<div dir="ltr">On Wed, Sep 26, 2018 at 7:27 PM Jose
Trujillo <<a href="mailto:ce.autom@protonmail.com" target="_blank" rel="noreferrer">ce.autom@protonmail.com</a>>
wrote:<br>
</div>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div>You are right Nico,<br>
</div>
<div><br>
</div>
<div>I just forgot the troubles this caused me.<br>
</div>
<div>I am sorry Vika... My mistake.<br>
</div>
<div><br>
</div>
<div>I can confirm with Nico:<br>
</div>
<div>ROM chip size = 8MB (your case)<br>
</div>
<div>CBFS_SIZE = 2 to 5MB (your specific case)<br>
</div>
<div><br>
</div>
<div>My recommended approach is using the original
Intel FW with already included the FD, TXE.<br>
</div>
<div><br>
</div>
<div>I never tested adding regions to coreboot but you
can try.<br>
</div>
<div><br>
</div>
<div>To have better chances of success you should be
dumping hardware settings booting with your original
"BIOS" (look for the attached file).<br>
</div>
<div><br>
</div>
<div>Check if the system is "Memory down"or/and ECC
because it will be needed to edit FSP (if using it).<br>
</div>
<div>Dump memory settings with the following commands:<br>
</div>
<div><br>
</div>
<div>sudo dnf install i2c-tools-perl<br>
</div>
<div>sudo modprobe eeprom<br>
</div>
<div>decode-dimms<br>
</div>
<div><br>
</div>
<div>If you have not done this already there is still
a long way to go.<br>
</div>
<div>Don't get intimidated, just do it, if you have
questions just ask.... I will try to help<br>
</div>
<div><br>
</div>
<div>Good luck,<br>
</div>
<div>Jose.<br>
</div>
<div><br>
</div>
<div><br>
</div>
<div>‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐<br>
</div>
<div>On Wednesday, September 26, 2018 6:28 PM, Nico
Huber <<a href="mailto:nico.h@gmx.de" target="_blank" rel="noreferrer">nico.h@gmx.de</a>>
wrote:<br>
</div>
<div><br>
</div>
<div>> Hi,<br>
</div>
<div>><br>
</div>
<div>> On 9/26/18 9:19 AM, Jose Trujillo via
coreboot wrote:<br>
</div>
<div>><br>
</div>
<div>> > No, don't change it, you change the
size of coreboot only if during the<br>
</div>
<div>> > building process "make" complain that
there is not enough space but in<br>
</div>
<div>> > your case your build was already
successful leave it like that.<br>
</div>
<div>><br>
</div>
<div>> this advice seems very weird to me. I'm not
experienced with Bay Trail.<br>
</div>
<div>> But unless there is a bug in the Bay Trail
code, you should always set<br>
</div>
<div>> the correct ROM_SIZE (to the full flash chip
size). Otherwise you may<br>
</div>
<div>> introduce bugs in code that relies on this
setting (e.g. saving the<br>
</div>
<div>> MRC cache might fail and so would S3
resume).<br>
</div>
<div>><br>
</div>
<div>> CBFS_SIZE however is the setting to adjust
according to your needs. It<br>
</div>
<div>> should be at most the size of the BIOS
region.<br>
</div>
<div>><br>
</div>
<div>> > In the rare circumstance that more
space is required you can increase<br>
</div>
<div>> > coreboot size to 4MB and istill will
fit into your system 5MB of space<br>
</div>
<div>> > available.<br>
</div>
<div>> > "ifdtool" will inject coreboot in the
top of the BYT_orig.bin and save<br>
</div>
<div>> > as BYT_orig.bin.new that you can flash
to your system.<br>
</div>
<div>><br>
</div>
<div>> I assume this doesn't work oob if you set
ROM_SIZE correctly. But it is<br>
</div>
<div>> unnecessary to craft a single file by hand.
You can either only flash<br>
</div>
<div>> the BIOS region (recommended) or add the
other regions in coreboot's<br>
</div>
<div>> config (HAVE_{IFD,ME,GBE}_BIN).<br>
</div>
<div>><br>
</div>
<div>> Nico<br>
</div>
<div><br>
</div>
<div><br>
</div>
</blockquote>
</div>
</blockquote>
<div><br>
</div>
</blockquote>
</div>
</blockquote>
<div><br>
</div>
<br>
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