<div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr"><div dir="ltr">Hi<div><br></div><div><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px">>PCH: device id a152 (rev 31) is Unknown </pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px">This indicates that LPCID 0xa152 is not added.</pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px">The #define should be added in source path: <a href="https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_ids.h#n2721">https://review.coreboot.org/cgit/coreboot.git/tree/src/include/device/pci_ids.h#n2721</a></pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><a href="https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/block/lpc/lpc.c#n131">https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/block/lpc/lpc.c#n131</a></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif">&</font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><a href="https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bootblock/report_platform.c#n73">https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/skylake/bootblock/report_platform.c#n73</a></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="font-family:"Courier New",Courier,monospace,arial,sans-serif;margin-top:0px;margin-bottom:0px;white-space:pre-wrap;color:rgb(0,0,0);font-size:14px"><span style="font-family:Arial,Helvetica,sans-serif;font-size:small;color:rgb(34,34,34)">as well. </span><br></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap"><br></span></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap"><br></span></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap">Additionally you can enable config DEBUG_BOOT_STATE to understand where exactly its stuck.</span></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap"><br></span></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap">Regards,</span></font></pre><pre class="gmail-aLF-aPX-K0-aPE" style="margin-top:0px;margin-bottom:0px"><font color="#000000" face="Courier New, Courier, monospace, arial, sans-serif"><span style="font-size:14px;white-space:pre-wrap">Naresh G. Solanki</span></font></pre></div></div></div></div></div></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Sep 12, 2018 at 9:24 PM Jose Trujillo via coreboot <<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>Dear All,<br></div><div>About the memory I just changed the dimm to address A0 and now coreboot is reporting correctly 1 dimm detected.<br></div><div><br></div><div>But still no luck on the 0x71 post code loop (looks it is in some kind of loop because is still responsive to power and reset buttons).<br></div><div>I don't know where this loop could be located (coreboot or FSP).<br></div><div>The description on the post_codes.h file shows the following:<br></div><div>....<br></div><div>/**<br></div><div>* \brief Initializing Chips<br></div><div>*<br></div><div>* Boot State Machine: bs_dev_init_chips()<br></div><div>*/<br></div><div>#define POST_BS_DEV_INIT_CHIPS 0x71<br></div><div>....<br></div><div><br></div><div>Any advice on this issue?<br></div><div>Attached is the serial dump with extra information.<br></div><div><br></div><div>Thank you<br></div><div>Jose Trujillo<br></div><div><br></div><div>‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐<br></div><div>On Wednesday, 12 September 2018 16:12, Jose Trujillo <<a href="mailto:ce.autom@protonmail.com" target="_blank">ce.autom@protonmail.com</a>> wrote:<br></div><div><br></div><blockquote type="cite" class="m_6333284090513465699protonmail_quote"><div>To begin with the system didn't find memory attached...<br></div><div>but there is memory attached, SPD address mismatch? I will check.<br></div><div>....<br></div><div>.......Timeout while sending command 0x0d to EC! <br></div><div>recv_ec_data: 0xff <br></div><div>recv_ec_data: 0xff <br></div><div>SPD index 7 <br></div><div>No memory dimm at address A0 <br></div><div>No memory dimm at address A2 <br></div><div>No memory dimm at address A6 <br></div><div>....<br></div><div>0 DIMMs found <br></div><div>....<br></div><div><br></div><div>‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐<br></div><div>On Wednesday, 12 September 2018 13:29, Jose Trujillo via coreboot <<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>> wrote:<br></div><div><br></div><blockquote type="cite" class="m_6333284090513465699protonmail_quote"><div>Dear coreboot engineers:<br></div><div><br></div><div>Right now I am stuck with a Kabylake system with the following message:<br></div><div>....<br></div><div>CPU #1 initialized <br></div><div>apic_id: 0x06 done. <br></div><div>microcode: updated to revision 0x8d date=2018-01-21 <br></div><div>CPU #3 initialized <br></div><div>bsp_do_flight_plan done after 220 msecs. <br></div><div>CPU: frequency set to 3600 MHz <br></div><div>Enabling SMIs. <br></div><div>Locking SMM. <br></div><div>VMX : param.enable = 0 <br></div><div>VMX: pre-conditions not met <br></div><div>SGX: pre-conditions not met <br></div><div>VMX: pre-conditions not met <br></div><div>VMX: pre-conditions not met <br></div><div>SGX: pre-conditions not met <br></div><div>SGX: pre-conditions not met <br></div><div>VMX: pre-conditions not met <br></div><div>SGX: pre-conditions not met <br></div><div>POST: 0x71<br></div><div>....<br></div><div><br></div><div>May be some configuration is missing and I am trying to find this out myself but if someone of you can give a hint on how to resolve it I will be grateful.<br></div><div><br></div><div>Attached is the full serial dump.<br></div><div><br></div><div>Thank you,<br></div><div>Jose Trujillo<br></div></blockquote><div><br></div></blockquote><div><br></div>-- <br>
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<a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/mailman/listinfo/coreboot</a></blockquote></div><br clear="all"><div><br></div>-- <br><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><div>Best regards,</div><div>Naresh G. Solanki</div></div></div>