<div dir="ltr">Hi Nico,<div><br></div><div><br></div><div class="gmail_extra"><div class="gmail_quote">On Tue, May 29, 2018 at 10:24 AM, Nico Huber <span dir="ltr"><<a href="mailto:nico.h@gmx.de" target="_blank">nico.h@gmx.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hello Hal,<br>
<span class="gmail-"><br>
On 28.05.2018 08:06, Hal Martin wrote:<br>
> Name Offset Type Size Comp<br>
</span>> ...<br>
<span class="gmail-">> cpu_microcode_blob.bin 0x6f00 microcode 0 none<br>
<br>
</span>The size looks troubling, I think you really need the correct microcode<br>
binary to get into coreboot. Make 100% sure it matches your SKU.<br></blockquote><div><br></div><div><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial">Nice catch! I added the CPU microcode extracted from the original firmware, but unfortunately it hasn't made any difference in the behaviour:</div><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial"><br></div><div style="text-decoration-style:initial;text-decoration-color:initial"><div> CREATE build/mainboard/compulab/fitlet2/cbfs-file.GH4n6d.out (from /home/ubuntu/coreboot/.config)</div><div>Created CBFS (capacity = 12179416 bytes)</div><div> CBFS fallback/romstage</div><div> CBFS cpu_microcode_blob.bin</div><div> CBFS fallback/ramstage</div><div> CBFS config</div><div> CBFS revision</div><div> CBFS fspm.bin</div><div> CBFS fsps.bin</div><div> CBFS fallback/postcar</div><div> CBFS fallback/dsdt.aml</div><div> CBFS fallback/payload</div><div> DD Adding Intel Firmware Descriptor</div><div> IFDTOOL Unlocking Management Engine</div><div>Platform is: aplk</div><div>File build/coreboot.pre is 16777216 bytes</div><div>Writing new image to build/coreboot.pre.new</div><div> CBFS coreboot.rom</div><div> UPDATE-FIT</div><div> CBFSLAYOUT coreboot.rom</div><div><br></div><div>This image contains the following sections that can be manipulated with this tool:</div><div><br></div><div>'SI_DESC' (size 4096, offset 0)</div><div>'IFWI' (size 3141632, offset 4096)</div><div>'COREBOOT' (CBFS, size 12179456, offset 3147776)</div><div>'RECOVERY_MRC_CACHE' (size 65536, offset 15327232)</div><div>'RW_MRC_CACHE' (size 65536, offset 15392768)</div><div>'RW_VAR_MRC_CACHE' (size 4096, offset 15458304)</div><div>'BIOS_UNUSABLE' (size 262144, offset 15462400)</div><div>'DEVICE_EXTENSION' (size 1048576, offset 15724544)</div><div>'UNUSED_HOLE' (size 4096, offset 16773120)</div><div><br></div><div>It is possible to perform either the write action or the CBFS add/remove actions on every section listed above.</div><div>To see the image's read-only sections as well, rerun with the -w option.</div><div> CBFSPRINT coreboot.rom</div><div><br></div><div>Name Offset Type Size Comp</div><div>cbfs master header 0x0 cbfs header 32 none</div><div>fallback/romstage 0x80 stage 31796 none</div><div>cpu_microcode_blob.bin 0x7d00 microcode 53248 none</div><div>fallback/ramstage 0x14d80 stage 72798 none</div><div>config 0x26a40 raw 772 none</div><div>revision 0x26d80 raw 575 none</div><div>fspm.bin 0x27000 fsp 364544 none</div><div>fallback/dsdt.aml 0x80040 raw 99 none</div><div>(empty) 0x80100 null 1688 none</div><div>fsps.bin 0x807c0 fsp 172032 none</div><div>fallback/postcar 0xaa800 stage 21284 none</div><div>fallback/payload 0xafb80 simple elf 633503 none</div><div>(empty) 0x14a680 null 10793240 none</div><div>bootblock 0xb957c0 bootblock 32768 none</div><div><br></div><div>Built compulab/fitlet2 (Fitlet2)</div><div style="font-size:small"><br></div></div><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial"> <br></div></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<span class="gmail-"><br>
> Is it expected that ifwitool will not work on the coreboot generated image?<br>
> Or does this indicate I've made a mistake somewhere?<br>
<br>
</span>I'm not sure. I'd extract the bios/ifwi region using ifdtool and try to<br>
run ifwitool on that.<br></blockquote><div><br></div><div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial">I've also tried to extract the bios region from the coreboot.rom file and run ifdtool on that, but I get the same error message I receive when running ifdtool on the coreboot.rom:</div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><div><br></div><div>E: Image does not contain BPDT!!</div><div>E: ./ifwitool: ifwi parsing failed</div></div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><br></div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial">More and more I am suspecting that something is wrong with the generated image.</div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><br></div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial">Is it possible to generate a "portable" coreboot image that I could use with the Intel FIT tool to replace the vendor BIOS region?</div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial"><br></div><div style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial">I am taking the FSP_M and FSP_S from Intel's Apollo Lake FSP repository, but I believe the vendor is using components from AMI for this. Without uart I'm not even sure if I'm getting to memory/silicon init. But maybe it's necessary to use the FSP components from Intel's repository because otherwise coreboot may call functions that don't exist in AMI's version?</div><span style="font-size:small;background-color:rgb(255,255,255);text-decoration-style:initial;text-decoration-color:initial;float:none;display:inline"></span><br class="gmail-Apple-interchange-newline"><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial"><br></div><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial">Thanks,</div><div style="font-size:small;text-decoration-style:initial;text-decoration-color:initial">Hal</div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<span class="gmail-HOEnZb"><font color="#888888"><br>
Nico<br>
</font></span></blockquote></div><br></div></div>