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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">In case of Harcuvar CRB we have 16M SPI flash: first 8M for ME (which is outside of CBFS) and last 8M for coreboot.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">We need to specify two things in coreboot config:<o:p></o:p></span></p>
<p class="MsoListParagraph" style="text-indent:-18.0pt;mso-list:l0 level1 lfo1"><![if !supportLists]><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">ROM chip size – 16M – physical size of SPI flash (needed for correct flash offset calculations inside coreboot code)<o:p></o:p></span></p>
<p class="MsoListParagraph" style="text-indent:-18.0pt;mso-list:l0 level1 lfo1"><![if !supportLists]><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Size of CBFS filesystem in ROM – 8M (0x800000) or less<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">16M coreboot.rom file should be built with above config.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">You need to manually inject 8M ME blob at offset 0 into ‘coreboot.rom’ file.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Or just flash last 8M from coreboot.rom into last 8M of SPI flash if ME blob is already there.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Mariusz<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><o:p> </o:p></a></p>
<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> coreboot [mailto:coreboot-bounces@coreboot.org]
<b>On Behalf Of </b>Sumo<br>
<b>Sent:</b> Monday, February 26, 2018 9:15 PM<br>
<b>To:</b> coreboot@coreboot.org<br>
<b>Subject:</b> [coreboot] Atom c3000 Harcuvar and Intel ME<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">In the coreboot build menu there is no option regarding the Intel ME integration.<o:p></o:p></p>
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<p class="MsoNormal">The 'coreboot.rom' file is the full SPI flash image or this file is suitable to<o:p></o:p></p>
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<p class="MsoNormal">replace the BIOS region of the SPI flash (0x00800000--0x00ffffff)?<o:p></o:p></p>
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<p class="MsoNormal">(i.e. in the SPI flash we already have a region for Intel ME firmware)<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">Sumo<o:p></o:p></p>
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