============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.1) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6BC Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEBCA0C EntryPoint=0x000FFEBCFE0 enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEBE69C EntryPoint=0x000FFEBEC04 Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEBFBCC EntryPoint=0x000FFEC04D8 Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFEC245C EntryPoint=0x000FFEC331C Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFEC4EE4 EntryPoint=0x000FFEC5B54 [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFEC79AC EntryPoint=0x000FFEF3A34 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 01820000 host = FE191798 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0x3F 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000041 SocketId: 0 CAPID4: 0x24080F03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x94000787 SocketId: 0 CAPID0: 0x00189520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080F03 ; Total Cbos: 02 Cbo List: 0x41 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 4 CpuList: 0x0F ; busIio: 0x00 0x40 0x80 0xC0 ; busUncore: 0x3F 0x7F 0xBF 0xFF ; Reset Type: Cold Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 94 ; Local Base - 01 Reallocation Base - 65 ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; EXTRA 0 94 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Programming RTIDs and other Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x01, 0x1FFF Checkpoint Code: Socket 0, 0xAA, 0x02, 0x1FFF ;******* Programming RTIDs and other Credits - END ******* ;******* Sync Up PBSPs - START ******* ; Setting Ubox Sticky SR07 to 0x00000000 ; Setting Ubox Sticky SR03 to 0x20000007 ; Setting Ubox Sticky SR02 to 0x00000001 ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ;******* Programming MSR for w/a - START ******* ;******* Programming MSR for w/a - END ******* ;******* Programming BGF Overrides - START ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x7D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x11 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x17D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x27D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x37D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x47D ; Wait for mailbox ready ;******* Programming BGF Overrides - END ******* ;******* Full Speed Transition - START *******Checkpoint Code: Socket 0, 0xAB, 0x00, 0x1FFF ; ;Single Socket, no QPI Links to transition ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Full Speed Transition - END ******* ;******* Cod Activate - START ******* ;******* Cod Activate - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 2 Pipe Init starting...Pipe Init completed! Reset Requested: 2 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 2 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449172 sizeof BDAT = 168490 sizeof memSetup = 1448 sizeof memNvram = 136288 sizeof socketNvram = 33684 sizeof memVar = 135009 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1673 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x8D9CD4DF, PPIN Lo = 0xB60C4D61 setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136426 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x1F2C Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Present N0.C0.D0: NVDIMM:N(380)=0x0 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Not Present 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 333ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 N0.C1: Channel disabled in MemSPD: mcId = 0, mcCh = 1 SODIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 The requested memory speed is faster than this processor supports. Set to maxDdrFreq = 6 ratioIndex = 6 Reset requested: non-MRC Entering no zone 2 Initialize DDR Clocks - 16ms mrcTask skipped; Index = 7 Send Status -- Started Send Status -- EXIT, status = 2h Total MRC time = 424ms Setting Last Boot Date = 384 days STOP_MRC_RUN Reset Requested: 2 Pipe Exit starting...Pipe Exit completed! Reset Requested: 2 Checking for Reset Requests ... Send HostResetWarning notification to ME. ME UMA: WARNING: HostResetWarning called on non S3 resume flow (0) - ignored HostResetWarning notification Complete. Issue WARM RESET! BIOS done set Checkpoint Code: Socket 0, 0xAF, 0x42, 0x0000 ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.1) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6BC Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEBCA0C EntryPoint=0x000FFEBCFE0 enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEBE69C EntryPoint=0x000FFEBEC04 Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEBFBCC EntryPoint=0x000FFEC04D8 Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFEC245C EntryPoint=0x000FFEC331C Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFEC4EE4 EntryPoint=0x000FFEC5B54 [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFEC79AC EntryPoint=0x000FFEF3A34 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 01820000 host = FE191798 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0xFF 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000041 SocketId: 0 CAPID4: 0x24080F03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x94000787 SocketId: 0 CAPID0: 0x00189520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080F03 ; Total Cbos: 02 Cbo List: 0x41 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 1 CpuList: 0x01 ; busIio: 0x00 ; busUncore: 0xFF ; Reset Type: Warm Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 94 ; Local Base - 01 Reallocation Base - 65 ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; EXTRA 0 94 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Check for QPI Topology change across reset - START ******* ;******* Check for QPI Topology change across reset - END ******* ;******* Phy/Link Updates On Warm Reset - START ******* ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Phy/Link Updates On Warm Reset - END ******* ;******* Sync Up PBSPs - START ******* ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x91 ; Wait for mailbox ready ;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF ; Locating the Rings Present in the Topology ; No Rings Found ; Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0 ; Adjacency Table ; ---------------- ; Checking for Deadlock... ;CPU0 Topology Tree ;------------------- ;Index Socket ParentSocket ParentPort ParentIndex Hop ; 00 CPU0 -- -- -- 0 ; ; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020 ;CPU 0 Routing Table ;------------------- ;DestSocket Port ;******* Topology Dicovery and Optimum Route Calculation - END ******* ;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF ;******* Program Optimum Route Table Settings - END ******* ;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027 ;******* Program Final IO SAD Setting - END ******* ;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF Lock QPI DFX. ;******* Program Misc. QPI Parameters - END ******* ;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF ;******* Program Home Agent Credits - END ******* ;******* Program Home tracker and Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF ;******* Program Home tracker and Route Back Table - END ******* ;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF ;******* Program System Coherency Registers - END ******* ;******* Check for S3 Resume - START ******* ;******* Check for S3 Resume - END ******* ;******* Collect Previous Boot Error - START ******* ;******* Collect Previous Boot Error - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 0 Pipe Init starting...Pipe Init completed! Reset Requested: 0 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 0 CAPID0[5] is set. SKU Detected as DE.PrevBootErrors - CBO mcbank: 18 - not present; skipping... PrevBootErrors - CBO mcbank: 19 - not present; skipping... PrevBootErrors - CBO mcbank: 20 - not present; skipping... PrevBootErrors - CBO mcbank: 21 - not present; skipping... PrevBootErrors - Valid MCA UC entries: 0 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449172 sizeof BDAT = 168490 sizeof memSetup = 1448 sizeof memNvram = 136288 sizeof socketNvram = 33684 sizeof memVar = 135009 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1673 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x8D9CD4DF, PPIN Lo = 0xB60C4D61 setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136426 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x1F2C Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Present N0.C0.D0: NVDIMM:N(380)=0x0 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Not Present 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 333ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 N0.C1: Channel disabled in MemSPD: mcId = 0, mcCh = 1 SODIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 The requested memory speed is faster than this processor supports. Set to maxDdrFreq = 6 ratioIndex = 6 Memory behind processor 0 running at DDR-1600 Entering no zone 2 Initialize DDR Clocks - 18ms mrcTask skipped; Index = 7 Send Status -- Started Send Status - 0ms Set Vdd -- Started N0: VR0 DDR Voltage: 1.20V Set Vdd - 2ms Check DIMM Ranks -- Started Checkpoint Code: Socket 0, 0xB4, 0x00, 0x0000 N0.C0.D0: dimmMtr: 0x001C514C N0.C0.D1: dimmMtr: 0x000F0000 N0.C0.D2: dimmMtr: 0x000F0000 N0.C1.D0: dimmMtr: 0x000F000C N0.C1.D1: dimmMtr: 0x000F000C N0.C1.D2: dimmMtr: 0x000F000C N0.C2.D0: dimmMtr: 0x000F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x000F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: Lockstep disabled, x4 DIMMs detected N0.C0.D0.R0: size 64 TechIndex 0x4, size 0x40 N0.C0.D0.R1: size 64 TechIndex 0x4, size 0x40 Entering no zone 3 Check DIMM Ranks - 49ms Send Data -- Started Send Data - 0ms Initialize Memory -- Started Initialize Memory - 0ms Gather SPD Data -- Started Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000 N0: SMB Clock Period = 2244 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 Entering no zone 4 Gather SPD Data - 25ms Configure XMP -- Started Configure XMP - 35ms Platform NVDIMM Status -- Started N0: CoreNVDIMMStatus Platform NVDIMM Status - 2ms Early Configuration -- Started Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000 Mem Timings: N0.C0: tCCD=4 N0.C0: tCCD_L=5 N0.C0: tCWL=11 N0.C0: tCL=11 N0.C0: tRP=11 N0.C0: tRCD=11 N0.C0: tRRD_S=4 N0.C0: tRRD_L=4 N0.C0: tWTR=2 N0.C0: tRAS=26 N0.C0: tRTP=6 N0.C0: tWR=12 N0.C0: tFAW=20 N0.C0: tRC=37 N0.C0: tRFC=208 N0.C0: casSup=0xFF8 N0: xoverModeVar = 2 N0.C0: trrMode = 4 N0.C0: twoXRefresh = 0 N0.C0: t_stagger_ref = 0x59 N0.C0.D0.R0: DRAM Rtt_wr = 240, Rtt_park = 60, Rtt_nom = 240 N0.C0.D0.R1: DRAM Rtt_wr = 240, Rtt_park = 60, Rtt_nom = 240 Entering no zone 5 Early Configuration - 48ms DDRIO Initialization -- Started Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000 N0: Enable xovercal N0: Enabling xover 1:1 mode N0.C0: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 2 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 3 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 4 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 5 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 6 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 7 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 8 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 9 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 10 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 11 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 12 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 13 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 14 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 15 0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 16 0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 17 0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 18 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 19 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 20 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 21 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 1 0 0 22 1 1 1 1 1 0 1 1 0 1 1 1 1 1 X 0 1 0 1 1 1 1 1 X 0 23 1 0 1 1 1 0 1 1 X 1 1 1 1 1 X 1 1 X 1 1 1 1 1 X 1 24 1 X 1 1 1 1 1 1 X 1 1 1 1 1 X 1 1 X 1 1 1 1 1 X 1 25 1 X 0 1 1 1 1 1 X 1 0 1 1 1 X 1 1 X 1 0 1 1 1 X 1 26 1 X X 1 1 1 1 1 X 1 X 1 0 1 X 1 1 X 1 X 1 0 1 X 1 27 1 X X 0 0 1 1 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 28 1 X X X X 1 1 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 29 1 X X X X 1 0 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 30 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 31 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 32 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 33 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 34 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 35 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 36 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 37 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 38 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 39 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 40 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 41 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 42 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 43 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 44 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 45 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 46 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 47 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 48 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 49 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 50 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 51 1 X X X X 1 X 1 X 1 X 1 X 1 X 1 1 X 1 X 1 X 1 X 1 52 1 X X X X 1 X 0 X 1 X 1 X 1 X 1 0 X 1 X 1 X 1 X 1 53 1 X X X X 1 X X X 1 X 1 X 1 X 1 X X 1 X 1 X 1 X 1 54 0 X X X X 1 X X X 1 X 1 X 0 X 1 X X 1 X 1 X 0 X 1 55 X X X X X 1 X X X 1 X 1 X X X 1 X X 0 X 1 X X X 1 56 X X X X X 1 X X X 0 X 1 X X X 1 X X X X 1 X X X 1 57 X X X X X 1 X X X X X 1 X X X 1 X X X X 1 X X X 1 58 X X X X X 1 X X X X X 1 X X X 1 X X X X 1 X X X 1 59 X X X X X 0 X X X X X 0 X X X 0 X X X X 0 X X X 0 breakOut set! N0.C0: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 48 19 17 21 21 53 23 46 16 50 19 53 20 48 15 53 N0: SetStartingCCC => CpuSku= 0, CtlEntries= 84 N0.C0: CTL Group 6, CTL side 1, piDelay 108 N0.C0: CTL Group 0, CTL side 1, piDelay 108 N0.C0: CTL Group 0, CTL side 0, piDelay 108 N0.C0: CTL Group 8, CTL side 1, piDelay 108 N0.C0: CTL Group 7, CTL side 1, piDelay 108 N0.C0: CTL Group 1, CTL side 1, piDelay 108 N0.C0: CTL Group 1, CTL side 0, piDelay 108 N0.C0: CTL Group 9, CTL side 1, piDelay 108 N0.C0: CTL Group 2, CTL side 1, piDelay 108 N0.C0: CTL Group 2, CTL side 0, piDelay 108 N0.C0: CTL Group 6, CTL side 0, piDelay 108 N0.C0: CTL Group 7, CTL side 0, piDelay 108 N0.C0: CTL Group 10, CTL side 1, piDelay 108 N0.C0: CTL Group 3, CTL side 1, piDelay 108 N0.C0: CTL Group 3, CTL side 0, piDelay 108 N0.C0: CTL Group 4, CTL side 0, piDelay 108 N0.C0: CTL Group 5, CTL side 0, piDelay 108 N0.C0: CTL Group 8, CTL side 0, piDelay 108 N0.C0: CTL Group 9, CTL side 0, piDelay 108 N0.C0: CTL Group 4, CTL side 1, piDelay 108 N0.C0: CTL Group 5, CTL side 1, piDelay 108 N0: SetStartingCCC => CpuSku= 0, CmdEntries= 48 N0.C0: CMD Group 0, CMD side 1, piDelay 103 N0.C0: CMD Group 3, CMD side 1, piDelay 103 N0.C0: CMD Group 4, CMD side 1, piDelay 103 N0.C0: CMD Group 1, CMD side 1, piDelay 103 N0.C0: CMD Group 1, CMD side 0, piDelay 103 N0.C0: CMD Group 0, CMD side 0, piDelay 103 N0.C0: CMD Group 3, CMD side 0, piDelay 103 N0.C0: CMD Group 4, CMD side 0, piDelay 103 N0.C0: CMD Group 2, CMD side 1, piDelay 103 N0.C0: CMD Group 2, CMD side 0, piDelay 103 N0.C0: CMD Group 5, CMD side 1, piDelay 103 N0.C0: CMD Group 5, CMD side 0, piDelay 103 N0: SetStartingCCC => CpuSku= 0, ClkEntries= 16 N0.C0: CLK 0, piDelay 128 N0.C0: CLK 2, piDelay 128 N0.C0: CLK 1, piDelay 128 N0.C0: CLK 3, piDelay 128 Reset All Channels JEDEC Init N0.C0: Issue ZQCL N0: Stage 1: Vref Offset Training Plot Of SumOfBits across Vref settings VR SA 0 1 2 3 4 5 6 7 8 N0.C0: 10 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 10 11 0 0 0 0 0 0 0 0 0 N0.C0: 11 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 11 11 0 0 0 0 0 0 0 0 0 N0.C0: 12 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 12 11 0 0 0 0 0 0 0 0 0 N0.C0: 13 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 13 11 0 0 0 0 0 0 0 0 0 N0.C0: 14 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 14 11 0 0 0 0 0 0 0 0 0 N0.C0: 15 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 15 11 0 0 0 0 0 0 0 0 0 N0.C0: 16 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 16 11 0 0 0 0 0 0 0 0 0 N0.C0: 17 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 17 11 0 0 0 0 0 0 0 0 0 N0.C0: 18 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 18 11 0 0 0 0 0 0 0 0 0 N0.C0: 19 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 19 11 0 0 0 0 0 0 0 0 0 N0.C0: 20 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 20 11 0 0 0 0 0 0 0 0 0 N0.C0: 21 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 21 11 0 0 0 0 0 0 0 0 0 N0.C0: 22 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 22 11 0 0 0 0 0 0 0 0 0 N0.C0: 23 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 23 11 0 0 0 0 0 0 0 0 0 N0.C0: 24 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 24 11 0 0 0 0 0 0 0 0 0 N0.C0: 25 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 25 11 0 0 0 0 0 0 0 0 0 N0.C0: 26 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 26 11 0 0 0 0 0 0 0 0 0 N0.C0: 27 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 27 11 0 0 0 0 0 0 0 0 0 N0.C0: 28 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 28 11 0 0 0 0 0 0 0 0 0 N0.C0: 29 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 29 11 0 0 0 0 0 0 0 0 0 N0.C0: 30 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 30 11 0 0 0 0 0 0 0 0 0 N0.C0: 31 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 31 11 0 0 0 0 0 0 0 0 0 N0.C0: 32 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 32 11 0 0 0 0 0 0 0 0 0 N0.C0: 33 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 33 11 0 0 0 0 0 0 0 0 0 N0.C0: 34 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 34 11 0 0 0 0 0 0 0 0 0 N0.C0: 35 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 35 11 0 0 0 0 0 0 0 0 0 N0.C0: 36 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C0: 36 11 0 0 0 0 0 0 0 0 0 N0.C0: 37 19 -7 -8 -8 -8 -8 -8 -7 -8 -8 N0.C0: 37 11 1 0 0 0 0 0 1 0 0 N0.C0: 38 19 -6 -7 -7 -8 -7 -7 -7 -8 -5 N0.C0: 38 11 2 1 1 0 1 1 1 0 3 N0.C0: 39 19 -4 -1 -6 -6 -5 -7 -6 -8 -3 N0.C0: 39 11 4 7 2 2 3 1 2 0 5 N0.C0: 40 19 -2 -1 -4 -1 -2 -5 -4 -4 -1 N0.C0: 40 11 6 7 4 7 6 3 4 4 7 N0.C0: 41 19 -2 0 -1 -1 -1 -3 -3 -2 -1 N0.C0: 41 11 6 8 7 7 7 5 5 6 7 N0.C0: 42 19 -1 0 0 -1 0 -1 -3 -1 -1 N0.C0: 42 11 7 8 8 7 8 7 5 7 7 N0.C0: 43 19 0 0 0 0 0 0 -1 0 0 N0.C0: 43 11 8 8 8 8 8 8 7 8 8 N0.C0: 44 19 0 0 0 0 0 0 -1 0 0 N0.C0: 44 11 8 8 8 8 8 8 7 8 8 N0.C0: 45 19 0 0 0 0 0 0 0 0 0 N0.C0: 45 11 8 8 8 8 8 8 8 8 8 N0.C0: 46 19 0 0 0 0 0 0 0 0 0 N0.C0: 46 11 8 8 8 8 8 8 8 8 8 N0.C0: 47 19 0 0 0 0 0 0 0 0 0 N0.C0: 47 11 8 8 8 8 8 8 8 8 8 N0.C0: 48 19 0 0 0 0 0 0 0 0 0 N0.C0: 48 11 7 8 8 8 8 8 8 8 8 N0.C0: 49 19 0 0 0 0 0 0 0 0 0 N0.C0: 49 11 6 8 7 8 8 8 7 8 8 N0.C0: 50 19 0 0 0 0 0 0 0 0 0 N0.C0: 50 11 4 6 7 8 7 7 7 8 7 N0.C0: 51 19 0 0 0 0 0 0 0 0 0 N0.C0: 51 11 2 1 4 4 5 7 6 8 3 N0.C0: 52 19 0 0 0 0 0 0 0 0 0 N0.C0: 52 11 2 1 3 2 3 4 3 3 1 N0.C0: 53 19 0 0 0 0 0 0 0 0 0 N0.C0: 53 11 1 0 0 1 1 4 3 2 1 N0.C0: 54 19 0 0 0 0 0 0 0 0 0 N0.C0: 54 11 0 0 0 0 0 1 1 0 1 N0.C0: 55 19 0 0 0 0 0 0 0 0 0 N0.C0: 55 11 0 0 0 0 0 0 1 0 0 N0.C0: 56 19 0 0 0 0 0 0 0 0 0 N0.C0: 56 11 0 0 0 0 0 0 1 0 0 N0.C0: 57 19 0 0 0 0 0 0 0 0 0 N0.C0: 57 11 0 0 0 0 0 0 0 0 0 N0.C0: 58 19 0 0 0 0 0 0 0 0 0 N0.C0: 58 11 0 0 0 0 0 0 0 0 0 N0.C0: 59 19 0 0 0 0 0 0 0 0 0 N0.C0: 59 11 0 0 0 0 0 0 0 0 0 N0.C0: 60 19 0 0 0 0 0 0 0 0 0 N0.C0: 60 11 0 0 0 0 0 0 0 0 0 N0.C0: 61 19 0 0 0 0 0 0 0 0 0 N0.C0: 61 11 0 0 0 0 0 0 0 0 0 N0.C0: 62 19 0 0 0 0 0 0 0 0 0 N0.C0: 62 11 0 0 0 0 0 0 0 0 0 N0.C0: 63 19 0 0 0 0 0 0 0 0 0 N0.C0: 63 11 0 0 0 0 0 0 0 0 0 N0.C0: 64 19 0 0 0 0 0 0 0 0 0 N0.C0: 64 11 0 0 0 0 0 0 0 0 0 N0.C0: 65 19 0 0 0 0 0 0 0 0 0 N0.C0: 65 11 0 0 0 0 0 0 0 0 0 N0.C0: 66 19 0 0 0 0 0 0 0 0 0 N0.C0: 66 11 0 0 0 0 0 0 0 0 0 N0.C0: 67 19 0 0 0 0 0 0 0 0 0 N0.C0: 67 11 0 0 0 0 0 0 0 0 0 N0.C0: 68 19 0 0 0 0 0 0 0 0 0 N0.C0: 68 11 0 0 0 0 0 0 0 0 0 N0.C0: 69 19 0 0 0 0 0 0 0 0 0 N0.C0: 69 11 0 0 0 0 0 0 0 0 0 N0.C0: 70 19 0 0 0 0 0 0 0 0 0 N0.C0: 70 11 0 0 0 0 0 0 0 0 0 N0.C0: 71 19 0 0 0 0 0 0 0 0 0 N0.C0: 71 11 0 0 0 0 0 0 0 0 0 N0.C0: 72 19 0 0 0 0 0 0 0 0 0 N0.C0: 72 11 0 0 0 0 0 0 0 0 0 N0.C0: 73 19 0 0 0 0 0 0 0 0 0 N0.C0: 73 11 0 0 0 0 0 0 0 0 0 N0.C0: 74 19 0 0 0 0 0 0 0 0 0 N0.C0: 74 11 0 0 0 0 0 0 0 0 0 N0.C0: Vref 46 46 46 47 46 47 47 48 47 Stage 2: SampOffset Training 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SA 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 N0.C0: 0 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 1 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 2 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 3 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 4 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 5 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 6 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 7 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 8 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 9 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 10 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C0: 13 11111111 11111111 11111111 10111111 11001101 11110111 11111111 10111111 10111111 N0.C0: 14 11100100 11110010 10111101 10110100 01000100 00110111 10100111 00110111 00110100 N0.C0: 15 10100000 10000000 00101101 10000000 00000000 00000100 10000010 00010110 00000100 N0.C0: 16 10000000 00000000 00000000 00000000 00000000 00000000 00000010 00000100 00000000 N0.C0: 17 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000100 00000000 N0.C0: 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 19 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 20 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 21 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 22 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 25 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 26 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 27 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 28 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 29 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C0: 31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BitSAmp bit: 0 1 2 3 N0.C0: Nibble 0: 16 14 15 13 N0.C0: Nibble 1: 13 14 13 13 N0.C0: Nibble 2: 15 14 14 14 N0.C0: Nibble 3: 13 13 14 13 N0.C0: Nibble 4: 14 13 15 14 N0.C0: Nibble 5: 15 15 13 15 N0.C0: Nibble 6: 15 12 14 14 N0.C0: Nibble 7: 13 14 13 13 N0.C0: Nibble 8: 13 14 12 12 N0.C0: Nibble 9: 13 14 12 13 N0.C0: Nibble 10: 13 13 14 14 N0.C0: Nibble 11: 12 15 14 14 N0.C0: Nibble 12: 15 13 14 13 N0.C0: Nibble 13: 13 14 16 14 N0.C0: Nibble 14: 13 12 14 15 N0.C0: Nibble 15: 13 17 15 14 N0.C0: Nibble 16: 13 12 14 14 N0.C0: Nibble 17: 13 15 13 13 N0: SenseAmpOffset - 929ms N0.C0: Number of DIMMS in channel: 1 Entering no zone 6 DDRIO Initialization - 1825ms Pre-Training Initialization -- Started Pre-Training Initialization - 0ms Early CTL/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x1A, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Early Ctl Clk Receive Enable Pi S0, Ch0, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 2 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 3 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 4 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 5 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 6 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 7 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 8 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 9 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 10 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 11 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 12 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 13 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 14 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 15 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 16 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 17 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 18 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 19 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 20 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 21 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 22 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 23 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 24 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 25 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 26 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 27 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 28 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 29 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 30 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 31 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 32 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 33 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 34 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 35 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 36 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 37 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 38 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 39 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 40 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 41 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 42 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 43 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 44 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 45 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 46 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 47 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 48 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 49 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 50 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 51 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 52 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 53 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 54 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 55 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 56 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 57 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 58 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 59 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 60 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 61 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 62 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 63 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 64 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 65 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 66 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 67 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 68 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 69 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 70 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 71 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 72 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 73 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 74 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 75 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 76 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 77 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 78 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 79 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 80 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 81 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 82 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 83 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 84 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 85 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 86 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 87 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 88 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 89 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 90 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 91 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 92 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 93 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 94 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 95 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 96 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 97 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 98 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 99 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 100 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 101 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 102 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 103 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 104 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 105 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 106 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 107 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 108 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 109 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 110 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 111 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 112 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 113 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 114 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 115 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 116 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 117 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 118 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 119 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 120 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 121 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 122 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 123 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 124 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 125 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 126 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 127 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 ---------------------------------------------------------------------------- RE: 102 118 75 5 39 96 62 86 22 110 1 83 12 47 104 70 94 29 CP: 3 21 106 36 69 125 92 114 51 11 30 114 42 76 4 101 121 58 FE: 33 52 10 67 99 26 123 15 80 40 60 18 73 105 33 4 21 88 PW: 59 62 63 62 60 58 61 57 58 58 59 63 61 58 57 62 55 59 N0.C0.D0.R0.S00: Rec En Delay 3 N0.C0.D0.R0.S01: Rec En Delay 21 N0.C0.D0.R0.S02: Rec En Delay 106 N0.C0.D0.R0.S03: Rec En Delay 36 N0.C0.D0.R0.S04: Rec En Delay 69 N0.C0.D0.R0.S05: Rec En Delay 125 N0.C0.D0.R0.S06: Rec En Delay 92 N0.C0.D0.R0.S07: Rec En Delay 114 N0.C0.D0.R0.S08: Rec En Delay 51 N0.C0.D0.R0.S09: Rec En Delay 11 N0.C0.D0.R0.S10: Rec En Delay 30 N0.C0.D0.R0.S11: Rec En Delay 114 N0.C0.D0.R0.S12: Rec En Delay 42 N0.C0.D0.R0.S13: Rec En Delay 76 N0.C0.D0.R0.S14: Rec En Delay 4 N0.C0.D0.R0.S15: Rec En Delay 101 N0.C0.D0.R0.S16: Rec En Delay 121 N0.C0.D0.R0.S17: Rec En Delay 58 N0.C0.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 57 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 55 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 53 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 51 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 49 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 47 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 45 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 43 N0.C0.D0.R0: IO Latency = 6 zeroFlag = 0x4000, allZeros[0] = 0x3FFFF N0.C0.D0.R0.S14: Rec En Delay = 132 N0.C0.D0.R0: IO Latency = 8 zeroFlag = 0x3F7FB, allZeros[0] = 0x3FFFF N0.C0.D0.R0.S00: Rec En Delay = 131 N0.C0.D0.R0.S01: Rec En Delay = 149 N0.C0.D0.R0.S03: Rec En Delay = 164 N0.C0.D0.R0.S04: Rec En Delay = 197 N0.C0.D0.R0.S05: Rec En Delay = 253 N0.C0.D0.R0.S06: Rec En Delay = 220 N0.C0.D0.R0.S07: Rec En Delay = 242 N0.C0.D0.R0.S08: Rec En Delay = 179 N0.C0.D0.R0.S09: Rec En Delay = 139 N0.C0.D0.R0.S10: Rec En Delay = 158 N0.C0.D0.R0.S12: Rec En Delay = 170 N0.C0.D0.R0.S13: Rec En Delay = 204 N0.C0.D0.R0.S14: Rec En Delay = 260 N0.C0.D0.R0.S15: Rec En Delay = 229 N0.C0.D0.R0.S16: Rec En Delay = 249 N0.C0.D0.R0.S17: Rec En Delay = 186 N0.C0.D0.R0: Round trip latency: Found all zeros Early CTL CLK Receive Enable Summary ------------------------ START_DATA_EARLY_CTL_CLK_REC_EN N0.C0.D0.R0.S00: Pi setting = 163 N0.C0.D0.R0.S01: Pi setting = 181 N0.C0.D0.R0.S02: Pi setting = 138 N0.C0.D0.R0.S03: Pi setting = 196 N0.C0.D0.R0.S04: Pi setting = 229 N0.C0.D0.R0.S05: Pi setting = 285 N0.C0.D0.R0.S06: Pi setting = 252 N0.C0.D0.R0.S07: Pi setting = 274 N0.C0.D0.R0.S08: Pi setting = 211 N0.C0.D0.R0.S09: Pi setting = 171 N0.C0.D0.R0.S10: Pi setting = 190 N0.C0.D0.R0.S11: Pi setting = 146 N0.C0.D0.R0.S12: Pi setting = 202 N0.C0.D0.R0.S13: Pi setting = 236 N0.C0.D0.R0.S14: Pi setting = 292 N0.C0.D0.R0.S15: Pi setting = 261 N0.C0.D0.R0.S16: Pi setting = 281 N0.C0.D0.R0.S17: Pi setting = 218 N0.C0.D0.R0: IO Latency = 8 N0.C0.D0.R0: Round Trip = 43 STOP_DATA_EARLY_CTL_CLK_REC_EN N0.D0.R1: RecEn Pi Scanning: Summary: Early Ctl Clk Receive Enable Pi S0, Ch0, DIMM0, Rank1 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 2 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 3 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 4 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 5 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 6 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 7 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 0 8 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 9 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 10 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 11 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 12 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 13 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 14 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 15 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 16 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 17 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 18 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 19 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 20 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 21 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 22 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 23 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 24 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 25 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 26 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 27 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 28 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 29 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 30 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 31 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 32 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 33 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 34 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 35 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 36 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 37 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 38 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 39 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 40 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 41 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 42 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 43 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 44 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 45 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 46 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 47 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 48 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 49 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 50 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 51 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 52 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 53 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 54 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 55 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 56 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 57 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 58 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 59 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 60 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 61 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 62 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 63 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 64 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 65 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 66 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 67 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 68 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 69 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 70 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 71 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 72 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 73 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 74 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 75 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 76 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 77 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 78 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 79 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 80 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 81 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 82 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 83 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 84 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 85 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 86 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 87 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 88 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 89 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 90 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 91 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 92 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 93 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 94 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 95 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 96 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 97 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 98 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 99 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 100 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 101 1 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 102 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 103 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 104 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 105 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 106 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 107 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 108 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 109 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 110 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 111 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 112 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 113 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 114 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 115 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 116 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 117 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 118 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 119 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 120 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 121 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 122 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 123 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 124 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 125 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 126 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 127 1 1 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 ---------------------------------------------------------------------------- RE: 101 125 84 10 44 102 69 92 25 111 5 92 19 53 109 77 101 36 CP: 2 28 114 39 73 3 100 120 56 11 36 121 47 82 10 106 1 65 FE: 31 60 16 69 102 32 4 21 87 40 67 23 76 111 40 8 30 94 PW: 58 63 60 59 58 58 63 57 62 57 62 59 57 58 59 59 57 58 N0.C0.D0.R1.S00: Rec En Delay 2 N0.C0.D0.R1.S01: Rec En Delay 28 N0.C0.D0.R1.S02: Rec En Delay 114 N0.C0.D0.R1.S03: Rec En Delay 39 N0.C0.D0.R1.S04: Rec En Delay 73 N0.C0.D0.R1.S05: Rec En Delay 3 N0.C0.D0.R1.S06: Rec En Delay 100 N0.C0.D0.R1.S07: Rec En Delay 120 N0.C0.D0.R1.S08: Rec En Delay 56 N0.C0.D0.R1.S09: Rec En Delay 11 N0.C0.D0.R1.S10: Rec En Delay 36 N0.C0.D0.R1.S11: Rec En Delay 121 N0.C0.D0.R1.S12: Rec En Delay 47 N0.C0.D0.R1.S13: Rec En Delay 82 N0.C0.D0.R1.S14: Rec En Delay 10 N0.C0.D0.R1.S15: Rec En Delay 106 N0.C0.D0.R1.S16: Rec En Delay 1 N0.C0.D0.R1.S17: Rec En Delay 65 N0.C0.D0.R1: Round trip latency = 73 IO latency = 4 N0.D0.R1: Round trip latency N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 71 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 69 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 67 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 65 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 63 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 61 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 59 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 57 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 55 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 53 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 51 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 49 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 47 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 45 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 43 N0.C0.D0.R1: IO Latency = 6 zeroFlag = 0x14020, allZeros[0] = 0x3FFFF N0.C0.D0.R1.S05: Rec En Delay = 131 N0.C0.D0.R1.S14: Rec En Delay = 138 N0.C0.D0.R1.S16: Rec En Delay = 129 N0.C0.D0.R1: IO Latency = 8 zeroFlag = 0x3F7FB, allZeros[0] = 0x3FFFF N0.C0.D0.R1.S00: Rec En Delay = 130 N0.C0.D0.R1.S01: Rec En Delay = 156 N0.C0.D0.R1.S03: Rec En Delay = 167 N0.C0.D0.R1.S04: Rec En Delay = 201 N0.C0.D0.R1.S05: Rec En Delay = 259 N0.C0.D0.R1.S06: Rec En Delay = 228 N0.C0.D0.R1.S07: Rec En Delay = 248 N0.C0.D0.R1.S08: Rec En Delay = 184 N0.C0.D0.R1.S09: Rec En Delay = 139 N0.C0.D0.R1.S10: Rec En Delay = 164 N0.C0.D0.R1.S12: Rec En Delay = 175 N0.C0.D0.R1.S13: Rec En Delay = 210 N0.C0.D0.R1.S14: Rec En Delay = 266 N0.C0.D0.R1.S15: Rec En Delay = 234 N0.C0.D0.R1.S16: Rec En Delay = 257 N0.C0.D0.R1.S17: Rec En Delay = 193 N0.C0.D0.R1: Round trip latency: Found all zeros Early CTL CLK Receive Enable Summary ------------------------ START_DATA_EARLY_CTL_CLK_REC_EN N0.C0.D0.R1.S00: Pi setting = 162 N0.C0.D0.R1.S01: Pi setting = 188 N0.C0.D0.R1.S02: Pi setting = 146 N0.C0.D0.R1.S03: Pi setting = 199 N0.C0.D0.R1.S04: Pi setting = 233 N0.C0.D0.R1.S05: Pi setting = 291 N0.C0.D0.R1.S06: Pi setting = 260 N0.C0.D0.R1.S07: Pi setting = 280 N0.C0.D0.R1.S08: Pi setting = 216 N0.C0.D0.R1.S09: Pi setting = 171 N0.C0.D0.R1.S10: Pi setting = 196 N0.C0.D0.R1.S11: Pi setting = 153 N0.C0.D0.R1.S12: Pi setting = 207 N0.C0.D0.R1.S13: Pi setting = 242 N0.C0.D0.R1.S14: Pi setting = 298 N0.C0.D0.R1.S15: Pi setting = 266 N0.C0.D0.R1.S16: Pi setting = 289 N0.C0.D0.R1.S17: Pi setting = 225 N0.C0.D0.R1: IO Latency = 8 N0.C0.D0.R1: Round Trip = 43 STOP_DATA_EARLY_CTL_CLK_REC_EN START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C0: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C0: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C0: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 N0.C0.D0.R0: le = -40 - re = 81 width = 121 N0.C0.D0.R1: le = -44 - re = 81 width = 125 N0.C0: Ctl group 0, left edge = -40 - right edge = 81 offset == 20 width =121 N0.C0: Ctl group 1, left edge = -44 - right edge = 81 offset == 18 width =125 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C0: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C0: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C0: 128 126 108 108 108 108 108 108 108 108 128 126 108 108 108 108 128 126 128 108 108 Entering no zone 7 Early CTL/CLK - 2910ms Early CMD/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x0C, 0x0000 START_PARITY_CMD_CLK N0.C0: Setting cmd timing to 0 N0.C0.D0.R0: Setting RTL to 39 N0.C0.D0.R1: Setting RTL to 39 N0: Enabling C/A Parity N0.C0.D0.R0: PAR -> **************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -53 - re = 66 N0.C0.D0.R1: PAR -> ********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -47 - re = 72 N0.C0.D0.R0: CAS_N -> ******************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000**************************************************************************************** N0.C0.D0.R0: le = -49 - re = 64 N0.C0.D0.R1: CAS_N -> **********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R1: le = -45 - re = 70 N0.C0.D0.R0: A13 -> ******************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -49 - re = 66 N0.C0.D0.R1: A13 -> ************************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -43 - re = 72 N0.C0.D0.R0: RAS_N -> **********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -45 - re = 68 N0.C0.D0.R1: RAS_N -> **********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -45 - re = 72 N0.C0.D0.R0: WE_N -> ********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -47 - re = 66 N0.C0.D0.R1: WE_N -> **************************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -41 - re = 72 N0.C0.D0.R0: A10 -> ****************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -51 - re = 66 N0.C0.D0.R1: A10 -> ********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R1: le = -47 - re = 68 N0.C0.D0.R0: BA1 -> ******************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -49 - re = 68 N0.C0.D0.R1: BA1 -> ************************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R1: le = -43 - re = 70 N0.C0.D0.R0: A0 -> **************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000**************************************************************************************** N0.C0.D0.R0: le = -53 - re = 64 N0.C0.D0.R1: A0 -> ******************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R1: le = -49 - re = 70 N0.C0.D0.R0: BA0 -> ****************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C0.D0.R0: le = -51 - re = 62 N0.C0.D0.R1: BA0 -> ******************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R1: le = -49 - re = 68 N0.C0.D0.R0: A1 -> ********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -47 - re = 68 N0.C0.D0.R1: A1 -> ************************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************** N0.C0.D0.R1: le = -43 - re = 74 N0.C0.D0.R0: A3 -> ****************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -51 - re = 68 N0.C0.D0.R1: A3 -> ************************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -43 - re = 72 N0.C0.D0.R0: A2 -> ****************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -51 - re = 68 N0.C0.D0.R1: A2 -> ********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -47 - re = 72 N0.C0.D0.R0: A4 -> **************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -53 - re = 66 N0.C0.D0.R1: A4 -> ********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R1: le = -47 - re = 68 N0.C0.D0.R0: A5 -> ****************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R0: le = -51 - re = 66 N0.C0.D0.R1: A5 -> **********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R1: le = -45 - re = 70 N0.C0.D0.R0: A6 -> ********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R0: le = -47 - re = 70 N0.C0.D0.R1: A6 -> **************************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000**************************************************************************** N0.C0.D0.R1: le = -41 - re = 76 N0.C0.D0.R0: A7 -> **************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C0.D0.R0: le = -53 - re = 62 N0.C0.D0.R1: A7 -> ********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R1: le = -47 - re = 68 N0.C0.D0.R0: A8 -> ********************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -47 - re = 68 N0.C0.D0.R1: A8 -> **********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -45 - re = 72 N0.C0.D0.R0: A9 -> ******************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************** N0.C0.D0.R0: le = -49 - re = 70 N0.C0.D0.R1: A9 -> ************************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -43 - re = 72 N0.C0.D0.R0: A12 -> **********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -45 - re = 68 N0.C0.D0.R1: A12 -> ************************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************** N0.C0.D0.R1: le = -43 - re = 74 N0.C0.D0.R0: A11 -> ******************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -49 - re = 68 N0.C0.D0.R1: A11 -> **********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R1: le = -45 - re = 66 N0.C0.D0.R0: BG1 -> ****************************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000**************************************************************************************** N0.C0.D0.R0: le = -51 - re = 64 N0.C0.D0.R1: BG1 -> ********************************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************** N0.C0.D0.R1: le = -47 - re = 66 N0.C0.D0.R0: ACT_N -> ******************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -49 - re = 68 N0.C0.D0.R1: ACT_N -> **********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -45 - re = 72 N0.C0.D0.R0: BG0 -> ******************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************ N0.C0.D0.R0: le = -49 - re = 68 N0.C0.D0.R1: BG0 -> **********************************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************** N0.C0.D0.R1: le = -45 - re = 72 N0.C0: PAR: CMD Pi Group 9 clk 0: le -53 re = 66, cmdLeft = -53 cmdRight = 66 N0.C0: CAS_N: CMD Pi Group 7 clk 0: le -49 re = 64, cmdLeft = -49 cmdRight = 64 N0.C0: A13: CMD Pi Group 11 clk 0: le -49 re = 66, cmdLeft = -49 cmdRight = 66 N0.C0: RAS_N: CMD Pi Group 1 clk 0: le -45 re = 68, cmdLeft = -45 cmdRight = 68 N0.C0: WE_N: CMD Pi Group 7 clk 0: le -47 re = 66, cmdLeft = -47 cmdRight = 64 N0.C0: A10: CMD Pi Group 1 clk 0: le -51 re = 66, cmdLeft = -45 cmdRight = 66 N0.C0: BA1: CMD Pi Group 11 clk 0: le -49 re = 68, cmdLeft = -49 cmdRight = 66 N0.C0: A0: CMD Pi Group 9 clk 0: le -53 re = 64, cmdLeft = -53 cmdRight = 64 N0.C0: BA0: CMD Pi Group 4 clk 0: le -51 re = 62, cmdLeft = -51 cmdRight = 62 N0.C0: A1: CMD Pi Group 3 clk 0: le -47 re = 68, cmdLeft = -47 cmdRight = 68 N0.C0: A3: CMD Pi Group 8 clk 0: le -51 re = 68, cmdLeft = -51 cmdRight = 68 N0.C0: A2: CMD Pi Group 3 clk 0: le -51 re = 68, cmdLeft = -47 cmdRight = 68 N0.C0: A4: CMD Pi Group 8 clk 0: le -53 re = 66, cmdLeft = -51 cmdRight = 66 N0.C0: A5: CMD Pi Group 2 clk 0: le -51 re = 66, cmdLeft = -51 cmdRight = 66 N0.C0: A6: CMD Pi Group 2 clk 0: le -47 re = 70, cmdLeft = -47 cmdRight = 66 N0.C0: A7: CMD Pi Group 6 clk 0: le -53 re = 62, cmdLeft = -53 cmdRight = 62 N0.C0: A8: CMD Pi Group 6 clk 0: le -47 re = 68, cmdLeft = -47 cmdRight = 62 N0.C0: A9: CMD Pi Group 0 clk 0: le -49 re = 70, cmdLeft = -49 cmdRight = 70 N0.C0: A12: CMD Pi Group 4 clk 0: le -45 re = 68, cmdLeft = -45 cmdRight = 62 N0.C0: A11: CMD Pi Group 0 clk 0: le -49 re = 68, cmdLeft = -49 cmdRight = 68 N0.C0: BG1: CMD Pi Group 10 clk 0: le -51 re = 64, cmdLeft = -51 cmdRight = 64 N0.C0: ACT_N: CMD Pi Group 5 clk 0: le -49 re = 68, cmdLeft = -49 cmdRight = 68 N0.C0: BG0: CMD Pi Group 10 clk 0: le -49 re = 68, cmdLeft = -49 cmdRight = 64 N0.C0: CS2_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C0: CS3_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C0: C2: CMD Pi Group 5 clk 0: le -511 re = 511, cmdLeft = -49 cmdRight = 68 N0.C0: PAR: CMD Pi Group 9 clk 2: le -47 re = 72, cmdLeft = -47 cmdRight = 72 N0.C0: CAS_N: CMD Pi Group 7 clk 2: le -45 re = 70, cmdLeft = -45 cmdRight = 70 N0.C0: A13: CMD Pi Group 11 clk 2: le -43 re = 72, cmdLeft = -43 cmdRight = 72 N0.C0: RAS_N: CMD Pi Group 1 clk 2: le -45 re = 72, cmdLeft = -45 cmdRight = 72 N0.C0: WE_N: CMD Pi Group 7 clk 2: le -41 re = 72, cmdLeft = -41 cmdRight = 70 N0.C0: A10: CMD Pi Group 1 clk 2: le -47 re = 68, cmdLeft = -45 cmdRight = 68 N0.C0: BA1: CMD Pi Group 11 clk 2: le -43 re = 70, cmdLeft = -43 cmdRight = 70 N0.C0: A0: CMD Pi Group 9 clk 2: le -49 re = 70, cmdLeft = -47 cmdRight = 70 N0.C0: BA0: CMD Pi Group 4 clk 2: le -49 re = 68, cmdLeft = -49 cmdRight = 68 N0.C0: A1: CMD Pi Group 3 clk 2: le -43 re = 74, cmdLeft = -43 cmdRight = 74 N0.C0: A3: CMD Pi Group 8 clk 2: le -43 re = 72, cmdLeft = -43 cmdRight = 72 N0.C0: A2: CMD Pi Group 3 clk 2: le -47 re = 72, cmdLeft = -43 cmdRight = 72 N0.C0: A4: CMD Pi Group 8 clk 2: le -47 re = 68, cmdLeft = -43 cmdRight = 68 N0.C0: A5: CMD Pi Group 2 clk 2: le -45 re = 70, cmdLeft = -45 cmdRight = 70 N0.C0: A6: CMD Pi Group 2 clk 2: le -41 re = 76, cmdLeft = -41 cmdRight = 70 N0.C0: A7: CMD Pi Group 6 clk 2: le -47 re = 68, cmdLeft = -47 cmdRight = 68 N0.C0: A8: CMD Pi Group 6 clk 2: le -45 re = 72, cmdLeft = -45 cmdRight = 68 N0.C0: A9: CMD Pi Group 0 clk 2: le -43 re = 72, cmdLeft = -43 cmdRight = 72 N0.C0: A12: CMD Pi Group 4 clk 2: le -43 re = 74, cmdLeft = -43 cmdRight = 68 N0.C0: A11: CMD Pi Group 0 clk 2: le -45 re = 66, cmdLeft = -43 cmdRight = 66 N0.C0: BG1: CMD Pi Group 10 clk 2: le -47 re = 66, cmdLeft = -47 cmdRight = 66 N0.C0: ACT_N: CMD Pi Group 5 clk 2: le -45 re = 72, cmdLeft = -45 cmdRight = 72 N0.C0: BG0: CMD Pi Group 10 clk 2: le -45 re = 72, cmdLeft = -45 cmdRight = 66 N0.C0: CS2_N: CMD Pi Group 12 clk 2: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C0: CS3_N: CMD Pi Group 12 clk 2: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C0: C2: CMD Pi Group 5 clk 2: le -511 re = 511, cmdLeft = -45 cmdRight = 72 N0.C0: CMD Pi Group 0 clk 0 cmdOffset 9 N0.C0: CMD Pi Group 1 clk 0 cmdOffset 10 N0.C0: CMD Pi Group 2 clk 0 cmdOffset 9 N0.C0: CMD Pi Group 3 clk 0 cmdOffset 10 N0.C0: CMD Pi Group 4 clk 0 cmdOffset 8 N0.C0: CMD Pi Group 5 clk 0 cmdOffset 9 N0.C0: CMD Pi Group 6 clk 0 cmdOffset 7 N0.C0: CMD Pi Group 7 clk 0 cmdOffset 8 N0.C0: CMD Pi Group 8 clk 0 cmdOffset 7 N0.C0: CMD Pi Group 9 clk 0 cmdOffset 5 N0.C0: CMD Pi Group 10 clk 0 cmdOffset 7 N0.C0: CMD Pi Group 11 clk 0 cmdOffset 8 N0.C0: CMD Pi Group 12 clk 0 cmdOffset 0 N0.C0: CMD Pi Group 13 clk 0 cmdOffset 0 N0.C0: CMD Pi Group 14 clk 0 cmdOffset 0 N0.C0: CMD Pi Group 0 clk 2 cmdOffset 11 N0.C0: CMD Pi Group 1 clk 2 cmdOffset 11 N0.C0: CMD Pi Group 2 clk 2 cmdOffset 14 N0.C0: CMD Pi Group 3 clk 2 cmdOffset 14 N0.C0: CMD Pi Group 4 clk 2 cmdOffset 12 N0.C0: CMD Pi Group 5 clk 2 cmdOffset 13 N0.C0: CMD Pi Group 6 clk 2 cmdOffset 11 N0.C0: CMD Pi Group 7 clk 2 cmdOffset 14 N0.C0: CMD Pi Group 8 clk 2 cmdOffset 12 N0.C0: CMD Pi Group 9 clk 2 cmdOffset 11 N0.C0: CMD Pi Group 10 clk 2 cmdOffset 10 N0.C0: CMD Pi Group 11 clk 2 cmdOffset 13 N0.C0: CMD Pi Group 12 clk 2 cmdOffset 0 N0.C0: CMD Pi Group 13 clk 2 cmdOffset 0 N0.C0: CMD Pi Group 14 clk 2 cmdOffset 0 N0.C0: CMD Pi Group 0: maxOffset = 11, minOffset = 9, cmdOffset = 10 N0.C0: CMD Pi Group 1: maxOffset = 11, minOffset = 10, cmdOffset = 10 N0.C0: CMD Pi Group 2: maxOffset = 14, minOffset = 9, cmdOffset = 11 N0.C0: CMD Pi Group 3: maxOffset = 14, minOffset = 10, cmdOffset = 12 N0.C0: CMD Pi Group 4: maxOffset = 12, minOffset = 8, cmdOffset = 10 N0.C0: CMD Pi Group 5: maxOffset = 13, minOffset = 9, cmdOffset = 11 N0.C0: CMD Pi Group 6: maxOffset = 11, minOffset = 7, cmdOffset = 9 N0.C0: CMD Pi Group 7: maxOffset = 14, minOffset = 8, cmdOffset = 11 N0.C0: CMD Pi Group 8: maxOffset = 12, minOffset = 7, cmdOffset = 9 N0.C0: CMD Pi Group 9: maxOffset = 11, minOffset = 5, cmdOffset = 8 N0.C0: CMD Pi Group 10: maxOffset = 10, minOffset = 7, cmdOffset = 8 N0.C0: CMD Pi Group 11: maxOffset = 13, minOffset = 8, cmdOffset = 10 N0.C0: CMD Pi Group 0: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C0: CMD Pi Group 1: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C0: CMD Pi Group 2: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C0: <--CMD Pi Group 0 clk 0: cmdLeft -59 - cmdRight 58 N0.C0: <--CMD Pi Group 0 clk 2: cmdLeft -53 - cmdRight 56 N0.C0: <--CMD Pi Group 1 clk 0: cmdLeft -55 - cmdRight 56 N0.C0: <--CMD Pi Group 1 clk 2: cmdLeft -55 - cmdRight 58 N0.C0: <--CMD Pi Group 2 clk 0: cmdLeft -58 - cmdRight 55 N0.C0: <--CMD Pi Group 2 clk 2: cmdLeft -52 - cmdRight 59 N0.C0: <--CMD Pi Group 3 clk 0: cmdLeft -59 - cmdRight 56 N0.C0: <--CMD Pi Group 3 clk 2: cmdLeft -55 - cmdRight 60 N0.C0: <--CMD Pi Group 4 clk 0: cmdLeft -55 - cmdRight 52 N0.C0: <--CMD Pi Group 4 clk 2: cmdLeft -53 - cmdRight 58 N0.C0: <--CMD Pi Group 5 clk 0: cmdLeft -60 - cmdRight 57 N0.C0: <--CMD Pi Group 5 clk 2: cmdLeft -56 - cmdRight 61 N0.C0: <--CMD Pi Group 6 clk 0: cmdLeft -56 - cmdRight 53 N0.C0: <--CMD Pi Group 6 clk 2: cmdLeft -54 - cmdRight 59 N0.C0: <--CMD Pi Group 7 clk 0: cmdLeft -58 - cmdRight 53 N0.C0: <--CMD Pi Group 7 clk 2: cmdLeft -52 - cmdRight 59 N0.C0: <--CMD Pi Group 8 clk 0: cmdLeft -60 - cmdRight 57 N0.C0: <--CMD Pi Group 8 clk 2: cmdLeft -52 - cmdRight 59 N0.C0: <--CMD Pi Group 9 clk 0: cmdLeft -61 - cmdRight 56 N0.C0: <--CMD Pi Group 9 clk 2: cmdLeft -55 - cmdRight 62 N0.C0: <--CMD Pi Group 10 clk 0: cmdLeft -57 - cmdRight 56 N0.C0: <--CMD Pi Group 10 clk 2: cmdLeft -53 - cmdRight 58 N0.C0: <--CMD Pi Group 11 clk 0: cmdLeft -59 - cmdRight 56 N0.C0: <--CMD Pi Group 11 clk 2: cmdLeft -53 - cmdRight 60 N0.C0: <--CMD Pi Group 12 clk 0: cmdLeft -255 - cmdRight 255 N0.C0: <--CMD Pi Group 12 clk 2: cmdLeft -255 - cmdRight 255 N0.C0: <--CMD Pi Group 13 clk 0: cmdLeft -255 - cmdRight 255 N0.C0: <--CMD Pi Group 13 clk 2: cmdLeft -255 - cmdRight 255 N0.C0: <--CMD Pi Group 14 clk 0: cmdLeft -255 - cmdRight 255 N0.C0: <--CMD Pi Group 14 clk 2: cmdLeft -255 - cmdRight 255 N0.C0: <----clk 0 ckOffset 1: -(maxLeftOffset:-55 + minRightOffset:52) / 2 N0.C0: <----clk 2 ckOffset -2: -(maxLeftOffset:-52 + minRightOffset:56) / 2 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C0: 113 114 113 112 112 111 113 115 114 114 111 113 START_DATA_CLK 0 1 2 3 N0.C0: 1 0 126 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C0: 129 124 108 108 108 108 108 108 108 108 129 124 108 108 108 108 129 124 129 108 108 Entering no zone 8 Early CMD/CLK - 2611ms Lrdimm BS Phase RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x14, 0x0000 Entering no zone 9 Lrdimm BS Phase RX - 0ms Lrdimm BS Cycle RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x15, 0x0000 Entering no zone 10 Lrdimm BS Cycle RX - 0ms Lrdimm BS Delay RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x16, 0x0000 Entering no zone 11 Lrdimm BS Delay RX - 0ms Receive Enable -- Started Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Receive Enable Pi S0, Ch0, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 2 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 3 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 4 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 5 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 6 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 7 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 8 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 9 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 10 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 11 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 12 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 13 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 14 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 1 0 15 1 1 0 1 0 1 0 0 0 1 1 1 1 0 1 0 0 0 16 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 17 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 18 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 19 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 20 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 21 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 22 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 23 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 24 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 25 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 26 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 27 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 28 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 29 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 30 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 31 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 32 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 33 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 34 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 35 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 36 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 37 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 38 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 39 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 40 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 41 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 42 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 43 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 44 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 45 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 46 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 47 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 48 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 49 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 50 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 51 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 52 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 53 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 54 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 55 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 56 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 57 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 58 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 59 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 60 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 61 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 62 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 63 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 64 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 65 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 66 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 67 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 68 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 69 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 70 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 71 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 72 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 73 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 74 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 75 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 76 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 77 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 78 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 79 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 80 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 81 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 82 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 83 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 84 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 85 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 86 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 87 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 88 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 89 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 90 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 91 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 92 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 93 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 94 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 95 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 96 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 97 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 98 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 99 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 100 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 101 1 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 102 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 103 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 104 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 105 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 106 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 107 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 108 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 109 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 110 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 111 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 112 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 113 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 114 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 115 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 116 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 117 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 118 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 119 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 120 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 121 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 122 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 123 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 124 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 125 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 126 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 127 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 ---------------------------------------------------------------------------- RE: 101 119 77 2 37 96 60 85 20 110 127 88 11 45 103 69 93 26 CP: 2 20 107 33 65 121 88 111 47 11 28 116 41 73 1 97 118 54 FE: 32 49 9 64 93 19 117 10 74 41 57 16 71 102 28 125 15 82 PW: 59 58 60 62 56 51 57 53 54 59 58 56 60 57 53 56 50 56 N0.C0.D0.R0.S00: Rec En Delay 2 N0.C0.D0.R0.S01: Rec En Delay 20 N0.C0.D0.R0.S02: Rec En Delay 107 N0.C0.D0.R0.S03: Rec En Delay 33 N0.C0.D0.R0.S04: Rec En Delay 65 N0.C0.D0.R0.S05: Rec En Delay 121 N0.C0.D0.R0.S06: Rec En Delay 88 N0.C0.D0.R0.S07: Rec En Delay 111 N0.C0.D0.R0.S08: Rec En Delay 47 N0.C0.D0.R0.S09: Rec En Delay 11 N0.C0.D0.R0.S10: Rec En Delay 28 N0.C0.D0.R0.S11: Rec En Delay 116 N0.C0.D0.R0.S12: Rec En Delay 41 N0.C0.D0.R0.S13: Rec En Delay 73 N0.C0.D0.R0.S14: Rec En Delay 1 N0.C0.D0.R0.S15: Rec En Delay 97 N0.C0.D0.R0.S16: Rec En Delay 118 N0.C0.D0.R0.S17: Rec En Delay 54 N0.C0.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 57 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 55 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 53 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 51 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 49 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 47 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 45 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 43 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 41 N0.C0.D0.R0: Round trip latency: No zeros found Round trip latency = 39 N0.C0.D0.R0: IO Latency = 6 zeroFlag = 0x4000, allZeros[0] = 0x3FFFF N0.C0.D0.R0.S14: Rec En Delay = 129 N0.C0.D0.R0: IO Latency = 8 zeroFlag = 0x3F7FB, allZeros[0] = 0x3FFFF N0.C0.D0.R0.S00: Rec En Delay = 130 N0.C0.D0.R0.S01: Rec En Delay = 148 N0.C0.D0.R0.S03: Rec En Delay = 161 N0.C0.D0.R0.S04: Rec En Delay = 193 N0.C0.D0.R0.S05: Rec En Delay = 249 N0.C0.D0.R0.S06: Rec En Delay = 216 N0.C0.D0.R0.S07: Rec En Delay = 239 N0.C0.D0.R0.S08: Rec En Delay = 175 N0.C0.D0.R0.S09: Rec En Delay = 139 N0.C0.D0.R0.S10: Rec En Delay = 156 N0.C0.D0.R0.S12: Rec En Delay = 169 N0.C0.D0.R0.S13: Rec En Delay = 201 N0.C0.D0.R0.S14: Rec En Delay = 257 N0.C0.D0.R0.S15: Rec En Delay = 225 N0.C0.D0.R0.S16: Rec En Delay = 246 N0.C0.D0.R0.S17: Rec En Delay = 182 N0.C0.D0.R0: Round trip latency: Found all zeros Receive Enable Summary ------------------------ START_DATA_REC_EN_BASIC N0.C0.D0.R0.S00: Pi setting = 162 N0.C0.D0.R0.S01: Pi setting = 180 N0.C0.D0.R0.S02: Pi setting = 139 N0.C0.D0.R0.S03: Pi setting = 193 N0.C0.D0.R0.S04: Pi setting = 225 N0.C0.D0.R0.S05: Pi setting = 281 N0.C0.D0.R0.S06: Pi setting = 248 N0.C0.D0.R0.S07: Pi setting = 271 N0.C0.D0.R0.S08: Pi setting = 207 N0.C0.D0.R0.S09: Pi setting = 171 N0.C0.D0.R0.S10: Pi setting = 188 N0.C0.D0.R0.S11: Pi setting = 148 N0.C0.D0.R0.S12: Pi setting = 201 N0.C0.D0.R0.S13: Pi setting = 233 N0.C0.D0.R0.S14: Pi setting = 289 N0.C0.D0.R0.S15: Pi setting = 257 N0.C0.D0.R0.S16: Pi setting = 278 N0.C0.D0.R0.S17: Pi setting = 214 N0.C0.D0.R0: IO Latency = 8 N0.C0.D0.R0: Round Trip = 39 STOP_DATA_REC_EN_BASIC N0.D0.R1: RecEn Pi Scanning: Summary: Receive Enable Pi S0, Ch0, DIMM0, Rank1 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 2 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 3 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 4 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 5 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 6 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 7 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 8 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 9 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 10 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 11 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 12 1 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 13 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 14 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 15 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 16 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 17 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 18 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 19 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 20 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 21 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 22 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 0 23 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 24 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 25 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 26 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 27 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 28 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 29 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 30 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 31 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 32 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 33 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 34 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 35 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 36 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 37 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 38 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 39 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 40 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 41 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 42 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 43 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 44 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 45 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 46 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 47 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 48 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 49 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 50 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 51 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 52 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 53 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 54 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 55 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 56 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 57 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 58 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 59 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 60 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 61 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 62 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 63 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 64 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 65 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 66 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 67 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 68 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 69 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 70 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 71 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 72 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 73 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 74 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 75 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 76 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 77 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 78 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 79 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 80 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 81 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 82 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 83 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 84 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 85 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 86 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 87 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 88 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 1 89 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 90 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 91 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 92 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 93 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 94 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 95 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 96 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 97 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 98 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 99 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 100 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 101 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 102 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 103 0 0 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 104 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 105 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 106 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 107 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 108 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 109 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 110 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 111 1 0 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 112 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 113 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 114 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 115 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 116 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 117 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 118 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 119 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 120 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 121 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 122 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 1 1 0 123 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 124 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 125 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 126 1 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 127 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 ---------------------------------------------------------------------------- RE: 104 0 81 11 40 99 67 88 23 112 9 91 21 48 104 72 95 31 CP: 4 29 110 41 69 126 95 114 52 11 38 119 50 76 4 101 123 60 FE: 32 59 12 71 98 25 123 13 81 39 67 20 79 105 33 3 23 89 PW: 56 59 59 60 58 54 56 53 58 55 58 57 58 57 57 59 56 58 N0.C0.D0.R1.S00: Rec En Delay 4 N0.C0.D0.R1.S01: Rec En Delay 29 N0.C0.D0.R1.S02: Rec En Delay 110 N0.C0.D0.R1.S03: Rec En Delay 41 N0.C0.D0.R1.S04: Rec En Delay 69 N0.C0.D0.R1.S05: Rec En Delay 126 N0.C0.D0.R1.S06: Rec En Delay 95 N0.C0.D0.R1.S07: Rec En Delay 114 N0.C0.D0.R1.S08: Rec En Delay 52 N0.C0.D0.R1.S09: Rec En Delay 11 N0.C0.D0.R1.S10: Rec En Delay 38 N0.C0.D0.R1.S11: Rec En Delay 119 N0.C0.D0.R1.S12: Rec En Delay 50 N0.C0.D0.R1.S13: Rec En Delay 76 N0.C0.D0.R1.S14: Rec En Delay 4 N0.C0.D0.R1.S15: Rec En Delay 101 N0.C0.D0.R1.S16: Rec En Delay 123 N0.C0.D0.R1.S17: Rec En Delay 60 N0.C0.D0.R1: Round trip latency = 73 IO latency = 4 N0.D0.R1: Round trip latency N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 71 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 69 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 67 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 65 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 63 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 61 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 59 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 57 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 55 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 53 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 51 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 49 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 47 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 45 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 43 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 41 N0.C0.D0.R1: Round trip latency: No zeros found Round trip latency = 39 N0.C0.D0.R1: IO Latency = 6 zeroFlag = 0x4000, allZeros[0] = 0x3FFFF N0.C0.D0.R1.S14: Rec En Delay = 132 N0.C0.D0.R1: IO Latency = 8 zeroFlag = 0x3F7FB, allZeros[0] = 0x3FFFF N0.C0.D0.R1.S00: Rec En Delay = 132 N0.C0.D0.R1.S01: Rec En Delay = 157 N0.C0.D0.R1.S03: Rec En Delay = 169 N0.C0.D0.R1.S04: Rec En Delay = 197 N0.C0.D0.R1.S05: Rec En Delay = 254 N0.C0.D0.R1.S06: Rec En Delay = 223 N0.C0.D0.R1.S07: Rec En Delay = 242 N0.C0.D0.R1.S08: Rec En Delay = 180 N0.C0.D0.R1.S09: Rec En Delay = 139 N0.C0.D0.R1.S10: Rec En Delay = 166 N0.C0.D0.R1.S12: Rec En Delay = 178 N0.C0.D0.R1.S13: Rec En Delay = 204 N0.C0.D0.R1.S14: Rec En Delay = 260 N0.C0.D0.R1.S15: Rec En Delay = 229 N0.C0.D0.R1.S16: Rec En Delay = 251 N0.C0.D0.R1.S17: Rec En Delay = 188 N0.C0.D0.R1: Round trip latency: Found all zeros Receive Enable Summary ------------------------ START_DATA_REC_EN_BASIC N0.C0.D0.R1.S00: Pi setting = 164 N0.C0.D0.R1.S01: Pi setting = 189 N0.C0.D0.R1.S02: Pi setting = 142 N0.C0.D0.R1.S03: Pi setting = 201 N0.C0.D0.R1.S04: Pi setting = 229 N0.C0.D0.R1.S05: Pi setting = 286 N0.C0.D0.R1.S06: Pi setting = 255 N0.C0.D0.R1.S07: Pi setting = 274 N0.C0.D0.R1.S08: Pi setting = 212 N0.C0.D0.R1.S09: Pi setting = 171 N0.C0.D0.R1.S10: Pi setting = 198 N0.C0.D0.R1.S11: Pi setting = 151 N0.C0.D0.R1.S12: Pi setting = 210 N0.C0.D0.R1.S13: Pi setting = 236 N0.C0.D0.R1.S14: Pi setting = 292 N0.C0.D0.R1.S15: Pi setting = 261 N0.C0.D0.R1.S16: Pi setting = 283 N0.C0.D0.R1.S17: Pi setting = 220 N0.C0.D0.R1: IO Latency = 8 N0.C0.D0.R1: Round Trip = 39 STOP_DATA_REC_EN_BASIC Entering no zone 12 Receive Enable - 2757ms Rx Dq/Dqs Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000 N0.D0.R0: RxDqDqs Pi Scanning... Read DQ/DQS summary for socket:0 channel:0 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # . # . # # # # # # # # # # # # # # 13 # . # . # # # # # # . # # # # # # # 14 # . # . # . # . # # . # # # # # # # 15 # . # . . . # . # # . # # # # # # # 16 # . # . . . # . . # . # # # . # # # 17 # . . . . . . . . # . # . . . # . # 18 . . . . . . . . . # . # . . . # . . 19 . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . 22 . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . 24 . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . 33 . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . 40 . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . 42 . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . # . . . . . . . . . . . . 69 . . . # # # . . . . . . . . . . . . 70 # . # # # # # . # . . . . . . . . . 71 # . . # # # # # # . . . . . . . . . ---------------------------------------------------------------------------- EE: 18 12 17 12 15 14 17 14 16 19 13 19 17 17 16 19 17 18 PP: 43 41 43 40 41 40 43 42 42 45 42 45 44 44 43 45 44 44 FE: 69 71 69 68 68 67 69 70 69 71 71 71 71 71 71 71 71 71 START_DATA_RX_DQS_BASIC N0.C0.D0.R0.S00: Pi = 43 N0.C0.D0.R0.S01: Pi = 41 N0.C0.D0.R0.S02: Pi = 43 N0.C0.D0.R0.S03: Pi = 40 N0.C0.D0.R0.S04: Pi = 41 N0.C0.D0.R0.S05: Pi = 40 N0.C0.D0.R0.S06: Pi = 43 N0.C0.D0.R0.S07: Pi = 42 N0.C0.D0.R0.S08: Pi = 42 N0.C0.D0.R0.S09: Pi = 45 N0.C0.D0.R0.S10: Pi = 42 N0.C0.D0.R0.S11: Pi = 45 N0.C0.D0.R0.S12: Pi = 44 N0.C0.D0.R0.S13: Pi = 44 N0.C0.D0.R0.S14: Pi = 43 N0.C0.D0.R0.S15: Pi = 45 N0.C0.D0.R0.S16: Pi = 44 N0.C0.D0.R0.S17: Pi = 44 STOP_DATA_RX_DQS_BASIC N0.D0.R1: RxDqDqs Pi Scanning... Read DQ/DQS summary for socket:0 channel:0 dimm:0 rank:1 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # . # # # # # # # # # # # # # # # # 13 # . # . # # # . # # # # # # # # # # 14 # . # . # . # . # # . # # # # # . # 15 # . # . # . # . # # . # # # # # . # 16 # . # . # . # . . # . # # # # # . # 17 . . # . . . # . . # . # . # # # . # 18 . . . . . . # . . # . # . # . # . # 19 . . . . . . . . . . . . . . . # . . 20 . . . . . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . 22 . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . 24 . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . 33 . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . 40 . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . 42 . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . . . . . . . . . . . . . . 69 . . . . . # # . . . . . . . . . . . 70 . . . # . # # . . . . . . . . . . . 71 . . . # . # # . . . . . . . . . . . ---------------------------------------------------------------------------- EE: 17 12 18 13 17 14 19 13 16 19 14 19 17 19 18 20 14 19 PP: 44 41 44 41 44 41 43 42 43 45 42 45 44 45 44 45 42 45 FE: 71 71 71 69 71 68 68 71 71 71 71 71 71 71 71 71 71 71 START_DATA_RX_DQS_BASIC N0.C0.D0.R1.S00: Pi = 44 N0.C0.D0.R1.S01: Pi = 41 N0.C0.D0.R1.S02: Pi = 44 N0.C0.D0.R1.S03: Pi = 41 N0.C0.D0.R1.S04: Pi = 44 N0.C0.D0.R1.S05: Pi = 41 N0.C0.D0.R1.S06: Pi = 43 N0.C0.D0.R1.S07: Pi = 42 N0.C0.D0.R1.S08: Pi = 43 N0.C0.D0.R1.S09: Pi = 45 N0.C0.D0.R1.S10: Pi = 42 N0.C0.D0.R1.S11: Pi = 45 N0.C0.D0.R1.S12: Pi = 44 N0.C0.D0.R1.S13: Pi = 45 N0.C0.D0.R1.S14: Pi = 44 N0.C0.D0.R1.S15: Pi = 45 N0.C0.D0.R1.S16: Pi = 42 N0.C0.D0.R1.S17: Pi = 45 STOP_DATA_RX_DQS_BASIC Entering no zone 13 Rx Dq/Dqs Basic - 1511ms Lrdimm BS Fine WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x17, 0x0000 Entering no zone 14 Lrdimm BS Fine WL - 0ms Lrdimm BS Coarse WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x18, 0x0000 Entering no zone 15 Lrdimm BS Coarse WL - 0ms Lrdimm BS Delay TX -- Started Checkpoint Code: Socket 0, 0xB7, 0x1C, 0x0000 Entering no zone 16 Lrdimm BS Delay TX - 0ms Write Leveling -- Started Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000 N0.C0: ODT Override: 0x1 N0.D0.R0: Write Leveling Pi Scanning... Summary: Write Leveling Pi S0, Ch0, DIMM0, Rank0 --------------------------------------- 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 2 0 0 0 1 1 0 1 0 1 3 0 0 0 1 1 0 1 0 1 4 0 0 0 1 1 0 1 0 1 5 0 0 0 1 1 0 1 0 1 6 0 0 0 1 1 0 1 0 1 7 0 0 0 1 1 0 1 0 1 8 0 0 0 1 1 0 1 0 1 9 0 0 0 1 1 0 1 0 1 10 0 0 0 0 1 0 1 0 1 11 0 0 0 0 1 0 1 0 1 12 0 0 1 0 1 0 1 0 1 13 0 0 1 0 1 0 1 0 1 14 0 0 1 0 1 0 1 0 1 15 0 0 1 0 1 0 1 0 1 16 0 0 1 0 1 0 1 1 1 17 0 0 1 0 1 0 1 1 1 18 0 0 1 0 1 0 1 1 1 19 0 0 1 0 1 0 1 1 1 20 0 0 1 0 1 0 1 1 1 21 0 0 1 0 1 0 1 1 1 22 0 0 1 0 1 0 1 1 1 23 0 0 1 0 1 0 1 1 1 24 0 0 1 0 1 0 1 1 1 25 0 0 1 0 1 0 1 1 1 26 0 0 1 0 1 0 1 1 1 27 0 0 1 0 1 0 1 1 1 28 0 0 1 0 1 0 1 1 1 29 0 0 1 0 1 0 1 1 0 30 1 0 1 0 1 0 1 1 0 31 1 0 1 0 1 0 1 1 0 32 1 0 1 0 1 0 1 1 0 33 1 0 1 0 1 0 1 1 0 34 1 0 1 0 1 0 1 1 0 35 1 0 1 0 1 0 1 1 0 36 1 0 1 0 1 0 1 1 0 37 1 0 1 0 1 0 1 1 0 38 1 0 1 0 1 1 1 1 0 39 1 0 1 0 1 1 1 1 0 40 1 0 1 0 1 1 1 1 0 41 1 0 1 0 1 1 1 1 0 42 1 0 1 0 1 1 1 1 0 43 1 0 1 0 1 1 1 1 0 44 1 0 1 0 1 1 1 1 0 45 1 0 1 0 1 1 1 1 0 46 1 1 1 0 1 1 1 1 0 47 1 1 1 0 0 1 1 1 0 48 1 1 1 0 0 1 1 1 0 49 1 1 1 0 0 1 1 1 0 50 1 1 1 0 0 1 1 1 0 51 1 1 1 0 0 1 1 1 0 52 1 1 1 0 0 1 1 1 0 53 1 1 1 0 0 1 1 1 0 54 1 1 1 0 0 1 1 1 0 55 1 1 1 0 0 1 1 1 0 56 1 1 1 0 0 1 1 1 0 57 1 1 1 0 0 1 1 1 0 58 1 1 1 0 0 1 1 1 0 59 1 1 1 0 0 1 1 1 0 60 1 1 1 0 0 1 1 1 0 61 1 1 1 0 0 1 1 1 0 62 1 1 1 0 0 1 1 1 0 63 1 1 1 0 0 1 1 1 0 64 1 1 1 0 0 1 1 1 0 65 1 1 1 0 0 1 0 1 0 66 1 1 1 0 0 1 0 1 0 67 1 1 1 0 0 1 0 1 0 68 1 1 1 0 0 1 0 1 0 69 1 1 1 0 0 1 0 1 0 70 1 1 1 0 0 1 0 1 0 71 1 1 1 0 0 1 0 1 0 72 1 1 1 0 0 1 0 1 0 73 1 1 1 0 0 1 0 1 0 74 1 1 1 1 0 1 0 1 0 75 1 1 1 1 0 1 0 1 0 76 1 1 0 1 0 1 0 1 0 77 1 1 0 1 0 1 0 1 0 78 1 1 0 1 0 1 0 1 0 79 1 1 0 1 0 1 0 1 0 80 1 1 0 1 0 1 0 1 0 81 1 1 0 1 0 1 0 1 0 82 1 1 0 1 0 1 0 1 0 83 1 1 0 1 0 1 0 0 0 84 1 1 0 1 0 1 0 0 0 85 1 1 0 1 0 1 0 0 0 86 1 1 0 1 0 1 0 0 0 87 1 1 0 1 0 1 0 0 0 88 1 1 0 1 0 1 0 0 0 89 1 1 0 1 0 1 0 0 0 90 1 1 0 1 0 1 0 0 0 91 1 1 0 1 0 1 0 0 0 92 1 1 0 1 0 1 0 0 1 93 1 1 0 1 0 1 0 0 1 94 0 1 0 1 0 1 0 0 1 95 0 1 0 1 0 1 0 0 1 96 0 1 0 1 0 1 0 0 1 97 0 1 0 1 0 1 0 0 1 98 0 1 0 1 0 1 0 0 1 99 0 1 0 1 0 1 0 0 1 100 0 1 0 1 0 1 0 0 1 101 0 1 0 1 0 1 0 0 1 102 0 1 0 1 0 1 0 0 1 103 0 1 0 1 0 0 0 0 1 104 0 1 0 1 0 0 0 0 1 105 0 1 0 1 0 0 0 0 1 106 0 1 0 1 0 0 0 0 1 107 0 1 0 1 0 0 0 0 1 108 0 1 0 1 0 0 0 0 1 109 0 1 0 1 0 0 0 0 1 110 0 0 0 1 1 0 0 0 1 111 0 0 0 1 1 0 0 0 1 112 0 0 0 1 1 0 0 0 1 113 0 0 0 1 1 0 0 0 1 114 0 0 0 1 1 0 0 0 1 115 0 0 0 1 1 0 0 0 1 116 0 0 0 1 1 0 0 0 1 117 0 0 0 1 1 0 0 0 1 118 0 0 0 1 1 0 0 0 1 119 0 0 0 1 1 0 0 0 1 120 0 0 0 1 1 0 0 0 1 121 0 0 0 1 1 0 0 0 1 122 0 0 0 1 1 0 0 0 1 123 0 0 0 1 1 0 0 0 1 124 0 0 0 1 1 0 0 0 1 125 0 0 0 1 1 0 0 0 1 126 0 0 0 1 1 0 0 0 1 127 0 0 0 1 1 0 1 0 1 ---------------------------------------------------------------------------- RE: 94 110 76 138 174 102 191 80 156 CP: 62 78 44 106 14 70 32 49 124 FE: 222 238 204 138 175 231 193 211 157 PW: 64 64 64 64 65 65 66 67 65 START_DATA_WR_LVL_BASIC N0.C0.D0.R0.S00: WrLevel Delay = 94 N0.C0.D0.R0.S01: WrLevel Delay = 110 N0.C0.D0.R0.S02: WrLevel Delay = 76 N0.C0.D0.R0.S03: WrLevel Delay = 138 N0.C0.D0.R0.S04: WrLevel Delay = 174 N0.C0.D0.R0.S05: WrLevel Delay = 102 N0.C0.D0.R0.S06: WrLevel Delay = 191 N0.C0.D0.R0.S07: WrLevel Delay = 80 N0.C0.D0.R0.S08: WrLevel Delay = 156 STOP_DATA_WR_LVL_BASIC N0.C0: ODT Override: 0x2 N0.D0.R1: Write Leveling Pi Scanning... Summary: Write Leveling Pi S0, Ch0, DIMM0, Rank1 --------------------------------------- 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 2 0 0 0 1 1 0 1 0 1 3 0 0 0 1 1 0 1 0 1 4 0 0 0 1 1 0 1 0 1 5 0 0 0 1 1 0 1 0 1 6 0 0 0 1 1 0 1 0 1 7 0 0 0 1 1 0 1 0 1 8 0 0 0 1 1 0 1 0 1 9 0 0 0 1 1 0 1 0 1 10 0 0 0 1 1 0 1 0 1 11 0 0 0 1 1 0 1 0 1 12 0 0 0 0 1 0 1 0 1 13 0 0 0 0 1 0 1 0 1 14 0 0 0 0 1 0 1 0 1 15 0 0 0 0 1 0 1 0 1 16 0 0 1 0 1 0 1 0 1 17 0 0 1 0 1 0 1 0 1 18 0 0 1 0 1 0 1 0 1 19 0 0 1 0 1 0 1 0 1 20 0 0 1 0 1 0 1 1 1 21 0 0 1 0 1 0 1 1 1 22 0 0 1 0 1 0 1 1 1 23 0 0 1 0 1 0 1 1 1 24 0 0 1 0 1 0 1 1 1 25 0 0 1 0 1 0 1 1 1 26 0 0 1 0 1 0 1 1 1 27 0 0 1 0 1 0 1 1 1 28 0 0 1 0 1 0 1 1 1 29 0 0 1 0 1 0 1 1 1 30 0 0 1 0 1 0 1 1 1 31 0 0 1 0 1 0 1 1 0 32 1 0 1 0 1 0 1 1 0 33 1 0 1 0 1 0 1 1 0 34 1 0 1 0 1 0 1 1 0 35 1 0 1 0 1 0 1 1 0 36 1 0 1 0 1 0 1 1 0 37 1 0 1 0 1 0 1 1 0 38 1 0 1 0 1 0 1 1 0 39 1 0 1 0 1 1 1 1 0 40 1 0 1 0 1 1 1 1 0 41 1 0 1 0 1 1 1 1 0 42 1 0 1 0 1 1 1 1 0 43 1 0 1 0 1 1 1 1 0 44 1 0 1 0 1 1 1 1 0 45 1 0 1 0 1 1 1 1 0 46 1 0 1 0 1 1 1 1 0 47 1 0 1 0 1 1 1 1 0 48 1 0 1 0 1 1 1 1 0 49 1 0 1 0 0 1 1 1 0 50 1 1 1 0 0 1 1 1 0 51 1 1 1 0 0 1 1 1 0 52 1 1 1 0 0 1 1 1 0 53 1 1 1 0 0 1 1 1 0 54 1 1 1 0 0 1 1 1 0 55 1 1 1 0 0 1 1 1 0 56 1 1 1 0 0 1 1 1 0 57 1 1 1 0 0 1 1 1 0 58 1 1 1 0 0 1 1 1 0 59 1 1 1 0 0 1 1 1 0 60 1 1 1 0 0 1 1 1 0 61 1 1 1 0 0 1 1 1 0 62 1 1 1 0 0 1 1 1 0 63 1 1 1 0 0 1 1 1 0 64 1 1 1 0 0 1 1 1 0 65 1 1 1 0 0 1 1 1 0 66 1 1 1 0 0 1 0 1 0 67 1 1 1 0 0 1 0 1 0 68 1 1 1 0 0 1 0 1 0 69 1 1 1 0 0 1 0 1 0 70 1 1 1 0 0 1 0 1 0 71 1 1 1 0 0 1 0 1 0 72 1 1 1 0 0 1 0 1 0 73 1 1 1 0 0 1 0 1 0 74 1 1 1 0 0 1 0 1 0 75 1 1 1 0 0 1 0 1 0 76 1 1 1 1 0 1 0 1 0 77 1 1 1 1 0 1 0 1 0 78 1 1 1 1 0 1 0 1 0 79 1 1 1 1 0 1 0 1 0 80 1 1 1 1 0 1 0 1 0 81 1 1 1 1 0 1 0 1 0 82 1 1 0 1 0 1 0 1 0 83 1 1 0 1 0 1 0 1 0 84 1 1 0 1 0 1 0 1 0 85 1 1 0 1 0 1 0 1 0 86 1 1 0 1 0 1 0 0 0 87 1 1 0 1 0 1 0 0 0 88 1 1 0 1 0 1 0 0 0 89 1 1 0 1 0 1 0 0 0 90 1 1 0 1 0 1 0 0 0 91 1 1 0 1 0 1 0 0 0 92 1 1 0 1 0 1 0 0 0 93 1 1 0 1 0 1 0 0 0 94 1 1 0 1 0 1 0 0 1 95 1 1 0 1 0 1 0 0 1 96 0 1 0 1 0 1 0 0 1 97 0 1 0 1 0 1 0 0 1 98 0 1 0 1 0 1 0 0 1 99 0 1 0 1 0 1 0 0 1 100 0 1 0 1 0 1 0 0 1 101 0 1 0 1 0 1 0 0 1 102 0 1 0 1 0 1 0 0 1 103 0 1 0 1 0 1 0 0 1 104 0 1 0 1 0 0 0 0 1 105 0 1 0 1 0 0 0 0 1 106 0 1 0 1 0 0 0 0 1 107 0 1 0 1 0 0 0 0 1 108 0 1 0 1 0 0 0 0 1 109 0 1 0 1 0 0 0 0 1 110 0 1 0 1 0 0 0 0 1 111 0 1 0 1 0 0 0 0 1 112 0 1 0 1 0 0 0 0 1 113 0 1 0 1 1 0 0 0 1 114 0 1 0 1 1 0 0 0 1 115 0 0 0 1 1 0 0 0 1 116 0 0 0 1 1 0 0 0 1 117 0 0 0 1 1 0 0 0 1 118 0 0 0 1 1 0 0 0 1 119 0 0 0 1 1 0 0 0 1 120 0 0 0 1 1 0 0 0 1 121 0 0 0 1 1 0 0 0 1 122 0 0 0 1 1 0 0 0 1 123 0 0 0 1 1 0 0 0 1 124 0 0 0 1 1 0 0 0 1 125 0 0 0 1 1 0 0 0 1 126 0 0 0 1 1 0 0 0 1 127 0 0 0 1 1 0 0 0 1 ---------------------------------------------------------------------------- RE: 96 114 80 140 177 103 64 84 158 CP: 64 82 49 108 17 71 33 53 126 FE: 224 243 210 140 177 232 194 214 159 PW: 64 65 66 64 64 65 66 66 65 START_DATA_WR_LVL_BASIC N0.C0.D0.R1.S00: WrLevel Delay = 96 N0.C0.D0.R1.S01: WrLevel Delay = 114 N0.C0.D0.R1.S02: WrLevel Delay = 80 N0.C0.D0.R1.S03: WrLevel Delay = 140 N0.C0.D0.R1.S04: WrLevel Delay = 177 N0.C0.D0.R1.S05: WrLevel Delay = 103 N0.C0.D0.R1.S06: WrLevel Delay = 64 N0.C0.D0.R1.S07: WrLevel Delay = 84 N0.C0.D0.R1.S08: WrLevel Delay = 158 STOP_DATA_WR_LVL_BASIC Entering no zone 17 Write Leveling - 1212ms Write Fly By -- Started Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000 N0.D0.R0: Current DQS offset delay is -1 DClks (DQS offset index=0) N0.C0.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 4 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R0: -1 0 0 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 -4 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 4 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 -8 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 8 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 -12 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 12 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 -20 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 20 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 -40 NO 0x001FF 0x00000 N0.C0.D0.R0: -1 0 40 NO 0x001FF 0x00000 N0.D0.R0: Current DQS offset delay is 0 DClks (DQS offset index=1) N0.C0.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 0 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R0: 0 1 0 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 -4 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 4 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 -8 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 8 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 -12 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 12 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 -20 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 20 NO 0x000A0 0x0015F N0.C0.D0.R0: 0 1 -40 NO 0x001FF 0x0015F N0.C0.D0.R0: 0 1 40 NO 0x001FF 0x0015F N0.D0.R0: Current DQS offset delay is 1 DClks (DQS offset index=2) N0.C0.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 1 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R0: 1 2 0 NO 0x0015F 0x001FF N0.D0.R1: Current DQS offset delay is -1 DClks (DQS offset index=0) N0.C0.D0.R1: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 4 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R1: -1 0 0 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 -4 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 4 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 -8 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 8 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 -12 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 12 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 -20 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 20 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 -40 NO 0x001FF 0x00000 N0.C0.D0.R1: -1 0 40 NO 0x001FF 0x00000 N0.D0.R1: Current DQS offset delay is 0 DClks (DQS offset index=1) N0.C0.D0.R1: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 0 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R1: 0 1 0 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 -4 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 4 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 -8 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 8 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 -12 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 12 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 -20 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 20 NO 0x000E0 0x0011F N0.C0.D0.R1: 0 1 -40 NO 0x001FF 0x0011F N0.C0.D0.R1: 0 1 40 NO 0x001FF 0x0011F N0.D0.R1: Current DQS offset delay is 1 DClks (DQS offset index=2) N0.C0.D0.R1: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 1 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C0.D0.R1: 1 2 0 NO 0x0011F 0x001FF -------------------------------------------------------------------------------- N0.C0.D0.R0: Current values: GlobalByteOff = 0 DClks, CRAddDelay[0] = 0 DClks N0.C0.D0.R0: Refining TargetOffset for all byte lanes... TgtOffset ByteOff -------------------------------------------------------------------------------- N0.C0.D0.R0.S00: 0 DClks 0 DClks N0.C0.D0.R0.S01: 0 DClks 0 DClks N0.C0.D0.R0.S02: 0 DClks 0 DClks N0.C0.D0.R0.S03: 0 DClks 0 DClks N0.C0.D0.R0.S04: 0 DClks 0 DClks N0.C0.D0.R0.S05: 0 DClks 1 DClks N0.C0.D0.R0.S06: 0 DClks 0 DClks N0.C0.D0.R0.S07: 0 DClks 1 DClks N0.C0.D0.R0.S08: 0 DClks 0 DClks -------------------------------------------------------------------------------- N0.C0.D0.R1: Current values: GlobalByteOff = 0 DClks, CRAddDelay[0] = 0 DClks N0.C0.D0.R1: Refining TargetOffset for all byte lanes... TgtOffset ByteOff -------------------------------------------------------------------------------- N0.C0.D0.R1.S00: 0 DClks 0 DClks N0.C0.D0.R1.S01: 0 DClks 0 DClks N0.C0.D0.R1.S02: 0 DClks 0 DClks N0.C0.D0.R1.S03: 0 DClks 0 DClks N0.C0.D0.R1.S04: 0 DClks 0 DClks N0.C0.D0.R1.S05: 0 DClks 1 DClks N0.C0.D0.R1.S06: 0 DClks 1 DClks N0.C0.D0.R1.S07: 0 DClks 1 DClks N0.C0.D0.R1.S08: 0 DClks 0 DClks TxDq (PI) TxDqs (PI) PI Offset -------------------------------------------------------------------------------- N0.C0.D0.R0.S00: 126 94 0 N0.C0.D0.R0.S01: 142 110 0 N0.C0.D0.R0.S02: 108 76 0 N0.C0.D0.R0.S03: 170 138 0 N0.C0.D0.R0.S04: 206 174 0 N0.C0.D0.R0.S05: 262 230 128 N0.C0.D0.R0.S06: 223 191 0 N0.C0.D0.R0.S07: 240 208 128 N0.C0.D0.R0.S08: 188 156 0 TxDq (PI) TxDqs (PI) PI Offset -------------------------------------------------------------------------------- N0.C0.D0.R1.S00: 128 96 0 N0.C0.D0.R1.S01: 146 114 0 N0.C0.D0.R1.S02: 112 80 0 N0.C0.D0.R1.S03: 172 140 0 N0.C0.D0.R1.S04: 209 177 0 N0.C0.D0.R1.S05: 263 231 128 N0.C0.D0.R1.S06: 224 192 128 N0.C0.D0.R1.S07: 244 212 128 N0.C0.D0.R1.S08: 190 158 0 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0: t_cwl_adj = 0 N0.C0.D0.R0: 94 110 76 138 174 230 191 208 156 N0.C0.D0.R1: 96 114 80 140 177 231 192 212 158 Entering no zone 18 Write Fly By - 645ms Tx Dq Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000 N0.D0.R0: TxDqDqs Pi Scanning... Write DQ/DQS summary for socket:0 channel:0 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # # # # # # # # # # # # # # # # # # 13 # # # # # # # # # # # # # # # # # # 14 # # # # # # # # # # # # # # # # # # 15 # # # # # # # # # # # # # # # # # # 16 # # # # # # # # # # # # # # # # # # 17 # # # # # # # # # # # # # # # # # # 18 # # # # # # # # # # # # # # # # # # 19 # # # # # # # # # # # # # # # # # # 20 # # # # # # # # # # # # # # # # # # 21 # # # # # # # # # # # # # # # # # # 22 # # # # # # # # # # # # # # # # # # 23 # # # # # # # # # # # # # # # # # # 24 # # # # # # # # # # # # # # # # # # 25 # # # # # # # # # # # # # # # # # # 26 # # # # # # # # # # # # # # # # # # 27 # # # # # # # # # # # # # # # # # # 28 # # # # # # # # # # # # # # # # # # 29 # # # # # # # # # # # # # # # # # # 30 # # # # # # # # # # # # # # # # # # 31 # # # # # # # # # # # # # # # # # # 32 # # # # # # # # # # # # # # # # # # 33 # # # # # # # # # # # # # # # # # # 34 # # # # # # # # # # # # # # # # # # 35 # # # # # # # # # # # # # # # # # # 36 # # # # # # # # # # # # # # # # # # 37 . # # # # # . # # # # # # # # # # # 38 . # . # # # . # . # # # # # # # # # 39 . # . . # # . # . # # # # # # . # # 40 . # . . . . . # . # # # # # # . # # 41 . # . . . . . # . # # # # # . . # . 42 . # . . . . . . . . # # # . . . # . 43 . # . . . . . . . . # . . . . . # . 44 . # . . . . . . . . # . . . . . . . 45 . . . . . . . . . . # . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . 70 . . . . . . . . . . . . . . . . . . 71 . . . . . . . . . . . . . . . . . . 72 . . . . . . . . . . . . . . . . . . 73 . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . 75 . . . . . . . . . . . . . . . . . . 76 . . . . . . . . . . . . . . . . . . 77 . . . . . . . . . . . . . . . . . . 78 . . . . . . . . . . . . . . . . . . 79 . . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . 81 . . . . . . . . . . . . . . . . . . 82 . . . . . . . . . . . . . . . . . . 83 . . . . . . . . . . . . . . . . . . 84 . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . . . . . . . . . 86 . . . . . . . . . . . . . . . . . . 87 . . . . . . . . . . . . . . . . . . 88 . . . . . . . . . . . . . . . . . . 89 . . . . . . . . . . . . . . . . . . 90 . . . . . . . . . . . . . . . . . . 91 . . . . . . . . . . . . . . . . . . 92 . . . . . . . . . . . . . . . . . . 93 . . . . . # . . # . . . . . . . . . 94 . . . . . # . # # . . . . . . . . . 95 # . . . . # . # # . . . . . . . . . 96 # . # # # # # # # . . . . . . . . . 97 # . # # # # # # # # . . . . . . . . 98 # . # # # # # # # # . . . # # . . # 99 # # # # # # # # # # . # . # # . . # 100 # # # # # # # # # # . # # # # # . # 101 # # # # # # # # # # . # # # # # # # 102 # # # # # # # # # # # # # # # # # # 103 # # # # # # # # # # # # # # # # # # 104 # # # # # # # # # # # # # # # # # # 105 # # # # # # # # # # # # # # # # # # 106 # # # # # # # # # # # # # # # # # # 107 # # # # # # # # # # # # # # # # # # 108 # # # # # # # # # # # # # # # # # # 109 # # # # # # # # # # # # # # # # # # 110 # # # # # # # # # # # # # # # # # # 111 # # # # # # # # # # # # # # # # # # 112 # # # # # # # # # # # # # # # # # # 113 # # # # # # # # # # # # # # # # # # 114 # # # # # # # # # # # # # # # # # # 115 # # # # # # # # # # # # # # # # # # 116 # # # # # # # # # # # # # # # # # # 117 # # # # # # # # # # # # # # # # # # 118 # # # # # # # # # # # # # # # # # # 119 # # # # # # # # # # # # # # # # # # 120 # # # # # # # # # # # # # # # # # # 121 # # # # # # # # # # # # # # # # # # 122 # # # # # # # # # # # # # # # # # # 123 # # # # # # # # # # # # # # # # # # 124 # # # # # # # # # # # # # # # # # # 125 # # # # # # # # # # # # # # # # # # 126 # # # # # # # # # # # # # # # # # # 127 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 61 85 44 107 144 200 158 180 124 66 86 49 111 146 201 160 182 127 PP: 89 111 72 135 171 226 187 205 151 93 113 76 139 173 229 190 210 155 FE: 118 138 101 163 199 252 216 231 178 120 141 104 167 201 257 220 238 183 START_DATA_TX_DQ_BASIC N0.C0.D0.R0.S00: TxDqDqs: Pi = 89 N0.C0.D0.R0.S01: TxDqDqs: Pi = 111 N0.C0.D0.R0.S02: TxDqDqs: Pi = 72 N0.C0.D0.R0.S03: TxDqDqs: Pi = 135 N0.C0.D0.R0.S04: TxDqDqs: Pi = 171 N0.C0.D0.R0.S05: TxDqDqs: Pi = 226 N0.C0.D0.R0.S06: TxDqDqs: Pi = 187 N0.C0.D0.R0.S07: TxDqDqs: Pi = 205 N0.C0.D0.R0.S08: TxDqDqs: Pi = 151 N0.C0.D0.R0.S09: TxDqDqs: Pi = 93 N0.C0.D0.R0.S10: TxDqDqs: Pi = 113 N0.C0.D0.R0.S11: TxDqDqs: Pi = 76 N0.C0.D0.R0.S12: TxDqDqs: Pi = 139 N0.C0.D0.R0.S13: TxDqDqs: Pi = 173 N0.C0.D0.R0.S14: TxDqDqs: Pi = 229 N0.C0.D0.R0.S15: TxDqDqs: Pi = 190 N0.C0.D0.R0.S16: TxDqDqs: Pi = 210 N0.C0.D0.R0.S17: TxDqDqs: Pi = 155 STOP_DATA_TX_DQ_BASIC N0.D0.R1: TxDqDqs Pi Scanning... Write DQ/DQS summary for socket:0 channel:0 dimm:0 rank:1 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # # # # # # # # # # # # # # # # # # 13 # # # # # # # # # # # # # # # # # # 14 # # # # # # # # # # # # # # # # # # 15 # # # # # # # # # # # # # # # # # # 16 # # # # # # # # # # # # # # # # # # 17 # # # # # # # # # # # # # # # # # # 18 # # # # # # # # # # # # # # # # # # 19 # # # # # # # # # # # # # # # # # # 20 # # # # # # # # # # # # # # # # # # 21 # # # # # # # # # # # # # # # # # # 22 # # # # # # # # # # # # # # # # # # 23 # # # # # # # # # # # # # # # # # # 24 # # # # # # # # # # # # # # # # # # 25 # # # # # # # # # # # # # # # # # # 26 # # # # # # # # # # # # # # # # # # 27 # # # # # # # # # # # # # # # # # # 28 # # # # # # # # # # # # # # # # # # 29 # # # # # # # # # # # # # # # # # # 30 # # # # # # # # # # # # # # # # # # 31 # # # # # # # # # # # # # # # # # # 32 # # # # # # # # # # # # # # # # # # 33 # # # # # # # # # # # # # # # # # # 34 # # # # # # # # # # # # # # # # # # 35 # # # # # # # # # # # # # # # # # # 36 # # . # # # . # # # # # # # # # # # 37 # # . # # # . # # # # # # # # # # # 38 . # . # . # . # # # # # # # # . # # 39 . # . . . # . # # # # # # # # . # # 40 . # . . . . . # # # # # # . # . # # 41 . # . . . . . . . # # # # . # . # . 42 . . . . . . . . . . # . # . . . # . 43 . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . 70 . . . . . . . . . . . . . . . . . . 71 . . . . . . . . . . . . . . . . . . 72 . . . . . . . . . . . . . . . . . . 73 . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . 75 . . . . . . . . . . . . . . . . . . 76 . . . . . . . . . . . . . . . . . . 77 . . . . . . . . . . . . . . . . . . 78 . . . . . . . . . . . . . . . . . . 79 . . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . 81 . . . . . . . . . . . . . . . . . . 82 . . . . . . . . . . . . . . . . . . 83 . . . . . . . . . . . . . . . . . . 84 . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . . . . . . . . . 86 . . . . . . . . . . . . . . . . . . 87 . . . . . . . . . . . . . . . . . . 88 . . . . . . . . . . . . . . . . . . 89 . . . . . . . . . . . . . . . . . . 90 . . . . . . . . . . . . . . . . . . 91 . . . . . . . . . . . . . . . . . . 92 . . . . . . . # . . . . . . . . . . 93 . . . . . . . # . . . . . . . . . . 94 . . # # . . # # . . . . . . . . . . 95 # . # # # . # # . . . . . . . . . . 96 # . # # # # # # . . . . . . . . . . 97 # # # # # # # # # . . . . . . . . # 98 # # # # # # # # # # . # . # # . . # 99 # # # # # # # # # # # # . # # # # # 100 # # # # # # # # # # # # . # # # # # 101 # # # # # # # # # # # # # # # # # # 102 # # # # # # # # # # # # # # # # # # 103 # # # # # # # # # # # # # # # # # # 104 # # # # # # # # # # # # # # # # # # 105 # # # # # # # # # # # # # # # # # # 106 # # # # # # # # # # # # # # # # # # 107 # # # # # # # # # # # # # # # # # # 108 # # # # # # # # # # # # # # # # # # 109 # # # # # # # # # # # # # # # # # # 110 # # # # # # # # # # # # # # # # # # 111 # # # # # # # # # # # # # # # # # # 112 # # # # # # # # # # # # # # # # # # 113 # # # # # # # # # # # # # # # # # # 114 # # # # # # # # # # # # # # # # # # 115 # # # # # # # # # # # # # # # # # # 116 # # # # # # # # # # # # # # # # # # 117 # # # # # # # # # # # # # # # # # # 118 # # # # # # # # # # # # # # # # # # 119 # # # # # # # # # # # # # # # # # # 120 # # # # # # # # # # # # # # # # # # 121 # # # # # # # # # # # # # # # # # # 122 # # # # # # # # # # # # # # # # # # 123 # # # # # # # # # # # # # # # # # # 124 # # # # # # # # # # # # # # # # # # 125 # # # # # # # # # # # # # # # # # # 126 # # # # # # # # # # # # # # # # # # 127 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 64 86 46 109 145 201 158 183 129 68 87 52 113 147 203 160 185 129 PP: 92 113 74 136 173 228 186 208 156 95 114 79 141 175 230 190 212 156 FE: 120 140 103 163 201 256 215 233 184 123 142 107 170 204 258 220 240 184 START_DATA_TX_DQ_BASIC N0.C0.D0.R1.S00: TxDqDqs: Pi = 92 N0.C0.D0.R1.S01: TxDqDqs: Pi = 113 N0.C0.D0.R1.S02: TxDqDqs: Pi = 74 N0.C0.D0.R1.S03: TxDqDqs: Pi = 136 N0.C0.D0.R1.S04: TxDqDqs: Pi = 173 N0.C0.D0.R1.S05: TxDqDqs: Pi = 228 N0.C0.D0.R1.S06: TxDqDqs: Pi = 186 N0.C0.D0.R1.S07: TxDqDqs: Pi = 208 N0.C0.D0.R1.S08: TxDqDqs: Pi = 156 N0.C0.D0.R1.S09: TxDqDqs: Pi = 95 N0.C0.D0.R1.S10: TxDqDqs: Pi = 114 N0.C0.D0.R1.S11: TxDqDqs: Pi = 79 N0.C0.D0.R1.S12: TxDqDqs: Pi = 141 N0.C0.D0.R1.S13: TxDqDqs: Pi = 175 N0.C0.D0.R1.S14: TxDqDqs: Pi = 230 N0.C0.D0.R1.S15: TxDqDqs: Pi = 190 N0.C0.D0.R1.S16: TxDqDqs: Pi = 212 N0.C0.D0.R1.S17: TxDqDqs: Pi = 156 STOP_DATA_TX_DQ_BASIC Entering no zone 19 Tx Dq Basic - 2559ms PPR Flow -- Started Checkpoint Code: Socket 0, 0xB7, 0x36, 0x0000 PPR Flow - 0ms Wr Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x32, 0x0000 Previous Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 85 85 85 85 85 85 85 85 85 N0.C0.D0.R1: 85 85 85 85 85 85 85 85 85 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 89 111 72 135 171 226 187 205 151 93 113 76 139 173 229 190 210 155 N0.C0.D0.R1: 92 113 74 136 173 228 186 208 156 95 114 79 141 175 230 190 212 156 N0.C0: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C0.D0.R0: Checking for eye widths!! Current VREF offset is 0 N0.C0.D0.R1: Checking for eye widths!! Current VREF offset is 0 N0.C0.D0.R0: txVrefSafe = 0x55 N0.C0.D0.R1: txVrefSafe = 0x55 New Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 85 85 85 85 85 85 85 85 85 N0.C0.D0.R1: 85 85 85 85 85 85 85 85 85 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 88 110 72 134 169 226 186 205 151 93 112 76 138 173 229 190 208 153 N0.C0.D0.R1: 92 111 74 136 172 227 185 207 154 95 114 79 140 175 230 190 212 154 Wr Early Vref Centering - 164ms Rd Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x31, 0x0000 Previous Settings START_DATA_RxVref N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 43 41 43 40 41 40 43 42 42 45 42 45 44 44 43 45 44 44 N0.C0.D0.R1: 44 41 44 41 44 41 43 42 43 45 42 45 44 45 44 45 42 45 N0.C0: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C0.D0.R0: Checking for eye widths!! Current VREF offset is 0 N0.C0.D0.R1: Checking for eye widths!! Current VREF offset is 0 New Settings START_DATA_RxVref N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 41 38 40 37 41 37 42 39 42 43 40 44 42 43 43 44 41 44 N0.C0.D0.R1: 42 38 43 38 42 38 40 39 42 44 41 44 43 44 41 45 41 46 Rd Early Vref Centering - 243ms CMD Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x24, 0x0000 N0.C0.D0.R0: High = 31 - Low = -31 N0.C0.D0.R1: High = 31 - Low = -31 N0.C0: Composite High = 31 - Composite Low = -31 final_offset = 0 Reset All Channels JEDEC Init N0.C0: Issue ZQCL N0.C4: (compHigh + compLow)/2 = 32 START_DATA_CMD_VREF_CENTERING N0.C0: Applying offset of 0... N0.C1: Applying offset of 0... N0.C2: Applying offset of 0... N0.C3: Applying offset of 0... STOP_DATA_CMD_VREF_CENTERING CMD Vref Centering - 62ms Late Cmd/Clk -- Started Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000 START_CMD_CLK_PER_GROUP_FINAL N0: Calling GetMargins for CmdAll C0.D0.R0: Platform Group = CmdAll C0.D0.R0: Found CMD Pi group: 0 side 0 C0.D0.R0: cmdLeft[0][0] = -53 : cmdRight[0][0] = 44 C0.D0.R0: Found CMD Pi group: 0 side 1 C0.D0.R0: cmdLeft[1][0] = -53 : cmdRight[1][0] = 44 C0.D0.R0: Found CMD Pi group: 1 side 0 C0.D0.R0: cmdLeft[2][0] = -53 : cmdRight[2][0] = 44 C0.D0.R0: Found CMD Pi group: 1 side 1 C0.D0.R0: cmdLeft[3][0] = -53 : cmdRight[3][0] = 44 C0.D0.R0: Found CMD Pi group: 2 side 0 C0.D0.R0: cmdLeft[4][0] = -53 : cmdRight[4][0] = 44 C0.D0.R0: Found CMD Pi group: 2 side 1 C0.D0.R0: cmdLeft[5][0] = -53 : cmdRight[5][0] = 44 C0.D0.R0: Found CMD Pi group: 3 side 0 C0.D0.R0: cmdLeft[6][0] = -53 : cmdRight[6][0] = 44 C0.D0.R0: Found CMD Pi group: 3 side 1 C0.D0.R0: cmdLeft[7][0] = -53 : cmdRight[7][0] = 44 C0.D0.R0: Found CMD Pi group: 4 side 0 C0.D0.R0: cmdLeft[8][0] = -53 : cmdRight[8][0] = 44 C0.D0.R0: Found CMD Pi group: 4 side 1 C0.D0.R0: cmdLeft[9][0] = -53 : cmdRight[9][0] = 44 C0.D0.R0: Found CMD Pi group: 5 side 0 C0.D0.R0: cmdLeft[10][0] = -53 : cmdRight[10][0] = 44 C0.D0.R0: Found CMD Pi group: 5 side 1 C0.D0.R0: cmdLeft[11][0] = -53 : cmdRight[11][0] = 44 C0.D0.R1: Platform Group = CmdAll C0.D0.R1: Found CMD Pi group: 0 side 0 C0.D0.R1: cmdLeft[0][2] = -49 : cmdRight[0][2] = 46 C0.D0.R1: Found CMD Pi group: 0 side 1 C0.D0.R1: cmdLeft[1][2] = -49 : cmdRight[1][2] = 46 C0.D0.R1: Found CMD Pi group: 1 side 0 C0.D0.R1: cmdLeft[2][2] = -49 : cmdRight[2][2] = 46 C0.D0.R1: Found CMD Pi group: 1 side 1 C0.D0.R1: cmdLeft[3][2] = -49 : cmdRight[3][2] = 46 C0.D0.R1: Found CMD Pi group: 2 side 0 C0.D0.R1: cmdLeft[4][2] = -49 : cmdRight[4][2] = 46 C0.D0.R1: Found CMD Pi group: 2 side 1 C0.D0.R1: cmdLeft[5][2] = -49 : cmdRight[5][2] = 46 C0.D0.R1: Found CMD Pi group: 3 side 0 C0.D0.R1: cmdLeft[6][2] = -49 : cmdRight[6][2] = 46 C0.D0.R1: Found CMD Pi group: 3 side 1 C0.D0.R1: cmdLeft[7][2] = -49 : cmdRight[7][2] = 46 C0.D0.R1: Found CMD Pi group: 4 side 0 C0.D0.R1: cmdLeft[8][2] = -49 : cmdRight[8][2] = 46 C0.D0.R1: Found CMD Pi group: 4 side 1 C0.D0.R1: cmdLeft[9][2] = -49 : cmdRight[9][2] = 46 C0.D0.R1: Found CMD Pi group: 5 side 0 C0.D0.R1: cmdLeft[10][2] = -49 : cmdRight[10][2] = 46 C0.D0.R1: Found CMD Pi group: 5 side 1 C0.D0.R1: cmdLeft[11][2] = -49 : cmdRight[11][2] = 46 N0.C0: CMD Pi Group 0 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 1 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 2 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 3 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 4 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 5 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 6 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 7 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 8 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 9 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 10 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 11 clk 0 cmdOffset -4 N0.C0: CMD Pi Group 0 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 1 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 2 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 3 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 4 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 5 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 6 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 7 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 8 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 9 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 10 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 11 clk 2 cmdOffset -1 N0.C0: CMD Pi Group 0: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 1: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 2: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 3: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 4: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 5: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 6: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 7: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 8: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 9: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 10: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: CMD Pi Group 11: maxOffset = -1, minOffset = -4, cmdOffset = -2 N0.C0: <--CMD Pi Group 0 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 0 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 1 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 1 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 2 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 2 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 3 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 3 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 4 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 4 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 5 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 5 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 6 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 6 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 7 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 7 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 8 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 8 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 9 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 9 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 10 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 10 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <--CMD Pi Group 11 clk 0: cmdLeft -51 - cmdRight 46 N0.C0: <--CMD Pi Group 11 clk 2: cmdLeft -47 - cmdRight 48 N0.C0: <----clk 0 ckOffset 2: -(maxLeftOffset:-51 + minRightOffset:46) / 2 N0.C0: <----clk 2 ckOffset 0: -(maxLeftOffset:-47 + minRightOffset:48) / 2 STOP_CMD_CLK_PER_GROUP_FINAL Reset All Channels JEDEC Init N0.C0: Issue ZQCL Late Cmd/Clk - 611ms Tx Eq -- Started Checkpoint Code: Socket 0, 0xB7, 0x1B, 0x0000 Printing initialized array of cached values... Tx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params [0] 0x0 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 59 60 59 60 60 59 59 59 60 59 60 59 60 60 59 59 59 60 N0.C0.D0.R1: 60 60 58 60 60 59 60 59 60 60 60 58 60 60 59 60 59 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 49 50 54 54 51 55 48 50 54 49 50 54 54 51 55 48 50 N0.C0.D0.R1: 51 49 50 50 54 51 53 49 49 51 49 50 50 54 51 53 49 49 Setting 1 Params [0] 0x2 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 59 60 59 60 60 59 59 59 60 59 60 59 60 60 59 59 59 60 N0.C0.D0.R1: 60 60 59 60 60 59 60 59 60 60 60 59 60 60 59 60 59 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 51 50 55 54 52 55 48 50 54 51 50 55 54 52 55 48 50 N0.C0.D0.R1: 51 49 51 51 54 51 53 49 49 51 49 51 51 54 51 53 49 49 Setting 2 Params [0] 0x4 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 59 60 59 60 60 59 59 60 60 59 60 59 60 60 59 59 60 60 N0.C0.D0.R1: 60 60 59 60 60 59 60 59 60 60 60 59 60 60 59 60 59 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 51 51 55 54 52 55 49 50 54 51 51 55 54 52 55 49 50 N0.C0.D0.R1: 52 49 52 51 54 51 53 50 51 52 49 52 51 54 51 53 50 51 Setting 3 Params [0] 0x6 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 59 60 59 60 60 59 59 60 60 59 60 59 60 60 59 59 60 60 N0.C0.D0.R1: 60 60 59 60 60 59 60 59 60 60 60 59 60 60 59 60 59 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 55 50 51 54 55 53 56 49 50 55 50 51 54 55 53 56 49 50 N0.C0.D0.R1: 53 49 52 50 54 52 54 50 51 53 49 52 50 54 52 54 50 51 Setting 4 Params [0] 0x8 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 59 59 59 60 60 58 59 60 60 59 59 59 60 60 58 59 60 60 N0.C0.D0.R1: 60 58 59 58 59 58 60 59 58 60 58 59 58 59 58 60 59 58 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 55 50 51 54 55 52 56 49 50 55 50 51 54 55 52 56 49 50 N0.C0.D0.R1: 52 48 52 50 54 52 54 50 50 52 48 52 50 54 52 54 50 50 Setting 5 Params [0] 0xA Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 58 57 58 59 60 56 58 58 58 58 57 58 59 60 56 58 58 58 N0.C0.D0.R1: 59 57 57 56 57 55 59 59 56 59 57 57 56 57 55 59 59 56 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 55 50 50 54 55 53 55 49 50 55 50 50 54 55 53 55 49 50 N0.C0.D0.R1: 52 48 51 50 53 51 54 50 50 52 48 51 50 53 51 54 50 50 Setting 6 Params [0] 0xC Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 57 55 56 56 59 53 56 57 57 57 55 56 56 59 53 56 57 57 N0.C0.D0.R1: 57 53 54 53 56 52 57 57 55 57 53 54 53 56 52 57 57 55 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 50 50 52 54 52 55 49 49 54 50 50 52 54 52 55 49 49 N0.C0.D0.R1: 51 49 51 49 54 52 54 49 50 51 49 51 49 54 52 54 49 50 Setting 7 Params [0] 0xE Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 53 52 52 54 55 50 53 53 53 53 52 52 54 55 50 53 53 53 N0.C0.D0.R1: 54 50 52 51 53 49 55 54 51 54 50 52 51 53 49 55 54 51 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 50 50 52 54 52 54 49 49 54 50 50 52 54 52 54 49 49 N0.C0.D0.R1: 51 48 50 49 53 51 54 49 50 51 48 50 49 53 51 54 49 50 Setting 8 Params [0] 0x10 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 50 49 50 50 52 46 50 51 50 50 49 50 50 52 46 50 51 50 N0.C0.D0.R1: 51 47 48 48 50 47 51 52 49 51 47 48 48 50 47 51 52 49 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 54 49 49 52 54 50 53 48 49 54 49 49 52 54 50 53 48 49 N0.C0.D0.R1: 50 47 50 49 52 51 54 49 49 50 47 50 49 52 51 54 49 49 Setting 9 Params [0] 0x12 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 48 46 46 47 49 43 47 48 48 48 46 46 47 49 43 47 48 48 N0.C0.D0.R1: 47 44 45 46 48 43 48 47 45 47 44 45 46 48 43 48 47 45 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 53 49 49 51 53 50 53 48 48 53 49 49 51 53 50 53 48 48 N0.C0.D0.R1: 50 46 50 49 52 50 53 48 48 50 46 50 49 52 50 53 48 48 Setting 10 Params [0] 0x14 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 44 43 43 44 46 41 45 44 44 44 43 43 44 46 41 45 44 44 N0.C0.D0.R1: 45 41 42 42 44 40 45 46 42 45 41 42 42 44 40 45 46 42 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 53 49 49 51 53 50 52 48 48 53 49 49 51 53 50 52 48 48 N0.C0.D0.R1: 50 46 50 49 51 50 51 48 47 50 46 50 49 51 50 51 48 47 Setting 11 Params [0] 0x16 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 41 40 41 41 43 37 42 42 42 41 40 41 41 43 37 42 42 42 N0.C0.D0.R1: 42 38 39 40 41 37 43 42 40 42 38 39 40 41 37 43 42 40 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 52 48 48 50 52 49 52 47 48 52 48 48 50 52 49 52 47 48 N0.C0.D0.R1: 49 45 49 48 50 50 50 48 47 49 45 49 48 50 50 50 48 47 Setting 12 Params [0] 0x18 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 38 37 37 38 40 34 38 39 38 38 37 37 38 40 34 38 39 38 N0.C0.D0.R1: 38 35 36 36 39 34 39 39 36 38 35 36 36 39 34 39 39 36 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 51 47 48 50 51 49 51 47 47 51 47 48 50 51 49 51 47 47 N0.C0.D0.R1: 49 46 49 48 49 50 50 47 46 49 46 49 48 49 50 50 47 46 Setting 13 Params [0] 0x1A Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 32 31 30 32 34 28 32 31 32 32 31 30 32 34 28 32 31 32 N0.C0.D0.R1: 32 29 30 31 33 28 33 34 30 32 29 30 31 33 28 33 34 30 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 50 46 48 50 49 48 50 46 45 50 46 48 50 49 48 50 46 45 N0.C0.D0.R1: 48 44 49 47 48 47 49 46 45 48 44 49 47 48 47 49 46 45 Setting 14 Params [0] 0x1C Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 29 28 28 28 31 24 30 29 29 29 28 28 28 31 24 30 29 29 N0.C0.D0.R1: 30 26 26 27 29 25 30 30 27 30 26 26 27 29 25 30 30 27 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 50 45 47 49 49 48 50 44 44 50 45 47 49 49 48 50 44 44 N0.C0.D0.R1: 48 44 48 46 48 47 49 46 45 48 44 48 46 48 47 49 46 45 Setting 15 Params [0] 0x1E Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 29 27 27 28 31 24 30 29 29 29 27 27 28 31 24 30 29 29 N0.C0.D0.R1: 30 27 27 26 29 25 30 30 26 30 27 27 26 29 25 30 30 26 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 50 45 47 49 49 48 50 45 44 50 45 47 49 49 48 50 45 44 N0.C0.D0.R1: 48 43 48 46 48 47 49 46 44 48 43 48 46 48 47 49 46 44 Power TrendLine Calculation N0.C0.D0.R0.S00: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C0.D0.R0.S01: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C0.D0.R0.S02: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C0.D0.R0.S03: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C0.D0.R0.S04: minPower = 0 : maxPower = 1500 AveOfMax = 575 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C0.D0.R0.S05: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C0.D0.R0.S06: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C0.D0.R0.S07: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C0.D0.R0.S08: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C0.D0.R0.S09: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C0.D0.R0.S10: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C0.D0.R0.S11: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C0.D0.R0.S12: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C0.D0.R0.S13: minPower = 0 : maxPower = 1500 AveOfMax = 575 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C0.D0.R0.S14: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C0.D0.R0.S15: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C0.D0.R0.S16: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C0.D0.R0.S17: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 17: N0.C0.D0.R1.S00: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C0.D0.R1.S01: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C0.D0.R1.S02: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C0.D0.R1.S03: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C0.D0.R1.S04: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C0.D0.R1.S05: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C0.D0.R1.S06: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C0.D0.R1.S07: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C0.D0.R1.S08: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C0.D0.R1.S09: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C0.D0.R1.S10: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C0.D0.R1.S11: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C0.D0.R1.S12: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C0.D0.R1.S13: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C0.D0.R1.S14: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C0.D0.R1.S15: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C0.D0.R1.S16: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C0.D0.R1.S17: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Tx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 8 2 6 0 8 4 0 6 0 8 2 6 0 8 4 0 6 0 N0.C0.D0.R1: 4 0 6 0 0 0 8 6 4 4 0 6 0 0 0 8 6 4 END_OPTIMAL_TRAINING_RESULTS Reset All Channels JEDEC Init N0.C0: Issue ZQCL Tx Eq - 2031ms Imode -- Started Checkpoint Code: Socket 0, 0xB7, 0x1D, 0x0000 Imode - 0ms CTLE -- Started Checkpoint Code: Socket 0, 0xB7, 0x67, 0x0000 Printing initialized array of cached values... Rx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params Rx Eq 0x0 CTLE C 0x0 CTLE R 0x0 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 46 54 46 48 51 47 48 48 49 46 54 46 48 51 47 48 48 49 N0.C0.D0.R1: 49 51 50 49 46 48 43 52 48 49 51 50 49 46 48 43 52 48 Setting 1 Params Rx Eq 0x2 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 46 52 47 48 51 48 46 49 48 46 52 47 48 51 48 46 49 48 N0.C0.D0.R1: 49 50 51 48 47 48 43 51 46 49 50 51 48 47 48 43 51 46 Setting 2 Params Rx Eq 0x2 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 46 51 47 48 51 47 46 48 47 46 51 47 48 51 47 46 48 47 N0.C0.D0.R1: 49 49 51 48 47 48 42 51 46 49 49 51 48 47 48 42 51 46 Setting 3 Params Rx Eq 0x2 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 51 47 48 51 47 45 48 47 45 51 47 48 51 47 45 48 47 N0.C0.D0.R1: 47 48 49 48 46 49 43 51 45 47 48 49 48 46 49 43 51 45 Setting 4 Params Rx Eq 0x3 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 52 48 49 51 48 47 49 48 45 52 48 49 51 48 47 49 48 N0.C0.D0.R1: 48 50 51 49 47 49 43 51 47 48 50 51 49 47 49 43 51 47 Setting 5 Params Rx Eq 0x3 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 51 47 48 51 47 47 48 46 45 51 47 48 51 47 47 48 46 N0.C0.D0.R1: 47 49 50 49 47 48 43 50 46 47 49 50 49 47 48 43 50 46 Setting 6 Params Rx Eq 0x3 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 51 47 47 49 47 46 47 45 45 51 47 47 49 47 46 47 45 N0.C0.D0.R1: 47 50 49 49 45 47 41 49 45 47 50 49 49 45 47 41 49 45 Setting 7 Params Rx Eq 0x4 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 47 51 48 49 51 49 47 49 48 47 51 48 49 51 49 47 49 48 N0.C0.D0.R1: 49 50 50 49 48 50 43 50 47 49 50 50 49 48 50 43 50 47 Setting 8 Params Rx Eq 0x4 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 50 49 48 51 48 47 48 47 45 50 49 48 51 48 47 48 47 N0.C0.D0.R1: 49 50 51 48 47 49 43 50 47 49 50 51 48 47 49 43 50 47 Setting 9 Params Rx Eq 0x4 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 N0.C0.D0.R1: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C0.D0.R0: 45 49 48 47 49 48 46 49 46 45 49 48 47 49 48 46 49 46 N0.C0.D0.R1: 47 48 50 47 46 48 42 50 46 47 48 50 47 46 48 42 50 46 Power TrendLine Calculation N0.C0.D0.R0.S00: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C0.D0.R0.S01: minPower = 0 : maxPower = 900 AveOfMax = 750 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C0.D0.R0.S02: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C0.D0.R0.S03: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C0.D0.R0.S04: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C0.D0.R0.S05: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C0.D0.R0.S06: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C0.D0.R0.S07: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C0.D0.R0.S08: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C0.D0.R0.S09: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C0.D0.R0.S10: minPower = 0 : maxPower = 900 AveOfMax = 750 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C0.D0.R0.S11: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C0.D0.R0.S12: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C0.D0.R0.S13: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C0.D0.R0.S14: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C0.D0.R0.S15: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C0.D0.R0.S16: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C0.D0.R0.S17: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 17: N0.C0.D0.R1.S00: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C0.D0.R1.S01: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C0.D0.R1.S02: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C0.D0.R1.S03: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C0.D0.R1.S04: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C0.D0.R1.S05: minPower = 0 : maxPower = 900 AveOfMax = 730 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C0.D0.R1.S06: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C0.D0.R1.S07: minPower = 0 : maxPower = 900 AveOfMax = 740 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C0.D0.R1.S08: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C0.D0.R1.S09: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C0.D0.R1.S10: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C0.D0.R1.S11: minPower = 0 : maxPower = 900 AveOfMax = 735 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C0.D0.R1.S12: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C0.D0.R1.S13: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C0.D0.R1.S14: minPower = 0 : maxPower = 900 AveOfMax = 730 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C0.D0.R1.S15: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C0.D0.R1.S16: minPower = 0 : maxPower = 900 AveOfMax = 740 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C0.D0.R1.S17: minPower = 0 : maxPower = 900 AveOfMax = 720 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Rx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_OPTIMAL_TRAINING_RESULTS CTLE - 1747ms Tx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0E, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Tx ============================================================================== PatternLength: 64 Per bit margins: TxDq 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 * * *** ******** ******** ** *** * ** ** ** ***** ******** ** *** * ******** 29 * *** ** **** ******* ** *** * * ** * ***** ******* ** *** * ** **** 28 * *** * *** ****** ** ** * * * * * ******* * *** * * ** 27 *** * ** * * * * ** * * * ******* * ** * * 26 * * ** * * * * * * ** * ** * * 25 * * * * * * * ** * 24 * * * * -25 * * * -26 * * * * * * * * * ** -27 * * * * * * * * * * * * * * * *** ** -28 *** * ** * * * * ** ** * *** ** * * ** *** *** -29 *** ** ** ** * * *** ** *** ** *** * ** * * * *** ******* -30 *** *** ** *** * * *** **** *** *** ** ******** * ** * * *** ******* N0.C0.D0.R0: TxDq - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 28 31 30 31 26 27 27 31 24 29 30 24 26 28 29 30 25 28 27 28 24 28 29 30 27 28 31 27 25 29 31 26 29 30 31 29 -31 -26 -28 -27 -31 -30 -29 -25 -31 -28 -27 -31 -31 -30 -29 -27 -31 -30 -31 -28 -31 -30 -30 -27 -29 -29 -27 -30 -31 -30 -26 -28 -29 -28 -27 -31 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 27 31 31 31 30 29 31 27 29 28 29 28 26 27 26 27 27 25 26 30 29 24 31 25 25 28 31 28 25 29 30 26 28 29 29 30 -31 -31 -26 -29 -28 -28 -26 -30 -29 -30 -25 -28 -31 -31 -31 -30 -31 -31 -30 -29 -26 -31 -26 -31 -31 -28 -26 -29 -31 -26 -25 -27 -29 -28 -27 -27 Per bit margins: TxDq 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******* ** ***** * * *** ** ***** ** ** ** ***** * ***** * ***** ***** ** 29 ******* * ** ** * * *** ** ***** * ** ** ***** * ***** * ***** ** ** 28 * ***** * ** * * * * * * ** * ** * * * * * ** * ** ** ** ** 27 * * * ** * * * * ** * * * * * ** * ** * * * 26 * * * * * ** * * ** ** * 25 * * * * * * * 24 * * -25 * * * * -26 * ** * ** * * * * ** -27 * * * ** *** * * ** * * * * * * * * * * **** -28 * * * *** *** * * ** *** ** *** * * * * *** * * *** * *** **** -29 * *** *** **** *** * *** **** *** *** *** * ** ***** * *** *** *** **** -30 **** *** *** **** *** * * *** **** ******** *** **** ***** * *** *** *** **** N0.C0.D0.R1: TxDq - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 26 29 28 28 25 28 27 31 28 30 31 24 27 30 28 29 26 31 28 31 27 29 27 31 26 29 31 26 25 29 29 29 27 30 31 28 -30 -27 -30 -30 -31 -27 -29 -25 -28 -26 -25 -31 -29 -27 -27 -27 -31 -26 -29 -29 -31 -30 -31 -27 -29 -26 -25 -31 -29 -28 -27 -28 -29 -28 -27 -30 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 27 31 31 31 29 25 31 24 29 27 29 28 28 31 29 29 29 26 26 31 31 27 31 25 26 29 28 27 25 28 30 28 27 31 30 30 -30 -28 -28 -28 -27 -29 -26 -31 -28 -30 -27 -29 -28 -27 -28 -29 -27 -31 -31 -28 -26 -28 -25 -31 -31 -29 -28 -29 -28 -28 -26 -31 -27 -26 -26 -27 N0.C0: Calculating Bit Centers N0.C0: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 ============================================================================== 0 -1 2 1 2 0 3 2 3 1 -2 -1 -1 3 0 1 1 5 2 -3 0 1 -3 0 3 4 0 3 -2 -1 0 1 0 1 2 3 4 -3 -1 -2 0 0 2 1 3 5 -3 -1 0 1 0 2 3 4 6 -1 0 2 -1 0 1 3 0 7 -3 0 2 -1 0 3 5 2 8 0 1 2 -1 1 2 3 0 9 -2 0 2 1 0 2 4 3 10 1 0 2 -1 2 1 3 0 11 0 -1 2 0 1 0 3 1 12 -2 -2 -2 -1 0 0 0 1 13 -2 -3 -2 0 1 0 1 3 14 1 -3 2 -3 4 0 5 0 15 -3 0 2 0 0 3 5 3 16 -3 1 2 0 0 4 5 3 17 0 0 1 1 0 0 1 1 N0.C0: dimm = 0, rank = 1 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 ============================================================================== 0 -2 1 -1 -1 0 3 1 1 1 -3 0 -1 3 0 3 2 6 2 0 2 3 -3 3 5 6 0 3 -1 1 0 1 0 2 1 2 4 -2 2 0 1 0 4 2 3 5 -2 0 -2 2 0 2 0 4 6 -1 1 3 -2 1 3 5 0 7 -2 0 1 0 0 2 3 2 8 -1 1 2 -1 0 2 3 0 9 -1 1 1 1 0 2 2 2 10 1 -2 2 -3 4 1 5 0 11 0 -1 1 0 1 0 2 1 12 0 2 0 0 0 2 0 0 13 1 -2 -2 1 3 0 0 3 14 2 0 3 -3 5 3 6 0 15 -2 0 0 -1 0 2 2 1 16 -1 0 2 -1 0 1 3 0 17 0 2 2 1 0 2 2 1 START_DATA_TX_DQ_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 45 48 47 48 49 50 50 54 35 38 39 35 38 39 40 41 31 33 32 34 35 37 38 39 0 1 3 0 2 5 7 4 6 7 8 5 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 8 10 12 11 31 30 32 29 33 32 35 33 16 16 16 17 20 19 20 22 5 1 6 1 4 7 9 7 49 53 54 52 54 54 55 55 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 46 49 47 47 48 51 50 54 37 39 40 34 39 41 40 41 32 36 34 35 37 39 37 41 0 2 4 63 3 5 6 5 6 8 9 6 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 9 11 11 11 30 27 31 26 32 31 33 32 15 17 15 15 21 18 18 21 6 4 7 1 7 9 9 8 52 53 55 52 53 55 55 54 N0: STOP_PER_BIT_DESKEW Tx Per Bit Deskew - 760ms Rx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0D, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx P ============================================================================== PatternLength: 64 Per bit margins: Rx DqsP 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 *** * * *** ** * * * *** ******** ******** ***** * ******** **** *** 29 * * * * ** * * *** ** ** * ******** ***** * ******** **** *** 28 * * * * ** * *** **** **** * ****** *** * 27 * * * *** **** * * ****** *** 26 * *** * ** * * ***** *** 25 * * * * * * ** 24 * * * * * 23 * * -23 * * * -24 * * * * * * * * * -25 * * * * * * ** ** ** * * * * * * * * -26 * * * * * * *** ***** * * * ** * * * * *** * ** * * * * -27 * * * * * * *** *** ***** * * * **** * * * * **** ******** * * * -28 *** *** ** ** * *** **** ***** * ** ***** **** * * * * **** ******** * **** -29 *** **** ** **** ******** ******** ******** ****** * *** **** ******** * **** -30 ******** ******** ******** ******** ******** ****** * ******** ******** *** **** N0.C0.D0.R0: RxDqsP - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 31 28 30 26 31 29 31 27 31 29 29 30 31 31 30 29 31 30 31 28 31 31 31 30 31 31 31 31 31 28 28 29 30 29 27 30 -23 -28 -28 -30 -24 -28 -24 -29 -26 -28 -30 -28 -27 -29 -27 -30 -23 -27 -25 -29 -25 -26 -26 -28 -24 -25 -26 -25 -24 -29 -29 -26 -26 -28 -29 -28 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 29 29 30 29 25 26 24 29 24 27 23 26 28 28 28 26 29 31 29 31 23 29 25 26 26 24 25 27 29 26 26 26 31 29 28 29 -26 -28 -28 -28 -25 -23 -27 -24 -29 -25 -31 -26 -25 -29 -27 -30 -26 -25 -26 -27 -27 -25 -27 -26 -25 -27 -27 -24 -25 -30 -30 -31 -26 -28 -26 -28 Per bit margins: Rx DqsP 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 **** *** ******** *** * * ******** * * ***** * * * ** *** **** ******** 29 **** * * ** **** *** * ******** * * * * * * * * * * * *** ******** 28 ** * * * ** *** *** * *** **** * * * * * * * * *** *** ** 27 * * * * * *** * * * *** **** * * ** ** * 26 * * * * * * * * ** **** * ** * 25 * * * ** **** * 24 * ** *** -22 * -23 * * -24 * * * * * -25 * * * * * * ** * * * * * * * * -26 * * * * * * *** ** ** * * ** * * * * * * * ** * -27 * * * ** ** * *** ** ** * * * ** * * * **** * * ** * ** * * -28 * * *** ** ** * * * *** ***** * * *** ****** * ******** ** ***** ** **** -29 *** *** ******* * * **** ******** ** ***** ****** * ******** ******** ******** -30 *** **** ******** *** **** ******** ** ***** ******** ******** ******** ******** N0.C0.D0.R1: RxDqsP - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 28 25 29 24 31 26 30 26 30 28 27 30 29 27 27 26 31 26 28 25 31 30 31 26 27 24 24 29 25 24 24 24 31 28 31 31 -24 -29 -28 -31 -25 -28 -26 -30 -26 -27 -29 -27 -26 -29 -28 -30 -25 -30 -28 -31 -25 -26 -25 -29 -25 -26 -28 -25 -25 -29 -29 -27 -25 -29 -31 -29 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 31 29 31 31 28 30 29 30 28 31 26 31 31 29 31 31 27 31 30 28 28 30 28 31 28 27 27 30 29 26 25 28 29 26 28 29 -25 -28 -28 -29 -26 -24 -28 -26 -28 -23 -30 -25 -22 -27 -26 -27 -28 -25 -28 -28 -28 -26 -29 -26 -26 -28 -28 -27 -24 -27 -29 -29 -27 -28 -27 -28 N0.C0: Calculating Bit Centers N0.C0: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 4 0 1 -2 6 2 3 0 1 3 0 3 -1 4 1 4 0 2 2 0 0 1 2 0 0 1 3 2 1 1 0 2 1 1 0 4 4 1 3 0 4 1 3 0 5 3 2 2 1 2 1 1 0 6 3 3 2 3 1 1 0 1 7 3 0 0 1 3 0 0 1 8 2 0 -1 1 3 1 0 2 9 1 0 1 0 1 0 1 0 10 0 1 -1 2 1 2 0 3 11 -2 1 -4 0 2 5 0 4 12 1 0 0 -2 3 2 2 0 13 1 3 1 2 0 2 0 1 14 -2 2 -1 0 0 4 1 2 15 0 -1 -1 1 1 0 0 2 16 2 -2 -2 -2 4 0 0 0 17 2 0 1 0 2 0 1 0 N0.C0: dimm = 0, rank = 1 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 2 -2 0 -3 5 1 3 0 1 3 -1 2 -2 5 1 4 0 2 2 0 -1 1 3 1 0 2 3 1 -1 0 -2 3 1 2 0 4 3 -2 0 -3 6 1 3 0 5 3 2 3 -1 4 3 4 0 6 1 -1 -2 2 3 1 0 4 7 0 -2 -2 -1 2 0 0 1 8 3 0 0 1 3 0 0 1 9 3 0 1 1 3 0 1 1 10 1 3 0 2 1 3 0 2 11 0 4 -2 3 2 6 0 5 12 4 1 2 2 3 0 1 1 13 0 3 1 0 0 3 1 0 14 0 2 0 2 0 2 0 2 15 1 0 0 1 1 0 0 1 16 2 0 -2 0 4 2 0 2 17 1 -1 0 0 2 0 1 1 START_DATA_RX_DQS_P_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6 2 3 0 4 1 4 0 2 0 0 1 2 1 1 0 4 1 3 0 2 1 1 0 1 1 0 1 3 0 0 1 3 1 0 2 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 1 0 1 0 1 2 0 3 2 5 0 4 3 2 2 0 0 2 0 1 0 4 1 2 1 0 0 2 4 0 0 0 2 0 1 0 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 1 3 0 5 1 4 0 3 1 0 2 3 1 2 0 6 1 3 0 4 3 4 0 3 1 0 4 2 0 0 1 3 0 0 1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 0 1 1 1 3 0 2 2 6 0 5 3 0 1 1 0 3 1 0 0 2 0 2 1 0 0 1 4 2 0 2 2 0 1 1 N0: STOP_PER_BIT_DESKEW N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx N ============================================================================== PatternLength: 64 Per bit margins: Rx DqsN 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 **** *** ******** **** *** ******** ******** ******** ******** * * ******** 29 **** *** ******* **** *** ******** ******** * * * ** ***** ** * * **** *** 28 **** *** *** *** *** *** ******** ******** * * ** **** ** *** ** 27 *** *** *** * * * * * ******** **** *** * * ** **** ** *** * 26 * * * * * * * * ******** *** *** * * **** *** 25 * * * * * *** *** ** * * * *** *** 24 * * * * * ** ** * * * * * 23 * * ** * * -25 * * -26 * * * * * -27 * * * * ** ** ** * * * * * -28 * * * * * ** ** * * ** * * * * ** * * * -29 * * * * * * * * * ***** * * * ** * * * * ** * ** * * **** -30 *** **** * *** * * * ****** * ** ***** **** * * * **** ******** * **** N0.C0.D0.R0: RxDqsN - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 28 24 27 23 31 27 27 24 30 27 26 27 29 28 28 26 29 27 28 23 31 26 28 24 26 24 24 25 26 23 23 25 27 26 24 25 -25 -30 -30 -31 -25 -30 -27 -30 -29 -31 -31 -31 -29 -30 -29 -31 -27 -31 -28 -31 -29 -31 -31 -31 -26 -27 -29 -27 -27 -30 -31 -29 -28 -30 -31 -30 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 28 26 26 25 29 30 25 30 27 30 24 27 26 24 25 23 29 30 27 27 29 31 29 31 31 31 31 31 29 25 23 25 30 29 28 27 -28 -30 -30 -30 -27 -26 -30 -27 -31 -27 -31 -29 -29 -31 -31 -31 -30 -26 -29 -30 -30 -28 -30 -28 -28 -30 -30 -27 -29 -31 -31 -31 -27 -29 -28 -29 Per bit margins: Rx DqsN 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 **** * * ******** *** * * ******** ******** ******** ******** ******** ******** 29 ** * * * ******** * * * ** **** ******** ***** ** ******** ******** ******** 28 ** * * * ******** * * * ** *** ******** ***** ** ******** *** **** ******** 27 * * * * *** **** * * * * *** ******** ***** * ******** * * * **** *** 26 * * * * *** *** * * *** ******** * * * * ******** * * **** ** 25 * * * * * * ******** * * ******** *** * 24 * * **** *** * ***** * * 23 *** * **** * * 22 *** * * 21 * * * 20 * -23 * -24 * -25 * * -26 * * * * * -27 * * * * * * * * * * -28 * * * * * * * * * ** *** * * * * * * * -29 * * * * * * * ** ** * * ** *** * * * * * * ** * * * -30 * * *** ** **** * *** ** ** * * ** ** *** * ******** ** ***** * * N0.C0.D0.R1: RxDqsN - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 28 25 30 25 31 26 31 26 26 26 24 28 27 26 26 24 31 27 30 25 31 30 31 27 30 28 26 30 29 26 25 26 24 21 22 21 -27 -31 -30 -31 -25 -30 -28 -31 -28 -30 -31 -30 -28 -30 -30 -31 -29 -31 -31 -31 -30 -30 -29 -31 -26 -29 -31 -28 -29 -31 -31 -30 -27 -31 -31 -31 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 25 23 24 24 24 27 26 27 26 30 25 28 25 20 23 22 23 24 25 23 26 28 26 29 28 27 28 28 26 25 23 25 28 27 25 26 -26 -30 -31 -31 -28 -27 -31 -28 -28 -23 -31 -27 -26 -30 -29 -30 -30 -27 -30 -29 -30 -28 -31 -28 -29 -30 -30 -28 -28 -31 -31 -31 -29 -31 -31 -31 N0.C0: Calculating Bit Centers N0.C0: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 1 -3 -1 -4 5 1 3 0 1 3 -1 0 -3 6 2 3 0 2 0 -2 -2 -2 2 0 0 0 3 0 -1 0 -2 2 1 2 0 4 1 -2 0 -4 5 2 4 0 5 1 -2 -1 -3 4 1 2 0 6 0 -1 -2 -1 2 1 0 1 7 0 -3 -4 -2 4 1 0 2 8 0 -2 -3 -2 3 1 0 1 9 0 -2 -2 -2 2 0 0 0 10 1 2 -2 1 3 4 0 3 11 -2 1 -3 -1 1 4 0 2 12 -1 -3 -3 -4 3 1 1 0 13 0 2 -1 -1 1 3 0 0 14 0 1 0 1 0 1 0 1 15 1 0 0 2 1 0 0 2 16 0 -3 -4 -3 4 1 0 1 17 1 0 0 -1 2 1 1 0 N0.C0: dimm = 0, rank = 1 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 0 -3 0 -3 3 0 3 0 1 3 -2 1 -2 5 0 3 0 2 -1 -2 -3 -1 2 1 0 2 3 0 -2 -2 -3 3 1 1 0 4 1 -2 0 -3 4 1 3 0 5 0 0 1 -2 2 2 3 0 6 2 0 -2 1 4 2 0 3 7 0 -2 -3 -2 3 1 0 1 8 -1 -5 -4 -5 4 0 1 0 9 0 -3 -3 -3 3 0 0 0 10 -2 0 -2 0 0 2 0 2 11 -1 3 -3 0 2 6 0 3 12 0 -5 -3 -4 5 0 2 1 13 -3 -1 -2 -3 0 2 1 0 14 -2 0 -2 0 0 2 0 2 15 0 -1 -1 0 1 0 0 1 16 -1 -3 -4 -3 3 1 0 1 17 0 -2 -3 -2 3 1 0 1 START_DATA_RX_DQS_N_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 1 3 0 6 2 3 0 2 0 0 0 2 1 2 0 5 2 4 0 4 1 2 0 2 1 0 1 4 1 0 2 3 1 0 1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 0 0 0 3 4 0 3 1 4 0 2 3 1 1 0 1 3 0 0 0 1 0 1 1 0 0 2 4 1 0 1 2 1 1 0 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 3 0 3 0 5 0 3 0 2 1 0 2 3 1 1 0 4 1 3 0 2 2 3 0 4 2 0 3 3 1 0 1 4 0 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 0 0 0 0 2 0 2 2 6 0 3 5 0 2 1 0 2 1 0 0 2 0 2 1 0 0 1 3 1 0 1 3 1 0 1 N0: STOP_PER_BIT_DESKEW Rx Per Bit Deskew - 1637ms Wr Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x1E, 0x0000 Wr Vref Centering (LRDIMM) - 0ms Rd Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x33, 0x0000 Rd Vref Centering (LRDIMM) - 0ms Wr Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x34, 0x0000 Wr Dq Centering (LRDIMM) - 0ms Rd Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x35, 0x0000 Rd Dq Centering (LRDIMM) - 0ms Wr Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x09, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C0.D0.R0: -4 4 0 N0.C0.D0.R1: -4 4 0 N0: Get vref margins at 3 timing points START_TX_VREF_CENTER N0: vref Margins - 0 + N0.C0.D0.R0.S00: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S01: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S02: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S03: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S04: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S05: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S06: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S07: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R0.S08: -31 : 29, -31 : 29, -31 : 29 N0: vref Margins - 0 + N0.C0.D0.R1.S00: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S01: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S02: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S03: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S04: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S05: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S06: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S07: -31 : 29, -31 : 29, -31 : 29 N0.C0.D0.R1.S08: -31 : 29, -31 : 29, -31 : 29 STOP_TX_VREF_CENTER vrefLo vrefHi offset N0.C0.D0.R0.S00: -31 29 -1 N0.C0.D0.R0.S01: -31 29 -1 N0.C0.D0.R0.S02: -31 29 -1 N0.C0.D0.R0.S03: -31 29 -1 N0.C0.D0.R0.S04: -31 29 -1 N0.C0.D0.R0.S05: -31 29 -1 N0.C0.D0.R0.S06: -31 29 -1 N0.C0.D0.R0.S07: -31 29 -1 N0.C0.D0.R0.S08: -31 29 -1 vrefLo vrefHi offset N0.C0.D0.R1.S00: -31 29 -1 N0.C0.D0.R1.S01: -31 29 -1 N0.C0.D0.R1.S02: -31 29 -1 N0.C0.D0.R1.S03: -31 29 -1 N0.C0.D0.R1.S04: -31 29 -1 N0.C0.D0.R1.S05: -31 29 -1 N0.C0.D0.R1.S06: -31 29 -1 N0.C0.D0.R1.S07: -31 29 -1 N0.C0.D0.R1.S08: -31 29 -1 N0.C0.D0.R0: txVrefSafe = 0x54 N0.C0.D0.R1: txVrefSafe = 0x54 Wr Vref Centering - 259ms Rd Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x08, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C0.D0.R0: -4 4 0 N0.C0.D0.R1: -4 4 0 N0: Get vref margins at 3 timing points START_RX_VREF_CENTER N0: vref Margins - 0 + N0.C0.D0.R0.S00: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S01: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S02: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S03: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S04: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S05: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S06: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S07: -47 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S08: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S09: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S10: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S11: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S12: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S13: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S14: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S15: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S16: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R0.S17: -48 : 48, -48 : 48, -48 : 48 N0: vref Margins - 0 + N0.C0.D0.R1.S00: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S01: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S02: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S03: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S04: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S05: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S06: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S07: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S08: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S09: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S10: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S11: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S12: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S13: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S14: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S15: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S16: -48 : 48, -48 : 48, -48 : 48 N0.C0.D0.R1.S17: -48 : 48, -48 : 48, -48 : 48 STOP_RX_VREF_CENTER vrefLo vrefHi offset N0.C0.S00: -48 48 0 N0.C0.S01: -48 48 0 N0.C0.S02: -48 48 0 N0.C0.S03: -48 48 0 N0.C0.S04: -48 48 0 N0.C0.S05: -48 48 0 N0.C0.S06: -48 48 0 N0.C0.S07: -47 48 0 N0.C0.S08: -48 48 0 N0.C0.S09: -48 48 0 N0.C0.S10: -48 48 0 N0.C0.S11: -48 48 0 N0.C0.S12: -48 48 0 N0.C0.S13: -48 48 0 N0.C0.S14: -48 48 0 N0.C0.S15: -48 48 0 N0.C0.S16: -48 48 0 N0.C0.S17: -48 48 0 Rd Vref Centering - 359ms Tx Dq Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x07, 0x0000 N0: Get eye width N0.C0.D0.R0: High = 26 - Low = -27 N0.C0.D0.R1: High = 26 - Low = -26 N0.C0: Composite High = 26 - Composite Low = -26 N0: Low: -26 High: 26 N0: Offset = 0 N0: Eye width = 52 N0: Get eye height N0.C0.D0.R0: High = 30 - Low = -31 N0.C0.D0.R1: High = 30 - Low = -31 N0.C0: Composite High = 30 - Composite Low = -31 N0.C0.D0.R0: txVrefSafe = 0x54 N0.C0.D0.R1: txVrefSafe = 0x54 N0: Low: -31 High: 30 N0: Eye height = 61 N0: numerator: 0 N0: denominator: 238200 N0: vrefRatio: 852, vrefRatioSpec: 1100 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_TX_DQ_ADV N0.C0.D0.R0.S00: Truncated: 1 -> 0 N0.C0.D0.R0.S01: Truncated: 0 -> -1 N0.C0.D0.R0.S02: Truncated: 1 -> 0 N0.C0.D0.R0.S06: Truncated: 1 -> 0 N0.C0.D0.R0.S07: Truncated: 0 -> -1 N0.C0.D0.R0.S09: Truncated: 1 -> 0 N0.C0.D0.R0.S13: Truncated: 1 -> 0 Results for N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -21 -22 -22 -22 -22 -21 -22 -23 -20 -20 -21 -21 -22 -23 -22 -21 -22 -21 Right: 22 20 22 21 22 22 23 22 22 23 20 22 21 23 22 23 22 21 Vref offset: 14 Left: -23 -25 -23 -23 -24 -23 -24 -25 -24 -23 -23 -25 -24 -25 -24 -24 -24 -23 Right: 24 23 25 24 24 23 26 24 24 25 22 24 24 26 25 24 24 23 Vref offset: 7 Left: -26 -27 -25 -25 -27 -26 -27 -27 -26 -25 -25 -27 -26 -26 -25 -26 -27 -26 Right: 27 24 27 26 27 25 27 26 25 27 24 26 25 28 27 26 26 25 Vref offset: 0 Left: -28 -28 -27 -28 -28 -27 -28 -27 -27 -28 -28 -27 -27 -29 -27 -28 -28 -27 Right: 29 26 28 28 29 28 28 26 27 28 28 27 28 30 27 28 28 28 Vref offset: -7 Left: -27 -26 -24 -26 -27 -25 -26 -26 -25 -25 -25 -26 -26 -26 -25 -26 -26 -26 Right: 28 24 26 27 27 25 27 25 26 27 25 26 26 28 27 27 26 25 Vref offset: -14 Left: -23 -24 -23 -23 -24 -23 -23 -24 -23 -23 -23 -22 -24 -25 -24 -25 -23 -22 Right: 25 23 23 24 24 23 26 24 24 25 23 24 24 26 26 25 23 23 Vref offset: -21 Left: -21 -21 -21 -22 -21 -21 -21 -21 -20 -20 -21 -21 -22 -23 -22 -21 -21 -20 Right: 23 20 21 22 22 22 24 21 22 23 21 22 22 24 22 24 21 22 ------------------------------------------------------------------------------- Prev Pi: 89 109 71 135 170 227 186 204 150 93 112 75 137 173 230 189 207 155 New Pi: 89 108 71 135 170 227 186 203 150 93 112 75 137 173 230 189 207 155 Diff: 0 -1 0 0 0 0 0 -1 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1.S06: Truncated: 1 -> 0 N0.C0.D0.R1.S08: Truncated: 0 -> -1 N0.C0.D0.R1.S09: Truncated: 1 -> 0 N0.C0.D0.R1.S13: Truncated: 0 -> -1 Results for N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -22 -21 -22 -22 -23 -23 -20 -20 -21 -21 -22 -22 -22 -23 -22 -20 -22 -20 Right: 21 21 22 22 23 22 23 22 23 22 21 22 22 25 22 23 22 22 Vref offset: 14 Left: -24 -24 -24 -24 -26 -24 -23 -23 -24 -23 -23 -24 -24 -25 -23 -24 -24 -23 Right: 23 23 24 24 25 24 25 24 24 24 22 24 24 26 23 24 23 24 Vref offset: 7 Left: -27 -27 -26 -25 -28 -25 -26 -26 -26 -25 -27 -27 -26 -26 -25 -26 -28 -26 Right: 26 25 26 26 27 26 27 25 25 27 25 26 26 28 26 25 27 26 Vref offset: 0 Left: -27 -27 -28 -26 -28 -27 -27 -27 -27 -27 -27 -29 -27 -28 -27 -28 -27 -27 Right: 28 27 28 27 28 27 28 28 26 28 28 29 27 27 28 28 28 27 Vref offset: -7 Left: -24 -26 -25 -24 -27 -26 -26 -26 -26 -25 -25 -27 -25 -26 -25 -26 -24 -26 Right: 27 25 26 26 26 25 26 25 25 26 25 27 25 26 27 27 27 25 Vref offset: -14 Left: -22 -23 -24 -23 -24 -24 -23 -23 -22 -23 -22 -23 -23 -24 -23 -24 -22 -22 Right: 24 23 24 23 24 24 24 24 23 24 23 25 23 25 24 25 25 23 Vref offset: -21 Left: -21 -21 -22 -21 -22 -22 -21 -21 -20 -21 -21 -22 -21 -23 -21 -21 -21 -20 Right: 22 21 21 20 22 22 23 23 22 22 21 22 22 22 22 23 22 22 ------------------------------------------------------------------------------- Prev Pi: 90 108 72 134 171 224 185 204 153 92 113 77 138 174 229 188 210 154 New Pi: 90 108 72 134 171 224 185 204 152 92 113 77 138 173 229 188 210 154 Diff: 0 0 0 0 0 0 0 0 -1 0 0 0 0 -1 0 0 0 0 STOP_DATA_TX_DQ_ADV Tx Dq Adv - 578ms Rx Dq/Dqs Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x06, 0x0000 N0: Get eye width N0.C0.D0.R0: High = 25 - Low = -26 N0.C0.D0.R1: High = 23 - Low = -25 N0.C0: Composite High = 23 - Composite Low = -25 N0: Low: -25 High: 23 N0: Offset = -1 N0: Eye width = 48 N0: Get eye height N0.C0.D0.R0: High = 48 - Low = -48 N0.C0.D0.R1: High = 48 - Low = -48 N0.C0: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 240000 N0: vrefRatio: 800, vrefRatioSpec: 1200 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSN_ADV N0.C0.D0.R0.S01: Truncated: 1 -> 0 N0.C0.D0.R0.S02: Truncated: 1 -> 0 N0.C0.D0.R0.S03: Truncated: 2 -> 1 N0.C0.D0.R0.S04: Truncated: 1 -> 0 N0.C0.D0.R0.S05: Truncated: 1 -> -1 N0.C0.D0.R0.S06: Truncated: 1 -> -1 N0.C0.D0.R0.S07: Truncated: 2 -> 0 N0.C0.D0.R0.S08: Truncated: 1 -> 0 N0.C0.D0.R0.S09: Truncated: 1 -> 0 N0.C0.D0.R0.S10: Truncated: 1 -> 0 N0.C0.D0.R0.S11: Truncated: 1 -> 0 N0.C0.D0.R0.S12: Truncated: 1 -> 0 N0.C0.D0.R0.S14: Truncated: 1 -> -1 N0.C0.D0.R0.S15: Truncated: 1 -> 0 N0.C0.D0.R0.S16: Truncated: 2 -> 1 Results for N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -20 -22 -21 -18 -20 -21 -20 -22 -22 -21 -21 -22 -20 -21 -21 -21 -22 -21 Right: 24 25 24 24 23 24 23 27 24 25 24 25 22 25 24 23 27 25 Vref offset: 14 Left: -22 -24 -22 -21 -22 -24 -22 -24 -24 -23 -23 -23 -22 -22 -23 -24 -24 -24 Right: 25 26 25 25 25 25 24 27 27 26 25 26 24 26 26 25 28 27 Vref offset: 7 Left: -23 -26 -25 -23 -24 -25 -24 -26 -27 -24 -26 -25 -24 -24 -25 -25 -25 -25 Right: 25 27 27 26 25 26 25 29 28 27 27 27 26 27 27 26 28 27 Vref offset: 0 Left: -25 -27 -27 -24 -26 -27 -27 -28 -28 -26 -27 -28 -26 -26 -27 -27 -28 -27 Right: 27 28 27 27 26 26 26 29 28 27 28 28 27 28 26 28 30 29 Vref offset: -7 Left: -24 -25 -26 -23 -27 -25 -25 -26 -25 -24 -26 -26 -23 -27 -24 -25 -26 -26 Right: 26 27 28 26 28 26 26 29 27 27 28 27 27 28 26 28 30 28 Vref offset: -14 Left: -22 -24 -23 -20 -25 -23 -22 -23 -23 -22 -23 -24 -21 -25 -23 -24 -23 -24 Right: 25 26 26 24 26 25 24 27 25 25 25 26 24 27 23 26 27 27 Vref offset: -21 Left: -20 -21 -21 -17 -23 -20 -21 -20 -21 -21 -21 -23 -19 -23 -21 -22 -22 -22 Right: 24 25 25 24 25 24 23 26 24 24 24 25 23 26 22 25 27 25 ------------------------------------------------------------------------------- Prev Pi: 36 35 35 34 37 34 37 38 37 39 37 40 37 40 39 42 40 42 New Pi: 37 35 35 35 37 33 36 38 37 39 37 40 37 41 38 42 41 43 Diff: 1 0 0 1 0 -1 -1 0 0 0 0 0 0 1 -1 0 1 1 N0.C0.D0.R1.S00: Truncated: 2 -> 1 N0.C0.D0.R1.S02: Truncated: -1 -> -2 N0.C0.D0.R1.S03: Truncated: 0 -> -1 N0.C0.D0.R1.S04: Truncated: 2 -> 1 N0.C0.D0.R1.S05: Truncated: 0 -> -1 N0.C0.D0.R1.S06: Truncated: 2 -> 1 N0.C0.D0.R1.S07: Truncated: 0 -> -1 N0.C0.D0.R1.S08: Truncated: 2 -> 1 N0.C0.D0.R1.S09: Truncated: 1 -> 0 N0.C0.D0.R1.S10: Truncated: 1 -> 0 N0.C0.D0.R1.S11: Truncated: 0 -> -2 N0.C0.D0.R1.S12: Truncated: 1 -> -1 N0.C0.D0.R1.S13: Truncated: 2 -> 1 N0.C0.D0.R1.S14: Truncated: 0 -> -1 N0.C0.D0.R1.S15: Truncated: 1 -> 0 N0.C0.D0.R1.S16: Truncated: 1 -> 0 Results for N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -20 -22 -23 -22 -19 -19 -18 -21 -21 -21 -21 -23 -22 -20 -20 -19 -21 -22 Right: 24 25 21 23 23 21 23 24 27 26 24 24 25 25 22 24 24 27 Vref offset: 14 Left: -22 -24 -25 -24 -21 -21 -21 -24 -23 -23 -23 -25 -24 -22 -22 -22 -23 -23 Right: 25 26 23 24 25 23 24 25 28 27 25 24 26 26 23 25 26 28 Vref offset: 7 Left: -23 -25 -26 -26 -23 -24 -23 -26 -25 -25 -25 -26 -25 -23 -23 -24 -25 -25 Right: 27 27 25 25 27 24 26 25 29 28 27 25 27 27 25 26 26 28 Vref offset: 0 Left: -25 -26 -29 -27 -25 -25 -24 -27 -26 -27 -27 -29 -27 -25 -25 -25 -27 -26 Right: 28 28 26 25 27 24 26 26 29 28 28 26 26 27 24 26 28 30 Vref offset: -7 Left: -23 -24 -29 -26 -25 -24 -23 -26 -23 -26 -25 -26 -24 -26 -23 -25 -26 -26 Right: 28 27 26 25 28 25 26 26 29 27 27 26 27 28 23 27 27 29 Vref offset: -14 Left: -22 -23 -26 -23 -23 -22 -21 -22 -21 -24 -23 -24 -22 -23 -21 -23 -24 -25 Right: 26 26 24 24 27 23 25 25 27 26 25 25 26 27 22 26 25 28 Vref offset: -21 Left: -20 -19 -23 -21 -20 -19 -19 -20 -19 -21 -20 -22 -21 -22 -20 -22 -21 -22 Right: 25 25 22 23 25 22 23 23 25 26 24 24 24 26 21 24 24 26 ------------------------------------------------------------------------------- Prev Pi: 38 34 39 35 36 35 34 36 37 41 37 41 39 40 37 41 39 42 New Pi: 39 35 37 34 37 34 35 35 38 41 37 39 38 41 36 41 39 44 Diff: 1 1 -2 -1 1 -1 1 -1 1 0 0 -2 -1 1 -1 0 0 2 STOP_DATA_RX_DQSN_ADV N0: Get eye width N0.C0.D0.R0: High = 23 - Low = -25 N0.C0.D0.R1: High = 25 - Low = -25 N0.C0: Composite High = 23 - Composite Low = -25 N0: Low: -25 High: 23 N0: Offset = -1 N0: Eye width = 48 N0: Get eye height N0.C0.D0.R0: High = 48 - Low = -48 N0.C0.D0.R1: High = 48 - Low = -48 N0.C0: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 240000 N0: vrefRatio: 800, vrefRatioSpec: 1200 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSP_ADV N0.C0.D0.R0.S00: Truncated: 2 -> 1 N0.C0.D0.R0.S01: Truncated: 2 -> 1 N0.C0.D0.R0.S02: Truncated: 2 -> 1 N0.C0.D0.R0.S03: Truncated: 2 -> 1 N0.C0.D0.R0.S04: Truncated: 2 -> 1 N0.C0.D0.R0.S05: Truncated: 2 -> 1 N0.C0.D0.R0.S07: Truncated: 1 -> 0 N0.C0.D0.R0.S09: Truncated: 2 -> 1 N0.C0.D0.R0.S10: Truncated: 2 -> 1 N0.C0.D0.R0.S11: Truncated: 2 -> 1 N0.C0.D0.R0.S12: Truncated: 1 -> 0 N0.C0.D0.R0.S14: Truncated: 1 -> 0 N0.C0.D0.R0.S15: Truncated: 1 -> 0 N0.C0.D0.R0.S16: Truncated: 1 -> 0 N0.C0.D0.R0.S17: Truncated: 1 -> 0 Results for N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -21 -21 -21 -20 -21 -18 -20 -18 -21 -20 -21 -22 -22 -21 -20 -21 -20 -21 Right: 25 26 25 24 26 24 24 22 24 26 25 26 25 25 23 23 22 24 Vref offset: 14 Left: -23 -23 -23 -22 -22 -19 -22 -20 -22 -24 -23 -24 -23 -23 -22 -23 -21 -24 Right: 26 27 27 26 26 25 26 24 24 28 28 28 26 26 26 24 23 25 Vref offset: 7 Left: -25 -26 -24 -24 -24 -21 -23 -23 -25 -25 -25 -26 -25 -24 -24 -25 -22 -25 Right: 28 29 28 28 27 26 27 25 26 29 28 29 27 27 26 27 25 26 Vref offset: 0 Left: -26 -27 -25 -26 -26 -24 -24 -25 -25 -26 -27 -27 -26 -26 -25 -27 -24 -26 Right: 28 30 28 28 29 26 28 25 27 28 29 29 27 28 26 28 24 27 Vref offset: -7 Left: -24 -25 -25 -25 -27 -24 -24 -23 -24 -24 -25 -25 -24 -26 -24 -25 -22 -25 Right: 28 27 29 28 29 25 28 24 26 28 28 27 27 29 25 27 23 27 Vref offset: -14 Left: -22 -23 -23 -22 -24 -20 -22 -20 -22 -21 -23 -23 -23 -24 -22 -24 -20 -24 Right: 27 27 28 26 28 25 27 24 24 27 27 26 25 26 24 25 22 25 Vref offset: -21 Left: -20 -20 -21 -20 -22 -18 -20 -18 -20 -19 -21 -20 -21 -23 -21 -22 -19 -22 Right: 25 25 27 24 26 24 26 22 23 25 26 25 25 25 22 24 22 25 ------------------------------------------------------------------------------- Prev Pi: 38 37 39 38 39 35 39 36 39 41 39 44 41 42 38 44 39 43 New Pi: 39 38 40 39 40 36 41 36 40 42 40 45 41 43 38 44 39 43 Diff: 1 1 1 1 1 1 2 0 1 1 1 1 0 1 0 0 0 0 N0.C0.D0.R1.S01: Truncated: 1 -> 0 N0.C0.D0.R1.S02: Truncated: 2 -> 1 N0.C0.D0.R1.S03: Truncated: 2 -> 1 N0.C0.D0.R1.S04: Truncated: 1 -> 0 N0.C0.D0.R1.S05: Truncated: 2 -> 1 N0.C0.D0.R1.S07: Truncated: 2 -> 1 N0.C0.D0.R1.S08: Truncated: 1 -> 0 N0.C0.D0.R1.S09: Truncated: 1 -> 0 N0.C0.D0.R1.S10: Truncated: 2 -> 1 N0.C0.D0.R1.S11: Truncated: 2 -> 1 N0.C0.D0.R1.S14: Truncated: 2 -> 1 N0.C0.D0.R1.S15: Truncated: 0 -> -1 N0.C0.D0.R1.S16: Truncated: 2 -> 1 Results for N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -20 -20 -22 -18 -22 -20 -21 -20 -21 -21 -21 -21 -20 -22 -21 -21 -21 -21 Right: 23 25 25 24 25 25 24 24 23 25 25 26 22 23 27 22 26 23 Vref offset: 14 Left: -22 -22 -23 -20 -24 -21 -22 -22 -22 -23 -22 -24 -22 -24 -23 -24 -22 -23 Right: 24 27 25 25 25 27 24 27 24 25 27 28 25 24 28 23 27 24 Vref offset: 7 Left: -24 -24 -24 -22 -25 -23 -24 -24 -23 -25 -24 -25 -23 -25 -24 -26 -24 -25 Right: 26 28 29 26 27 28 27 28 26 26 28 30 26 27 30 26 28 25 Vref offset: 0 Left: -25 -26 -26 -24 -26 -26 -24 -27 -25 -27 -26 -27 -24 -27 -26 -27 -26 -26 Right: 27 27 29 27 27 29 27 29 26 27 28 29 27 27 29 26 28 26 Vref offset: -7 Left: -24 -25 -25 -23 -27 -26 -24 -24 -23 -25 -24 -25 -23 -27 -24 -26 -24 -25 Right: 25 26 28 27 26 29 26 27 24 26 27 29 25 26 29 25 28 25 Vref offset: -14 Left: -22 -22 -23 -20 -25 -24 -23 -22 -21 -23 -22 -23 -22 -25 -22 -25 -22 -23 Right: 24 25 27 25 25 25 26 26 23 25 26 26 24 26 27 25 27 24 Vref offset: -21 Left: -20 -20 -21 -18 -23 -21 -22 -20 -18 -20 -20 -20 -20 -24 -21 -23 -20 -21 Right: 23 24 25 23 25 25 25 25 22 24 23 26 23 24 27 23 26 23 ------------------------------------------------------------------------------- Prev Pi: 38 36 39 35 41 37 40 38 39 41 38 42 40 43 38 44 40 44 New Pi: 39 36 40 36 41 38 41 39 39 41 39 43 41 43 39 43 41 44 Diff: 1 0 1 1 0 1 1 1 0 0 1 1 1 0 1 -1 1 0 STOP_DATA_RX_DQSP_ADV Rx Dq/Dqs Adv - 1217ms Round Trip Optimization -- Started Checkpoint Code: Socket 0, 0xB7, 0x13, 0x0000 Round Trip Optimization - 0ms Display Training Results -- Started N0: START_TRAINING_REGISTER_DUMP START_DATA_XOVER CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 N0.C0: 48 19 17 21 21 53 23 46 16 50 19 53 20 48 15 53 START_DATA_REC_EN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 164 182 141 195 227 283 250 273 209 173 190 150 203 235 291 259 280 216 N0.C0.D0.R0: IO Latency = 8, Round Trip = 39 N0.C0.D0.R1: 164 189 142 201 229 286 255 274 212 171 198 151 210 236 292 261 283 220 N0.C0.D0.R1: IO Latency = 8, Round Trip = 39 START_DATA_RX_DQSP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 39 38 40 39 40 36 41 36 40 42 40 45 41 43 38 44 39 43 N0.C0.D0.R1: 39 36 40 36 41 38 41 39 39 41 39 43 41 43 39 43 41 44 START_DATA_RX_DQSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 37 35 35 35 37 33 36 38 37 39 37 40 37 41 38 42 41 43 N0.C0.D0.R1: 39 35 37 34 37 34 35 35 38 41 37 39 38 41 36 41 39 44 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0: t_cwl_adj = 0 N0.C0.D0.R0: 96 112 78 140 176 232 193 210 158 N0.C0.D0.R1: 96 114 80 140 177 231 192 212 158 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 89 108 71 135 170 227 186 203 150 93 112 75 137 173 230 189 207 155 N0.C0.D0.R1: 90 108 72 134 171 224 185 204 152 92 113 77 138 173 229 188 210 154 START_DATA_RX_VREF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0: 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 84 84 84 84 84 84 84 84 84 N0.C0.D0.R1: 84 84 84 84 84 84 84 84 84 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C0: 111 112 111 110 110 109 111 113 112 112 109 111 START_DATA_CLK 0 1 2 3 N0.C0: 3 0 126 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C0: 131 124 108 108 108 108 108 108 108 108 131 124 108 108 108 108 131 124 131 108 108 START_DATA_MRS MR0 MR1 MR2 MR3 MR4 MR5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 318 401 4D0 0 0 40 494 494 494 494 494 494 494 494 494 N0.C0.D0.R1: 318 401 4D0 0 0 40 494 494 494 494 494 494 494 494 494 START_DATA_RX_DQS_P_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6 2 3 0 4 1 4 0 2 0 0 1 2 1 1 0 4 1 3 0 2 1 1 0 1 1 0 1 3 0 0 1 3 1 0 2 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 1 0 1 0 1 2 0 3 2 5 0 4 3 2 2 0 0 2 0 1 0 4 1 2 1 0 0 2 4 0 0 0 2 0 1 0 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 1 3 0 5 1 4 0 3 1 0 2 3 1 2 0 6 1 3 0 4 3 4 0 3 1 0 4 2 0 0 1 3 0 0 1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 0 1 1 1 3 0 2 2 6 0 5 3 0 1 1 0 3 1 0 0 2 0 2 1 0 0 1 4 2 0 2 2 0 1 1 START_DATA_RX_DQS_N_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 1 3 0 6 2 3 0 2 0 0 0 2 1 2 0 5 2 4 0 4 1 2 0 2 1 0 1 4 1 0 2 3 1 0 1 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 0 0 0 3 4 0 3 1 4 0 2 3 1 1 0 1 3 0 0 0 1 0 1 1 0 0 2 4 1 0 1 2 1 1 0 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 3 0 3 0 5 0 3 0 2 1 0 2 3 1 1 0 4 1 3 0 2 2 3 0 4 2 0 3 3 1 0 1 4 0 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 0 0 0 0 2 0 2 2 6 0 3 5 0 2 1 0 2 1 0 0 2 0 2 1 0 0 1 3 1 0 1 3 1 0 1 START_DATA_TX_DQ_PER_BIT N0.C0.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 45 48 47 48 49 50 50 54 34 37 38 34 38 39 40 41 31 33 32 34 35 37 38 39 0 1 3 0 2 5 7 4 6 7 8 5 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 8 10 12 11 31 30 32 29 33 32 35 33 16 16 16 17 20 19 20 22 4 0 5 0 4 7 9 7 49 53 54 52 54 54 55 55 N0.C0.D0.R1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 46 49 47 47 48 51 50 54 37 39 40 34 39 41 40 41 32 36 34 35 37 39 37 41 0 2 4 63 3 5 6 5 6 8 9 6 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 8 10 10 10 30 27 31 26 32 31 33 32 15 17 15 15 21 18 18 21 6 4 7 1 7 9 9 8 51 52 54 51 53 55 55 54 START_DATA_CMD_VREF_CENTERING_OFFSETS N0.C0: 32 START_SENSE_AMP_TRAINING_OFFSETS BitSAmp for Channel 0 bit: 0 1 2 3 N0.C0: Nibble 0: 16 14 15 13 N0.C0: Nibble 1: 13 14 13 13 N0.C0: Nibble 2: 15 14 14 14 N0.C0: Nibble 3: 13 13 14 13 N0.C0: Nibble 4: 14 13 15 14 N0.C0: Nibble 5: 15 15 13 15 N0.C0: Nibble 6: 15 12 14 14 N0.C0: Nibble 7: 13 14 13 13 N0.C0: Nibble 8: 13 14 12 12 N0.C0: Nibble 9: 13 14 12 13 N0.C0: Nibble 10: 13 13 14 14 N0.C0: Nibble 11: 12 15 14 14 N0.C0: Nibble 12: 15 13 14 13 N0.C0: Nibble 13: 13 14 16 14 N0.C0: Nibble 14: 13 12 14 15 N0.C0: Nibble 15: 13 17 15 14 N0.C0: Nibble 16: 13 12 14 14 N0.C0: Nibble 17: 13 15 13 13 START_POWER_TRAINING_DUMP START_DATA_TX_IMODE 0 1 2 3 4 5 6 7 8 N0.C0.D0.R0: 15 15 15 15 15 15 15 15 15 N0.C0.D0.R1: 15 15 15 15 15 15 15 15 15 START_DATA_RX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C0.D0.R1: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_DRAM_DRVSTR N0.C0.D0.R0: 34 N0.C0.D0.R1: 34 START_DATA_TX_RON N0.C0: 43 START_DATA_WR_ODT N0.C0.D0.R0: 240 N0.C0.D0.R1: 240 START_DATA_RX_ODT N0.C0: 50 START_DATA_PARK_ODT N0.C0.D0.R0: 60 N0.C0.D0.R1: 60 START_DATA_NOM_ODT N0.C0.D0.R0: 240 N0.C0.D0.R1: 240 START_DATA_TX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C0.D0.R0: 8 2 6 0 8 4 0 6 0 8 2 6 0 8 4 0 6 0 N0.C0.D0.R1: 4 0 6 0 0 0 8 6 4 4 0 6 0 0 0 8 6 4 START_SWIZZLE_TRAINING_RESULTS Pattern 0 1 2 3 4 5 N0.C0: E400FE00 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4 START_COMP_REG_DUMP Ch COMP 0 1 2 3 4 5 6 7 8 0 DrvUp 37 37 37 37 37 37 37 37 37 0 DrvDn 33 33 33 33 33 33 33 33 33 Ch COMP 0 1 2 3 4 5 6 7 8 0 ODTUp 30 30 30 30 30 30 30 30 30 0 ODTDn 26 26 26 26 26 26 26 26 26 Ch COMP 0 1 2 3 4 5 6 7 8 0 Scomp 12 12 12 12 12 12 12 12 12 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 0 DrvUp 60 14 14 34 34 0 DrvDn 63 12 12 30 30 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 0 Scomp 12 21 21 12 12 N0: STOP_TRAINING_REGISTER_DUMP N0: STOP_TRAINING_REGISTER_DUMP Display Training Results - 1043ms Post-Training Initialization -- Started N0.C0.D0: dimmMtr: 0x001C514C N0.C0.D1: dimmMtr: 0x000F0000 N0.C0.D2: dimmMtr: 0x000F0000 N0.C1.D0: dimmMtr: 0x001F000C N0.C1.D1: dimmMtr: 0x000F000C N0.C1.D2: dimmMtr: 0x000F000C N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: (x10000) tck = 12500, tPDM_RD=15860, tPDM_WR=15860, tWRPRE=0, tRPRE=0, BL=80000, specMin=3 N0.C0: tRRDR = 1 N0.C0: tRRDD = 1 N0.C0: odtStretch = 0 N0.C0: tWWDR = 3, minWWDR = 3 N0.C0: odtStretch = 0 N0.C0: tWWDD = 3, minWWDD = 3 N0.C0: specMin = 3, tRWSR = 2 N0.C0: specMin = 3, tRWDR = 3 N0.C0: tRWDD = 3 N0.C0: odtStretch = 0 N0.C0: tWRDR = 1 N0.C0: odtStretch = 0 N0.C0: tWRDD = 1 Post-Training Initialization - 75ms Rank Margin Tool -- Started Checkpoint Code: Socket 0, 0xB7, 0x10, 0x0000 Rank Margin Tool - 0ms Fill BDAT Structure -- Started Fill BDAT Structure - 0ms Platform Restore NVDIMMs -- Started N0: PlatformRestoreNVDIMMs Platform Restore NVDIMMs - 2ms Platform Arm NVDIMMs -- Started N0: PlatformArmNVDIMMs Platform Arm NVDIMMs - 2ms Late Configuration -- Started Checkpoint Code: Socket 0, 0xB7, 0x11, 0x0000 N0: DRAM Maintenance Late Configuration - 2ms Initialize Throttling -- Started Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000 Initialize Throttling N0.C0.D0: Initialize DRAM RAPL N0: Initialize DRAM Phase Shedding Initialize Throttling - 10ms Advanced MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 Advanced MemTest - 0ms MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 MemTest - 1838ms MemInit -- Started Checkpoint Code: Socket 0, 0xBA, 0x00, 0x0000 MemInit - 934ms Check Ras Support After MemInit -- Started N0.C0.D0: dimmMtr: 0x001C514C N0.C0.D1: dimmMtr: 0x000F0000 N0.C0.D2: dimmMtr: 0x000F0000 N0.C1.D0: dimmMtr: 0x001F000C N0.C1.D1: dimmMtr: 0x000F000C N0.C1.D2: dimmMtr: 0x000F000C N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C Check Ras Support After MemInit - 36ms Switch to Normal Mode -- Started Checkpoint Code: Socket 0, 0xB7, 0x12, 0x0000 N0: MboxStatus: 0 PCU_MISC_CONFIG = 0x1000000 N0: MBoxStatus: 0 PCU_MISC_CONFIG = 0x0 Switch to Normal Mode - 8ms Initialize ADR -- Started No Pending Reset, clearing the ADR status bit Initialize ADR - 4ms Get NVRAM Data -- Started Get NVRAM Data - 0ms Initialize Memory Map -- Started Checkpoint Code: Socket 0, 0xBB, 0x00, 0x0000 N0.C0.D0: Memory Found! TAD setup HA 0 ----------- Memory Map Info ---------------- Socket XOR Config = Non-XOR mode Socket RAS Config = Channel Independent NUMA Config Socket Interleave Ways: 1 System Mem Size (64MB granularity): 0x80 SAD Table Rule Enable Limit Mode Ways Interleave List(right to left) ------------------------------------------------------------------- 0 1 0xA0 0 1 00000000 ----------- Socket Info ---------------- ----------- Socket 0 Socket Enabled Socket max DIMM pop count = 1 Socket mem size (64MB) = 0x80 ----------- TAD Info ---------------- TAD Table (Socket 0) Rule Enable Limit Mode Ch Ways --------------------------------------- Home Agent 0 0 1 0x20 0 1 TAD Interleave List Way Target Offset ChIndex 0 0 0x0 0 1 0 0x0 0 2 0 0x0 0 3 0 0x0 0 1 1 0xA0 0 1 TAD Interleave List Way Target Offset ChIndex 0 0 0x20 0 1 0 0x0 0 2 0 0x0 0 3 0 0x0 0 ----------- Channel Info ---------------- ----------- Channel 0 Channel Enabled Channel mem size (64MB) = 0x80 ----------- RIR Info ---------------- RIR Table (Socket 0, Channel 0) ---------------------------------------------- Rule Enable Limit(Ch Space) Ways 0 1 0x80 2 Rank Interleave List Way Target Offset 0 0 0 1 1 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 ----------- Channel 1 Channel not enabled ----------- Channel 2 Channel not enabled ----------- Channel 3 Channel not enabled ----------- Socket 1 Socket not enabled ----------- Socket 2 Socket not enabled ----------- Socket 3 Socket not enabled highMemBase: 0x40 highMemSize: 0x60 TOLM: 0x1F TOHM: 0x9F Initialize Memory Map - 168ms Set RAS Configuration -- Started Checkpoint Code: Socket 0, 0xBC, 0x00, 0x0000 Set RAS Config N0: Independent ch mode enabled N0: Patrol scrub enabled and started N0: Demand scrub enabled ECC is enabled Set RAS Configuration - 12ms Memory Late -- Started Memory Late - 0ms DIMM Information -- Started START_DIMMINFO_TABLE ====================================================================================== START_SOCKET_0_TABLE BDX Unknown - DE ====================================================================================== S| Channel 0 | Channel 1 | Channel 2 | Channel 3 | ====================================================================================== 0| DIMM: 7A01 | Not installed | Not installed | Not installed | | DRAM: Samsung | | | | | | | | | | 8GB(4Gbx8 1H DR) | | | | | DDR4 SODIMM R/C-G | | | | | 2400 11-11-11 | | | | | ww37 2017 | | | | |76.C355G.D340B | | | | |0x0000000000000000 | | | | | | | | | -------------------------------------------------------------------------------------- 1| Not installed | Not installed | Not installed | Not installed | -------------------------------------------------------------------------------------- STOP_SOCKET_0_TABLE ====================================================================================== ====================================================================================== | Socket 0 | Socket 1 | Socket 2 | Socket 3 | System | ====================================================================================== Active Memory | 8GB | N/A | N/A | N/A | 8GB | DDR Freq | | | | | DDR4-1600 | Ch0 CL-RCD-RP-CMD |11-11-11-1n | | | | | DDR Vdd | | | | | 1.20V | ECC Checking | | | | | On | CAP Checking | | | | | On | Patrol/Demand Scrub | | | | | On/On | RAS Mode | | | | | Indep | Xover Mode | | | | | 1:1 | Paging Policy | | | | | Adapt Open | Data Scrambling | | | | | On | CCMRC Revision | | | | | 00.50.00 | RC Revision | | | | | 01.82.00 | ====================================================================================== STOP_DIMMINFO_TABLE ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Platform DIMM Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Socket : 0 Channel : 0 ddr4Size : 128 volSize : 0 perSize : 0 blkSize : 0 Channel : 1 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 2 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 3 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 DIMM Information - 353ms Total MRC time = 31360ms Setting Last Boot Date = 384 days STOP_MRC_RUN Checkpoint Code: Socket 0, 0xBF, 0x00, 0x0000 nvram[0].ppin.hi: 0x8D9CD4DF, var[0].ppin.hi: 0x8D9CD4DF nvram[0].ppin.lo: 0xB60C4D61, var[0].ppin.lo: 0xB60C4D61 Install EFI Memory Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE MRC: lowMemBase:0 lowMemSize:20 MRC: highMemBase:40 highMemSize:60 TSEG Unaligned Size is 0x00800000 TSEG Aligned Size is 0x00800000 Low Memory Discovered at 0x00000000 - 0x7F800000 PeiInstallPeiMemory MemoryBegin 0x7F000000, MemoryLength 0x800000 TopOfHighMem 0x280000000 High Memory Discovered at 0x100000000 - 0x280000000 Save NVRAM restore data into Hob MRC status = 00000000 UMA: Memory retrain occurred during warm reset. Force ME FW reload. ME UMA: ------------- MePlatformPolicyPpi Dump Begin ------------- Revision : 0x2 DidEnabled : 0x1 DidTimeout : 0x0 DidInitStat : 0x0 ME UMA: ------------- MePlatformPolicyPpi Dump End ---------------- ME UMA: Entered ME DRAM Init Done procedure. ME UMA: MeUmaBase read: FFF80000 ME UMA: InitStat: 3 ME UMA: ME H_GS written: 1300FFFF ME UMA: HFS read before DID ACK: 0x000F0345 ME UMA: BiosAction = 0 MeDramInitDone Complete. Checking for reset... ME UMA: MeFwsts2 = 38006000. ME UMA: DID Ack was not received, no BIOS Action to process. Reset Requested: 0 Pipe Exit starting...Pipe Exit completed! Reset Requested: 0 Checking for Reset Requests ... None Continue with system BIOS POST ... mmCfgBase 80000000 QPI: CPU[0] bus = FF QPI: IIO[0] bus = 0 QPI: IIO[0] busbase = 0 Limit=FF QPI: IIO[0] IoBase = 0 IoLimit=FFFF QPI: IIO[0] IoApicBase = FEC00000 IoApicLimit=FEC3FFFF QPI: IIO[0] Mem32Base = 90000000 Mem32Limit=FBFFFFFF QPI: IIO[0] VtdBarAddress = FBFFC000 RcbaAddress=FBFFE000 PCI: IIO[0] NEW!PciResourceMem32Limit=FBFFBFFF QPI: CPU[1] is invalid QPI: IoApic[1] is invalid QPI: CPU[2] is invalid QPI: IoApic[2] is invalid QPI: CPU[3] is invalid QPI: IoApic[3] is invalid QPI: num of Cpus = 1 QPI: num of IIOs = 1 Node:0 BaseAddress:00000000 ElementSize:000000A0 Setting pam0_hienable = 3 Setting pam1_loenable = 3 Setting pam1_hienable = 3 Setting pam2_loenable = 3 Setting pam2_hienable = 3 Setting pam3_loenable = 3 Setting pam3_hienable = 3 Setting pam4_loenable = 3 Setting pam4_hienable = 3 Setting pam5_loenable = 3 Setting pam5_hienable = 3 Setting pam6_loenable = 3 Setting pam6_hienable = 3 PeimMemoryQpiInit END Temp Stack : BaseAddress=0xFE184000 Length=0x7C000 Temp Heap : BaseAddress=0xFE108000 Length=0x271F0 Total temporary memory: 1015808 bytes. temporary memory stack ever used: 481988 bytes. temporary memory heap used: 160240 bytes. Old Stack size 507904, New stack size 1048576 Heap Offset = 0x0 Stack Offset = 0x7F100000 Stack Hob: BaseAddress=0x7F000000 Length=0x100000 Loading PEIM at 0x0007F7F7190 EntryPoint=0x0007F7F814C Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFEFD008 Memory Discovered Notify invoked ... Loading PEIM at 0x0007F7F2188 EntryPoint=0x0007F7F29D0 Install PPI: EE4E5898-3914-4259-9D6E-DC7BD79403CF Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Loading PEIM at 0x0007F7E9000 EntryPoint=0x0007F7E96F8 Install PPI: 057A449A-1FDC-4C06-BFC9-F53F6A99BB92 Loading PEIM at 0x0007F7D4000 EntryPoint=0x0007F7D56B0 PowerStateAfterG3 Default has been overridden by UPD option to 0 Install PPI: A7CED760-C71C-4E1A-ACB1-89604D5216CB Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Loading PEIM at 0x0007F7C5000 EntryPoint=0x0007F7C6290 Install PPI: 0067835F-9A50-433A-8CBB-852078197814 Loading PEIM at 0x0007F782000 EntryPoint=0x0007F78FA90 IsocEn changed because QPI config. IsocEn =0 Bifurcation of the ConfigIOU1 (Port#3) for CBM will be updated to = 4 Bifurcation of the ConfigIOU2 (Port#1) for CBM will be updated to = 1 Install PPI: DDC3080A-2740-4EC2-9AA5-A0ADEFD6FF9C Socket 0 does not support uplink port! Update iioErrPinDatReg = 7 Program Uniphy recipe Revision 4.00 Program RX Recipe values Start. B0 D6 F0 O30760h = 0x55 B0 D6 F1 O31760h = 0xAAAA B0 D7 F0 O38760h = 0xAAAAAAAA B0 D6 F0 O30710h = 0x208 B0 D6 F1 O31710h = 0x208208 B0 D7 F0 O38710h = 0x8208208 B0 D7 F0 O38714h = 0x8208 B0 D6 F0 O30708h = 0x410 B0 D6 F1 O31708h = 0x410410 B0 D7 F0 O38708h = 0x10410410 B0 D7 F0 O3870Ch = 0x10410 B0 D6 F0 O30704h = 0x12 B0 D6 F1 O31704h = 0x492 B0 D7 F0 O38704h = 0x492492 B0 D6 F0 O30700h = 0x24 B0 D6 F1 O31700h = 0x924 B0 D7 F0 O38700h = 0x924924 B0 D6 F0 O30730h = 0x0 B0 D6 F1 O31730h = 0x0 B0 D7 F0 O38730h = 0x0 B0 D6 F0 O30734h = 0x0 B0 D6 F1 O31734h = 0x0 B0 D7 F0 O38734h = 0x0 B0 D7 F0 O38738h = 0x0 B0 D6 F0 O30A50h = 0x3 B0 D6 F1 O31A50h = 0xF B0 D7 F0 O38A50h = 0xFF B0 D6 F0 O30A60h = 0x0 B0 D6 F1 O31A60h = 0x0 B0 D7 F0 O38A60h = 0x0 B0 D6 F1 O31A64h = 0xAA B0 D7 F0 O38A64h = 0xAAAA B0 D6 F0 O30788h = 0xAA B0 D6 F1 O31788h = 0xAAAA B0 D7 F0 O38788h = 0xAAAAAAAA B0 D6 F0 O30780h = 0xA B0 D6 F1 O31780h = 0xAA B0 D7 F0 O38780h = 0xAAAA B0 D6 F0 O30790h = 0xF B0 D6 F1 O31790h = 0xFF B0 D7 F0 O38790h = 0xFFFF B0 D6 F0 O306ECh = 0x42108 B0 D6 F1 O316ECh = 0x10842108 B0 D6 F1 O316F0h = 0x108 B0 D7 F0 O386ECh = 0x10842108 B0 D7 F0 O386F0h = 0x10842108 B0 D7 F0 O386F4h = 0x42108 B0 D6 F1 O316E0h = 0x16B5AD6B B0 D6 F1 O316E4h = 0x16B B0 D7 F0 O386E0h = 0x16B5AD6B B0 D7 F0 O386E4h = 0x16B5AD6B B0 D7 F0 O386E8h = 0x5AD6B B0 D6 F0 O307B0h = 0xFF B0 D6 F1 O317B0h = 0xFFFF B0 D7 F0 O387B0h = 0xFFFFFFFF B0 D6 F0 O30798h = 0xF B0 D6 F1 O31798h = 0xFF B0 D7 F0 O38798h = 0xFFFF B0 D6 F0 O30794h = 0x0 B0 D6 F1 O31794h = 0x0 B0 D7 F0 O38794h = 0x0 B0 D6 F0 O307A0h = 0x0 B0 D6 F1 O317A0h = 0x0 B0 D7 F0 O387A0h = 0x0 B0 D7 F0 O387A4h = 0x0 B0 D6 F0 O306C8h = 0x5 B0 D6 F1 O316C8h = 0x55 B0 D7 F0 O386C8h = 0x5555 B0 D6 F0 O306CCh = 0x3 B0 D6 F1 O316CCh = 0xF B0 D7 F0 O386CCh = 0xFF B0 D6 F7 O37650h = 0xC B0 D6 F0 O306ACh = 0xF B0 D6 F1 O316ACh = 0xFF B0 D7 F0 O386ACh = 0xFFFF B0 D6 F0 O306A0h = 0xFF B0 D6 F1 O316A0h = 0xFFFF B0 D7 F0 O386A0h = 0xFFFFFFFF B0 D6 F1 O31A88h = 0x5555 B0 D7 F0 O38A88h = 0x55555555 B0 D6 F0 O30A8Ch = 0x55 B0 D6 F1 O31A8Ch = 0x5555 B0 D7 F0 O38A8Ch = 0x55555555 B0 D6 F1 O31A90h = 0xBBBB B0 D7 F0 O38A90h = 0xBBBBBBBB B0 D6 F0 O30840h = 0x1EF B0 D6 F1 O31840h = 0x5AD6B B0 D7 F0 O38840h = 0x16B5AD6B B0 D7 F0 O38844h = 0x16B B0 D6 F0 O30838h = 0x16B B0 D6 F1 O31838h = 0x9CE73 B0 D7 F0 O38838h = 0x2739CE73 B0 D7 F0 O3883Ch = 0x273 B0 D6 F7 O37644h = 0x238100 B0 D6 F7 O37648h = 0x14000200 B0 D6 F7 O37628h = 0x12 B0 D6 F7 O37638h = 0x132 B0 D6 F7 O37614h = 0x202C000 B0 D6 F7 O3760Ch = 0xB B0 D6 F7 O37608h = 0x5000010 B0 D6 F7 O37634h = 0x24010 B0 D6 F7 O37654h = 0x1 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O306B0h = 0x0 B0 D6 F1 O316B0h = 0x0 B0 D7 F0 O386B0h = 0x0 B0 D7 F0 O386B4h = 0x0 B0 D1 F0 O825Ch = 0x2777 B0 D1 F1 O925Ch = 0x2777 B0 D3 F0 O1825Ch = 0x2777 B0 D3 F1 O1925Ch = 0x2777 B0 D3 F2 O1A25Ch = 0x2777 B0 D3 F3 O1B25Ch = 0x2777 B0 D6 F0 O307C0h = 0x36 B0 D6 F1 O317C0h = 0xDB6 B0 D7 F0 O387C0h = 0xDB6DB6 B0 D6 F0 O30480h = 0xAE0449E2 B0 D6 F1 O31480h = 0xAE0449E2 B0 D7 F0 O38480h = 0xAE0449E2 B0 D6 F0 O30464h = 0x70BFE3 B0 D6 F1 O31464h = 0x70BFE3 B0 D7 F0 O38464h = 0x70BFE3 B0 D6 F1 O31464h = 0x73FFE3 B0 D7 F0 O38464h = 0x73FFE3 B0 D6 F0 O30490h = 0x4 B0 D6 F1 O31490h = 0x4 B0 D6 F2 O32490h = 0x4 B0 D7 F0 O38490h = 0x4 B0 D7 F1 O39490h = 0x4 B0 D7 F2 O3A490h = 0x4 B0 D7 F3 O3B490h = 0x4 B0 D6 F0 O30B04h = 0x48087185 B0 D6 F1 O31B04h = 0x48006181 B0 D7 F0 O38B04h = 0x48006181 B0 D6 F0 O303F4h = 0x8A340C10 B0 D6 F1 O313F4h = 0x8A340C10 B0 D7 F0 O383F4h = 0x8A340C10 B0 D6 F0 O3048Ch = 0x2120000 B0 D6 F1 O3148Ch = 0x2020000 B0 D7 F0 O3848Ch = 0x2020000 B0 D6 F0 O304C4h = 0x10083 B0 D6 F1 O314C4h = 0x10083 B0 D7 F0 O384C4h = 0x10083 B0 D6 F1 O3139Ch = 0x641000 B0 D6 F2 O3239Ch = 0x641000 B0 D7 F0 O3839Ch = 0x641000 B0 D7 F1 O3939Ch = 0x641000 B0 D7 F2 O3A39Ch = 0x641000 B0 D7 F3 O3B39Ch = 0x641000 B0 D6 F1 O313F0h = 0x3C002000 B0 D7 F0 O383F0h = 0x3C002000 B0 D6 F1 O313FCh = 0x2 B0 D7 F0 O383FCh = 0x2 B0 D6 F1 O313CCh = 0x1000480 B0 D6 F2 O323CCh = 0x1000480 B0 D7 F0 O383CCh = 0x1000480 B0 D7 F1 O393CCh = 0x1000480 B0 D7 F2 O3A3CCh = 0x1000480 B0 D7 F3 O3B3CCh = 0x1000480 B0 D6 F1 O31438h = 0x2057F B0 D7 F0 O38438h = 0x2057F B0 D6 F1 O31B24h = 0x10011 B0 D7 F0 O38B24h = 0x10011 Program RX Recipe values End. Gen3: Gen3PrelinkOverride(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) PcieLinkTrainingInit at device scanning... IIO=0, IOU2=1. IIO=0, IOU0=3. IIO=0, IOU1=4. DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link Down! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! Gen3: Gen3Override(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Socket:[0] Port:[1] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Socket:[0] Port:[7] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) Program WA 4986406 Skt[0], D[1]:F[0] : Link Down , WA not required! Skt[0], D[3]:F[0] : Link Down , WA not required! DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link Down! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! DMI IIOInitPhase1... Initialize IIO:0 PCIE port:1 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:2... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:3 Func:0... PciEarlyInit at device scanning... DMI IIOInitPhase2... Enabling PCIE Dev:1 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 1 ASPM configured as 7 Vendor specific pcie Link Init port:2 Func0... Vendor specific pcie Link Init port:2 Func2... Enabling PCIE Dev:3 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 7 ASPM configured as 7 DMI IIOInitPhase3... DMI Link Retrain() DMI speed is 2.5Gb/s (Gen1) PciPostInit port:1 Func0... PciPostInit port:2 Func0... PciPostInit port:2 Func2... PciPostInit port:3 Func0... Initialize IIO[0] IOxAPIC... IIO[0] IOxAPIC Base=FEC01000 IIO[0] TOMMIOL_OB = FEF00000 VT-d Chipset Initialization for IIO0 ... Vt-D base address : 0x7F130675FBFFC000 VtDGenCtrlReg : 0x000080A8 VtDIsoCtrlReg : 0x00000001 Non-Iso Engine CapReg : 0x08D2078C106F0466 Non-Iso Engine ExtCapReg : 0x0000000000F020DF IIOMISCCTRL for IIO 0 = 0x42030170 Initializing NTB for SKT0 setup PPD 0 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Calling IioClockDisables: Socket=0 IioClockDisables: Socket=0, Port=0 IioClockDisables: Data Link Active or skipped for D0 : F0 IioClockDisables: DisableBitMap=CEE0000 IioClockDisables: Socket=0, Port=1 IioClockDisables: Socket=0, Port=2 IioClockDisables: Socket=0, Port=3 IioClockDisables: Data Link Active or skipped for D2 : F0 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=4 IioClockDisables: Data Link Active or skipped for D2 : F1 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=5 IioClockDisables: Data Link Active or skipped for D2 : F2 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=6 IioClockDisables: Data Link Active or skipped for D2 : F3 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=7 IioClockDisables: Socket=0, Port=8 IioClockDisables: Socket=0, Port=9 IioClockDisables: Socket=0, Port=10 IIO Port/Clocks Powering down: Socket=0, Disable Bit Map=80220000 IioInit Secure the Platform (TXT).. IioInit PCIe device hide.. Bus=255, Device=1, Function=1 is hidden. Bus=255, Device=2, Function=1 is hidden. Bus=255, Device=2, Function=3 is hidden. Bus=255, Device=3, Function=1 is hidden. Bus=255, Device=3, Function=2 is hidden. Bus=255, Device=3, Function=3 is hidden. Skt[0], D[1]:F[0] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link Down! Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F771000 EntryPoint=0x0007F7722C0 Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Loading PEIM at 0x0007F766000 EntryPoint=0x0007F766ADC [HECI-0] VID-DID: 8086-8C3A Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F751000 EntryPoint=0x0007F7535E4 InstallPchInitPpi() - Start Rcba needs to be programmed before here PchMiscEarlyInit() - Start PchMiscEarlyInit() - End Install PPI: ED097352-9041-445A-80B6-B29D509E8845 Install PPI: 09EA894A-BE0D-4230-A003-EDC693B48E95 Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7F75461D PchInitialize() - Start PchSataInit() - Start PchSataInit() - End [MPHY] Creating HOB to adjust Hsio settings from DXE, if required. [MPHY] SystemConfiguration.MeMphyDebugEnableSurvivabilityTable:0 [MPHY] SystemConfiguration.MeMphyDebugCorruptEndpoints:0 [MPHY] Suppress passing the expected ChipsetInit table to the DXE code, and further on to ME Unsupported PCH Stepping for PchDmiHsio PchInitialize() - End Install PPI: 1EDCBDF9-FFC6-4BD4-94F6-195D1DE17056 InstallPchInitPpi() - End Loading PEIM at 0x0007F740000 EntryPoint=0x0007F7417DC TempMmioBase = 90000000 TempMmioLimit = FBFFFFFF TempIoBase = 1000 TempIoLimit = FFFF XHCI (14h) = 90000000...90003000 (00003000) EHCI (1Dh) = 90003000...90003400 (00000400) EHCI2 (1Ah) = 90003400...90003800 (00000400) SATA (1Fh.2) [AHCI] = 90003800...90004800 (00001000) PCI Root Port[0] Status from UPD = 1 PCI Root Port[1] Status from UPD = 1 PCI Root Port[2] Status from UPD = 1 PCI Root Port[3] Status from UPD = 1 PCI Root Port[4] Status from UPD = 1 PCI Root Port[5] Status from UPD = 1 PCI Root Port[6] Status from UPD = 1 PCI Root Port[7] Status from UPD = 1 Cpu Type= 0x56, Cpu Stepping= 0x3 Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Number of Active Cores / Threads = 2 / 2 :::: CapId5 = 6000041, PlatformInfo->CpuData.SkuSlices = 41 :::: CapId4 = 24080F03, PlatformInfo->CpuData.CpuPCPSInfo = 30002 Socket Present BitMap, mmCfgBase, dimmTypePresent, BoardId, CpuType 1, 80000000, 7F130DDE, 0 56 EFI_PPM_STRUCT size: 166 :: !!! PPM Revision: Major:00Minor:01Rev:0000!!!. :: Reading MSR_TURBO_POWER_LIMIT (610) =4380C8 0 :: Reading Socket = 0, CSR_TURBO_POWER_LIMIT=0 0 :: Wrote Socket = 0, CSR_PCIE_ILTR_OVRD=0 Program FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE as 100 (39) Detected Boot Mode 0 Detected 2 CPU threads Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Loading PEIM at 0x0007F717000 EntryPoint=0x0007F7181CC PchInitEntryPoint() Start PCH Device: ------------- RCBA 0xFED1C000 PmBase 0x400 GpioBase 0x500 ------------- InitializePchDevice() Start ChipsetInitSettingsCheck() Start ConfigureMiscPm() Start ConfigureMiscPm() End ConfigureDmi() Start ConfigureDmi() End ConfigureMiscItems() Start ConfigureMiscItems() End ConfigureLan() Start LAN can be enabled or disabled as SPI is in Descriptor Mode. ConfigureLan() End ConfigureUsb() Start CommonUsbInit() - Start CommonUsbInit() - End ConfigureUsb() End PchInitRootPorts() Start PCI Root Port[0] Status = 1 PCI Root Port[1] Status = 1 PCI Root Port[2] Status = 1 PCI Root Port[3] Status = 1 PCI Root Port[4] Status = 1 PCI Root Port[5] Status = 1 PCI Root Port[6] Status = 1 PCI Root Port[7] Status = 1 PCI Function 1 enabled Root Port 1 device enabled. RpEnableMask: 0x1D PCI Function 2 disabled as specified in the Fuse Straps PCI Function 3 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 4 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 5 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 6 disabled as specified in the Fuse Straps PCI Function 7 disabled as specified in the Fuse Straps PCI Function 8 disabled as specified in the Fuse Straps PCH PCI Root Port Clock Gating is 1 PchInitRootPorts() End ConfigureSata() Start ConfigureSata() End ConfigureDisplay() Start ConfigureDisplay() End PCH PCIe Function Disable Register = 2FE0001. ConfigureClockGating() Start ConfigureClockGating() End ConfigureIoApic() Start ConfigureIoApic() End ProgramSvidSid() Start ProgramSvidSid() End Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B InitializePchDevice() End PchInitEntryPoint() End Loading PEIM at 0x0007F70C000 EntryPoint=0x0007F70CFBC [SPS] DXE PHASE [SPS] Getting Info from PEI [SPS] Looking for SPS HOB info from PEI [SPS] HOB: flow 1, feature set 0x2106, pwr opt boot 0, cores2disable 0 [HECI-0] VID-DID: 8086-8C3A [SPS] Sending PCH temperature reporting configuration to ME [SPS] PCH Temperatur Reporting Interval: 0x00FA [SPS] PCH Temperatur Maximum Low Power Interval: 0x03E8 [HECI-0] Send msg: 80060020 [HECI-0] Got msg: 80040020 [SPS] SiliconEnabling Mode Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F701000 EntryPoint=0x0007F701C58 DEBUG:::: IioDmiInitPeiEntryPoint() Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7F701ED0 PchDmiGen2Prog() Start PchDmiGen2Prog() End DEBUG:::: DmiVc1 = 0 ; DmiVcp = 0 ; DmiVcm = 0 Register PPI Notify: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Notify: PPI Guid: 1E2ACC41-E26A-483D-AFC7-A056C34E087B, Peim notify entry point: 7F702781 DEBUG:::: IioSouthComplexPeiInit() Enable/disable the SC CBDMA and GbE ports in the IIO IOSF bridge...(0,2,0,0x190) = 0x33 DXE IPL Entry FSP HOB is located at 0x7F100000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 FSP is waiting for NOTIFY romstage_main_continue status: 0 hob_list_ptr: 7f100000 FSP Status: 0x0 CBMEM: IMD: root @ 7efff000 254 entries. IMD: root @ 7effec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 9100 size c453 coreboot-coreboot-unknown Wed Jan 3 06:02:08 UTC 2018 ramstage starting... Moving GDT to 7effe9e0...ok BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0 CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 3c80 size 5400 microcode: sig=0x50663 pf=0x10 revision=0x700000e CPUID: 00050663 Cores: 2 Stepping: V2 Revision ID: 05 msr(17) = 0010000000000000 msr(ce) = 20080833f2810c00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 29408 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 6) DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:00.0 [8086/6f00] ops fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.1 PCI: 00:00.0 [8086/6f00] enabled Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0xe0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/6f02] enabled Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0xe0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [8086/6f04] enabled Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0xe0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [8086/6f06] enabled Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0xe0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/6f08] enabled PCI: 00:05.0 [8086/6f28] enabled PCI: 00:05.1 [8086/6f29] enabled PCI: 00:05.2 [8086/6f2a] enabled PCI: 00:05.4 [8086/6f2c] enabled PCI: 00:05.6 [8086/6f39] enabled PCI: 00:06.0 [8086/6f10] enabled PCI: 00:06.1 [8086/6f11] enabled PCI: 00:06.2 [8086/6f12] enabled PCI: 00:06.3 [8086/6f13] enabled PCI: 00:06.4 [8086/6f14] enabled PCI: 00:06.5 [8086/6f15] enabled PCI: 00:06.6 [8086/6f16] enabled PCI: 00:06.7 [8086/6f17] enabled PCI: 00:07.0 [8086/6f18] enabled PCI: 00:07.1 [8086/6f19] enabled PCI: 00:07.2 [8086/6f1a] enabled PCI: 00:07.3 [8086/6f1b] enabled PCI: 00:07.4 [8086/6f1c] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:14.0 [8086/8c31] enabled PCI: 00:16.0 [8086/8c3a] enabled PCI: 00:16.1 [8086/8c3b] enabled PCI: 00:16.2 [8086/8c3c] enabled PCI: 00:16.3 [8086/8c3d] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:19.0 not found, disabling it. PCI: 00:1a.0 [8086/8c2d] enabled PCI: 00:1b.0 [8086/8c20] enabled Capability: type 0x10 @ 0x40 Capability: type 0x05 @ 0x80 Capability: type 0x0d @ 0x90 Capability: type 0x01 @ 0xa0 Capability: type 0x10 @ 0x40 PCI: 00:1c.0 subordinate bus PCI Express PCI: 00:1c.0 [8086/8c10] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1d.0 [8086/8c26] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.0 [8086/8c54] bus ops PCI: 00:1f.0 [8086/8c54] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.2 [8086/8c02] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/8c22] enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:1f.5 not found, disabling it. PCI: 00:1f.6 [8086/8c24] enabled PCI: 00:01.0 scanning... do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:01.0 took 9042 usecs PCI: 00:02.0 scanning... do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [8086/6f50] enabled PCI: 02:00.1 [8086/6f51] enabled PCI: 02:00.2 [8086/6f52] enabled PCI: 02:00.3 [8086/6f53] enabled Capability: type 0x10 @ 0x40 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x10 @ 0x40 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x10 @ 0x40 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x10 @ 0x40 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 scan_bus: scanning of bus PCI: 00:02.0 took 68849 usecs PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/15ab] enabled PCI: 03:00.1 [8086/15ab] enabled Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x0d @ 0x40 Capability: type 0x05 @ 0x60 Capability: type 0x10 @ 0x90 scan_bus: scanning of bus PCI: 00:02.2 took 56409 usecs PCI: 00:03.0 scanning... do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 04 scan_bus: scanning of bus PCI: 00:03.0 took 9041 usecs PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [8086/1538] enabled Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x11 @ 0x70 Capability: type 0x10 @ 0xa0 Capability: type 0x10 @ 0x40 scan_bus: scanning of bus PCI: 00:1c.0 took 26940 usecs PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9028 usecs PCI: 00:1f.3 scanning... scan_generic_bus for PCI: 00:1f.3 scan_generic_bus for PCI: 00:1f.3 done scan_bus: scanning of bus PCI: 00:1f.3 took 9805 usecs scan_bus: scanning of bus DOMAIN: 0000 took 546113 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 578524 usecs done FspNotify(EnumInitPhaseAfterPciEnumeration) FSP Got Notification. Notification Value : 0x00000020 FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F799A9B Found the CBDMA on bus:2 Found the GbE on bus:3 BDF=2,0,0 - CB_BAR=0x0 CB BAR not initialized! CBDMA[0].version=0x33 Enable IIO[0] IOxAPIC Hide devices in Bus:255 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F7417E7 FSP Notification Handler Returns : 0x00000000 Returned from FspNotify(EnumInitPhaseAfterPciEnumeration) BS: BS_DEV_ENUMERATE times (us): entry 0 run 652893 exit 62193 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 fsp_mem_base: 0x7f000000 fsp_mem_len: 0x00800000 tseg_base: 0x7f800000 tseg_len: 0x00800000 highmem_size: 0x00000001 80000000 tolm: 0x80000000 Top of system low memory: 0x80000000 FSP memory location: 0x7f000000 (size: 8M) tseg: 0x7f800000 (size: 0x00800000) Available memory above 4GB: 6144M Adding PCIe config bar base=0x80000000 size=0x10000000 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:02.2 read_resources bus 3 link: 0 PCI: 00:02.2 read_resources bus 3 link: 0 done PCI: 00:03.0 read_resources bus 4 link: 0 PCI: 00:03.0 read_resources bus 4 link: 0 done PCI: 00:05.6 register 10(ffffffff), read-only ignoring it PCI: 00:05.6 register 14(ffffffff), read-only ignoring it PCI: 00:05.6 register 18(ffffffff), read-only ignoring it PCI: 00:05.6 register 1c(ffffffff), read-only ignoring it PCI: 00:05.6 register 20(ffffffff), read-only ignoring it PCI: 00:05.6 register 24(ffffffff), read-only ignoring it PCI: 00:05.6 register 30(ffffffff), read-only ignoring it PCI: 00:06.0 register 10(ffffffff), read-only ignoring it PCI: 00:06.0 register 14(ffffffff), read-only ignoring it PCI: 00:06.0 register 18(ffffffff), read-only ignoring it PCI: 00:06.0 register 1c(ffffffff), read-only ignoring it PCI: 00:06.0 register 20(ffffffff), read-only ignoring it PCI: 00:06.0 register 24(ffffffff), read-only ignoring it PCI: 00:06.0 register 30(ffffffff), read-only ignoring it PCI: 00:06.1 register 10(ffffffff), read-only ignoring it PCI: 00:06.1 register 14(ffffffff), read-only ignoring it PCI: 00:06.1 register 18(ffffffff), read-only ignoring it PCI: 00:06.1 register 1c(ffffffff), read-only ignoring it PCI: 00:06.1 register 20(ffffffff), read-only ignoring it PCI: 00:06.1 register 24(ffffffff), read-only ignoring it PCI: 00:06.1 register 30(ffffffff), read-only ignoring it PCI: 00:06.2 register 10(ffffffff), read-only ignoring it PCI: 00:06.2 register 14(ffffffff), read-only ignoring it PCI: 00:06.2 register 18(ffffffff), read-only ignoring it PCI: 00:06.2 register 1c(ffffffff), read-only ignoring it PCI: 00:06.2 register 20(ffffffff), read-only ignoring it PCI: 00:06.2 register 24(ffffffff), read-only ignoring it PCI: 00:06.2 register 30(ffffffff), read-only ignoring it PCI: 00:06.3 register 10(ffffffff), read-only ignoring it PCI: 00:06.3 register 14(ffffffff), read-only ignoring it PCI: 00:06.3 register 18(ffffffff), read-only ignoring it PCI: 00:06.3 register 1c(ffffffff), read-only ignoring it PCI: 00:06.3 register 20(ffffffff), read-only ignoring it PCI: 00:06.3 register 24(ffffffff), read-only ignoring it PCI: 00:06.3 register 30(ffffffff), read-only ignoring it PCI: 00:06.4 register 10(ffffffff), read-only ignoring it PCI: 00:06.4 register 14(ffffffff), read-only ignoring it PCI: 00:06.4 register 18(ffffffff), read-only ignoring it PCI: 00:06.4 register 1c(ffffffff), read-only ignoring it PCI: 00:06.4 register 20(ffffffff), read-only ignoring it PCI: 00:06.4 register 24(ffffffff), read-only ignoring it PCI: 00:06.4 register 30(ffffffff), read-only ignoring it PCI: 00:06.5 register 10(ffffffff), read-only ignoring it PCI: 00:06.5 register 14(ffffffff), read-only ignoring it PCI: 00:06.5 register 18(ffffffff), read-only ignoring it PCI: 00:06.5 register 1c(ffffffff), read-only ignoring it PCI: 00:06.5 register 20(ffffffff), read-only ignoring it PCI: 00:06.5 register 24(ffffffff), read-only ignoring it PCI: 00:06.5 register 30(ffffffff), read-only ignoring it PCI: 00:06.6 register 10(ffffffff), read-only ignoring it PCI: 00:06.6 register 14(ffffffff), read-only ignoring it PCI: 00:06.6 register 18(ffffffff), read-only ignoring it PCI: 00:06.6 register 1c(ffffffff), read-only ignoring it PCI: 00:06.6 register 20(ffffffff), read-only ignoring it PCI: 00:06.6 register 24(ffffffff), read-only ignoring it PCI: 00:06.6 register 30(ffffffff), read-only ignoring it PCI: 00:06.7 register 10(ffffffff), read-only ignoring it PCI: 00:06.7 register 14(ffffffff), read-only ignoring it PCI: 00:06.7 register 18(ffffffff), read-only ignoring it PCI: 00:06.7 register 1c(ffffffff), read-only ignoring it PCI: 00:06.7 register 20(ffffffff), read-only ignoring it PCI: 00:06.7 register 24(ffffffff), read-only ignoring it PCI: 00:06.7 register 30(ffffffff), read-only ignoring it PCI: 00:07.0 register 10(ffffffff), read-only ignoring it PCI: 00:07.0 register 14(ffffffff), read-only ignoring it PCI: 00:07.0 register 18(ffffffff), read-only ignoring it PCI: 00:07.0 register 1c(ffffffff), read-only ignoring it PCI: 00:07.0 register 20(ffffffff), read-only ignoring it PCI: 00:07.0 register 24(ffffffff), read-only ignoring it PCI: 00:07.0 register 30(ffffffff), read-only ignoring it PCI: 00:07.1 register 10(ffffffff), read-only ignoring it PCI: 00:07.1 register 14(ffffffff), read-only ignoring it PCI: 00:07.1 register 18(ffffffff), read-only ignoring it PCI: 00:07.1 register 1c(ffffffff), read-only ignoring it PCI: 00:07.1 register 20(ffffffff), read-only ignoring it PCI: 00:07.1 register 24(ffffffff), read-only ignoring it PCI: 00:07.1 register 30(ffffffff), read-only ignoring it PCI: 00:07.2 register 10(ffffffff), read-only ignoring it PCI: 00:07.2 register 14(ffffffff), read-only ignoring it PCI: 00:07.2 register 18(ffffffff), read-only ignoring it PCI: 00:07.2 register 1c(ffffffff), read-only ignoring it PCI: 00:07.2 register 20(ffffffff), read-only ignoring it PCI: 00:07.2 register 24(ffffffff), read-only ignoring it PCI: 00:07.2 register 30(ffffffff), read-only ignoring it PCI: 00:07.3 register 10(ffffffff), read-only ignoring it PCI: 00:07.3 register 14(ffffffff), read-only ignoring it PCI: 00:07.3 register 18(ffffffff), read-only ignoring it PCI: 00:07.3 register 1c(ffffffff), read-only ignoring it PCI: 00:07.3 register 20(ffffffff), read-only ignoring it PCI: 00:07.3 register 24(ffffffff), read-only ignoring it PCI: 00:07.3 register 30(ffffffff), read-only ignoring it PCI: 00:07.4 register 10(ffffffff), read-only ignoring it PCI: 00:07.4 register 14(ffffffff), read-only ignoring it PCI: 00:07.4 register 18(ffffffff), read-only ignoring it PCI: 00:07.4 register 1c(ffffffff), read-only ignoring it PCI: 00:07.4 register 20(ffffffff), read-only ignoring it PCI: 00:07.4 register 24(ffffffff), read-only ignoring it PCI: 00:07.4 register 30(ffffffff), read-only ignoring it PCI: 00:1c.0 read_resources bus 5 link: 0 PCI: 00:1c.0 read_resources bus 5 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:05.0 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:16.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:19.0 PCI: 00:1a.0 PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1b.0 PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1c.0 child on link 0 PCI: 05:00.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10 PCI: 05:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 PCI: 05:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c PCI: 05:00.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 2200 index 30 PCI: 00:1d.0 PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fee00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fee0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.5 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:03.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 05:00.0 18 * [0x0 - 0x1f] io PCI: 00:1c.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1c.0 1c * [0x0 - 0xfff] io PCI: 00:1f.2 20 * [0x1000 - 0x101f] io PCI: 00:1f.3 20 * [0x1020 - 0x103f] io PCI: 00:16.2 20 * [0x1040 - 0x104f] io PCI: 00:16.2 10 * [0x1050 - 0x1057] io PCI: 00:16.2 18 * [0x1058 - 0x105f] io PCI: 00:16.3 10 * [0x1060 - 0x1067] io PCI: 00:1f.2 10 * [0x1068 - 0x106f] io PCI: 00:1f.2 18 * [0x1070 - 0x1077] io PCI: 00:16.2 14 * [0x1078 - 0x107b] io PCI: 00:16.2 1c * [0x107c - 0x107f] io PCI: 00:1f.2 14 * [0x1080 - 0x1083] io PCI: 00:1f.2 1c * [0x1084 - 0x1087] io DOMAIN: 0000 io: base: 1088 size: 1088 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0x1fff] mem PCI: 02:00.1 10 * [0x2000 - 0x3fff] mem PCI: 02:00.2 10 * [0x4000 - 0x5fff] mem PCI: 02:00.3 10 * [0x6000 - 0x7fff] mem PCI: 00:02.0 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:00.0 10 * [0x0 - 0x1fffff] prefmem PCI: 03:00.1 10 * [0x200000 - 0x3fffff] prefmem PCI: 03:00.0 20 * [0x400000 - 0x403fff] prefmem PCI: 03:00.1 20 * [0x404000 - 0x407fff] prefmem PCI: 00:02.2 prefmem: base: 408000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0x7ffff] mem PCI: 03:00.1 30 * [0x80000 - 0xfffff] mem PCI: 00:02.2 mem: base: 100000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:03.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 05:00.0 10 * [0x0 - 0xfffff] mem PCI: 05:00.0 30 * [0x100000 - 0x1fffff] mem PCI: 05:00.0 1c * [0x200000 - 0x203fff] mem PCI: 00:1c.0 mem: base: 204000 size: 300000 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.2 24 * [0x0 - 0x4fffff] prefmem PCI: 00:1c.0 20 * [0x500000 - 0x7fffff] mem PCI: 00:02.0 20 * [0x800000 - 0x8fffff] mem PCI: 00:02.2 20 * [0x900000 - 0x9fffff] mem PCI: 00:14.0 10 * [0xa00000 - 0xa0ffff] mem PCI: 00:1b.0 10 * [0xa10000 - 0xa13fff] mem PCI: 00:05.4 10 * [0xa14000 - 0xa14fff] mem PCI: 00:16.3 14 * [0xa15000 - 0xa15fff] mem PCI: 00:1f.6 10 * [0xa16000 - 0xa16fff] mem PCI: 00:1f.2 24 * [0xa17000 - 0xa177ff] mem PCI: 00:1a.0 10 * [0xa18000 - 0xa183ff] mem PCI: 00:1d.0 10 * [0xa19000 - 0xa193ff] mem PCI: 00:1f.3 10 * [0xa1a000 - 0xa1a0ff] mem PCI: 00:16.0 10 * [0xa1b000 - 0xa1b00f] mem PCI: 00:16.1 10 * [0xa1c000 - 0xa1c00f] mem DOMAIN: 0000 mem: base: a1c010 size: a1c010 align: 21 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) constrain_resources: PCI: 00:00.0 01 base 00100000 limit 7effffff mem (fixed) constrain_resources: PCI: 00:00.0 02 base 7f800000 limit 7fffffff mem (fixed) constrain_resources: PCI: 00:00.0 05 base 80000000 limit 8fffffff mem (fixed) constrain_resources: PCI: 00:00.0 06 base fee00000 limit fee00fff mem (fixed) constrain_resources: PCI: 00:1f.0 feb0 base feb00000 limit feb0ffff mem (fixed) constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base fe000000 limit feafffff Setting resources... DOMAIN: 0000 io: base:1000 size:1088 align:12 gran:0 limit:ffff PCI: 00:1c.0 1c * [0x1000 - 0x1fff] io PCI: 00:1f.2 20 * [0x2000 - 0x201f] io PCI: 00:1f.3 20 * [0x2020 - 0x203f] io PCI: 00:16.2 20 * [0x2040 - 0x204f] io PCI: 00:16.2 10 * [0x2050 - 0x2057] io PCI: 00:16.2 18 * [0x2058 - 0x205f] io PCI: 00:16.3 10 * [0x2060 - 0x2067] io PCI: 00:1f.2 10 * [0x2068 - 0x206f] io PCI: 00:1f.2 18 * [0x2070 - 0x2077] io PCI: 00:16.2 14 * [0x2078 - 0x207b] io PCI: 00:16.2 1c * [0x207c - 0x207f] io PCI: 00:1f.2 14 * [0x2080 - 0x2083] io PCI: 00:1f.2 1c * [0x2084 - 0x2087] io DOMAIN: 0000 io: next_base: 2088 size: 1088 align: 12 gran: 0 done PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:03.0 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:1c.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 05:00.0 18 * [0x1000 - 0x101f] io PCI: 00:1c.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:fe000000 size:a1c010 align:21 gran:0 limit:feafffff PCI: 00:02.2 24 * [0xfe000000 - 0xfe4fffff] prefmem PCI: 00:1c.0 20 * [0xfe500000 - 0xfe7fffff] mem PCI: 00:02.0 20 * [0xfe800000 - 0xfe8fffff] mem PCI: 00:02.2 20 * [0xfe900000 - 0xfe9fffff] mem PCI: 00:14.0 10 * [0xfea00000 - 0xfea0ffff] mem PCI: 00:1b.0 10 * [0xfea10000 - 0xfea13fff] mem PCI: 00:05.4 10 * [0xfea14000 - 0xfea14fff] mem PCI: 00:16.3 14 * [0xfea15000 - 0xfea15fff] mem PCI: 00:1f.6 10 * [0xfea16000 - 0xfea16fff] mem PCI: 00:1f.2 24 * [0xfea17000 - 0xfea177ff] mem PCI: 00:1a.0 10 * [0xfea18000 - 0xfea183ff] mem PCI: 00:1d.0 10 * [0xfea19000 - 0xfea193ff] mem PCI: 00:1f.3 10 * [0xfea1a000 - 0xfea1a0ff] mem PCI: 00:16.0 10 * [0xfea1b000 - 0xfea1b00f] mem PCI: 00:16.1 10 * [0xfea1c000 - 0xfea1c00f] mem DOMAIN: 0000 mem: next_base: fea1c010 size: a1c010 align: 21 gran: 0 done PCI: 00:01.0 prefmem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:01.0 prefmem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 mem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:01.0 mem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:02.0 prefmem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:02.0 prefmem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:02.0 mem: base:fe800000 size:100000 align:20 gran:20 limit:fe8fffff PCI: 02:00.0 10 * [0xfe800000 - 0xfe801fff] mem PCI: 02:00.1 10 * [0xfe802000 - 0xfe803fff] mem PCI: 02:00.2 10 * [0xfe804000 - 0xfe805fff] mem PCI: 02:00.3 10 * [0xfe806000 - 0xfe807fff] mem PCI: 00:02.0 mem: next_base: fe808000 size: 100000 align: 20 gran: 20 done PCI: 00:02.2 prefmem: base:fe000000 size:500000 align:21 gran:20 limit:fe4fffff PCI: 03:00.0 10 * [0xfe000000 - 0xfe1fffff] prefmem PCI: 03:00.1 10 * [0xfe200000 - 0xfe3fffff] prefmem PCI: 03:00.0 20 * [0xfe400000 - 0xfe403fff] prefmem PCI: 03:00.1 20 * [0xfe404000 - 0xfe407fff] prefmem PCI: 00:02.2 prefmem: next_base: fe408000 size: 500000 align: 21 gran: 20 done PCI: 00:02.2 mem: base:fe900000 size:100000 align:20 gran:20 limit:fe9fffff PCI: 03:00.0 30 * [0xfe900000 - 0xfe97ffff] mem PCI: 03:00.1 30 * [0xfe980000 - 0xfe9fffff] mem PCI: 00:02.2 mem: next_base: fea00000 size: 100000 align: 20 gran: 20 done PCI: 00:03.0 prefmem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:03.0 prefmem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 mem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:03.0 mem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 prefmem: base:feafffff size:0 align:20 gran:20 limit:feafffff PCI: 00:1c.0 prefmem: next_base: feafffff size: 0 align: 20 gran: 20 done PCI: 00:1c.0 mem: base:fe500000 size:300000 align:20 gran:20 limit:fe7fffff PCI: 05:00.0 10 * [0xfe500000 - 0xfe5fffff] mem PCI: 05:00.0 30 * [0xfe600000 - 0xfe6fffff] mem PCI: 05:00.0 1c * [0xfe700000 - 0xfe703fff] mem PCI: 00:1c.0 mem: next_base: fe704000 size: 300000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00fe800000 - 0x00fe8fffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.0 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00fe800000 - 0x00fe801fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.1 10 <- [0x00fe802000 - 0x00fe803fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.2 10 <- [0x00fe804000 - 0x00fe805fff] size 0x00002000 gran 0x0d mem64 PCI: 02:00.3 10 <- [0x00fe806000 - 0x00fe807fff] size 0x00002000 gran 0x0d mem64 PCI: 00:02.0 assign_resources, bus 2 link: 0 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io PCI: 00:02.2 24 <- [0x00fe000000 - 0x00fe4fffff] size 0x00500000 gran 0x14 bus 03 prefmem PCI: 00:02.2 20 <- [0x00fe900000 - 0x00fe9fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:02.2 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fe000000 - 0x00fe1fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.0 20 <- [0x00fe400000 - 0x00fe403fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.0 30 <- [0x00fe900000 - 0x00fe97ffff] size 0x00080000 gran 0x13 romem PCI: 03:00.1 10 <- [0x00fe200000 - 0x00fe3fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 03:00.1 20 <- [0x00fe404000 - 0x00fe407fff] size 0x00004000 gran 0x0e prefmem64 PCI: 03:00.1 30 <- [0x00fe980000 - 0x00fe9fffff] size 0x00080000 gran 0x13 romem PCI: 00:02.2 assign_resources, bus 3 link: 0 PCI: 00:03.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:03.0 24 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:03.0 20 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:05.4 10 <- [0x00fea14000 - 0x00fea14fff] size 0x00001000 gran 0x0c mem PCI: 00:14.0 10 <- [0x00fea00000 - 0x00fea0ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 10 <- [0x00fea1b000 - 0x00fea1b00f] size 0x00000010 gran 0x04 mem64 PCI: 00:16.1 10 <- [0x00fea1c000 - 0x00fea1c00f] size 0x00000010 gran 0x04 mem64 PCI: 00:16.2 10 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io PCI: 00:16.2 14 <- [0x0000002078 - 0x000000207b] size 0x00000004 gran 0x02 io PCI: 00:16.2 18 <- [0x0000002058 - 0x000000205f] size 0x00000008 gran 0x03 io PCI: 00:16.2 1c <- [0x000000207c - 0x000000207f] size 0x00000004 gran 0x02 io PCI: 00:16.2 20 <- [0x0000002040 - 0x000000204f] size 0x00000010 gran 0x04 io PCI: 00:16.3 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io PCI: 00:16.3 14 <- [0x00fea15000 - 0x00fea15fff] size 0x00001000 gran 0x0c mem PCI: 00:1a.0 10 <- [0x00fea18000 - 0x00fea183ff] size 0x00000400 gran 0x0a mem PCI: 00:1b.0 10 <- [0x00fea10000 - 0x00fea13fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 05 io PCI: 00:1c.0 24 <- [0x00feafffff - 0x00feaffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:1c.0 20 <- [0x00fe500000 - 0x00fe7fffff] size 0x00300000 gran 0x14 bus 05 mem PCI: 00:1c.0 assign_resources, bus 5 link: 0 PCI: 05:00.0 10 <- [0x00fe500000 - 0x00fe5fffff] size 0x00100000 gran 0x14 mem PCI: 05:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io PCI: 05:00.0 1c <- [0x00fe700000 - 0x00fe703fff] size 0x00004000 gran 0x0e mem PCI: 05:00.0 30 <- [0x00fe600000 - 0x00fe6fffff] size 0x00100000 gran 0x14 romem PCI: 00:1c.0 assign_resources, bus 5 link: 0 PCI: 00:1d.0 10 <- [0x00fea19000 - 0x00fea193ff] size 0x00000400 gran 0x0a mem PCI: 00:1f.2 10 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io PCI: 00:1f.2 14 <- [0x0000002080 - 0x0000002083] size 0x00000004 gran 0x02 io PCI: 00:1f.2 18 <- [0x0000002070 - 0x0000002077] size 0x00000008 gran 0x03 io PCI: 00:1f.2 1c <- [0x0000002084 - 0x0000002087] size 0x00000004 gran 0x02 io PCI: 00:1f.2 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:1f.2 24 <- [0x00fea17000 - 0x00fea177ff] size 0x00000800 gran 0x0b mem PCI: 00:1f.3 10 <- [0x00fea1a000 - 0x00fea1a0ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io PCI: 00:1f.6 10 <- [0x00fea16000 - 0x00fea16fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 1088 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base fe000000 size a1c010 align 21 gran 0 limit feafffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:01.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60081202 index 24 PCI: 00:01.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60080202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60081202 index 24 PCI: 00:02.0 resource base fe800000 size 100000 align 20 gran 20 limit fe8fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base fe800000 size 2000 align 13 gran 13 limit fe801fff flags 60000201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base fe802000 size 2000 align 13 gran 13 limit fe803fff flags 60000201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base fe804000 size 2000 align 13 gran 13 limit fe805fff flags 60000201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base fe806000 size 2000 align 13 gran 13 limit fe807fff flags 60000201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base fe000000 size 500000 align 21 gran 20 limit fe4fffff flags 60081202 index 24 PCI: 00:02.2 resource base fe900000 size 100000 align 20 gran 20 limit fe9fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fe000000 size 200000 align 21 gran 21 limit fe1fffff flags 60001201 index 10 PCI: 03:00.0 resource base fe400000 size 4000 align 14 gran 14 limit fe403fff flags 60001201 index 20 PCI: 03:00.0 resource base fe900000 size 80000 align 19 gran 19 limit fe97ffff flags 60002200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base fe200000 size 200000 align 21 gran 21 limit fe3fffff flags 60001201 index 10 PCI: 03:00.1 resource base fe404000 size 4000 align 14 gran 14 limit fe407fff flags 60001201 index 20 PCI: 03:00.1 resource base fe980000 size 80000 align 19 gran 19 limit fe9fffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60081202 index 24 PCI: 00:03.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60080202 index 20 PCI: 00:05.0 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base fea14000 size 1000 align 12 gran 12 limit fea14fff flags 60000200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base fea00000 size 10000 align 16 gran 16 limit fea0ffff flags 60000201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base fea1b000 size 10 align 12 gran 4 limit fea1b00f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base fea1c000 size 10 align 12 gran 4 limit fea1c00f flags 60000201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 2050 size 8 align 3 gran 3 limit 2057 flags 60000100 index 10 PCI: 00:16.2 resource base 2078 size 4 align 2 gran 2 limit 207b flags 60000100 index 14 PCI: 00:16.2 resource base 2058 size 8 align 3 gran 3 limit 205f flags 60000100 index 18 PCI: 00:16.2 resource base 207c size 4 align 2 gran 2 limit 207f flags 60000100 index 1c PCI: 00:16.2 resource base 2040 size 10 align 4 gran 4 limit 204f flags 60000100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 PCI: 00:16.3 resource base fea15000 size 1000 align 12 gran 12 limit fea15fff flags 60000200 index 14 PCI: 00:19.0 PCI: 00:1a.0 PCI: 00:1a.0 resource base fea18000 size 400 align 12 gran 10 limit fea183ff flags 60000200 index 10 PCI: 00:1b.0 PCI: 00:1b.0 resource base fea10000 size 4000 align 14 gran 14 limit fea13fff flags 60000201 index 10 PCI: 00:1c.0 child on link 0 PCI: 05:00.0 PCI: 00:1c.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:1c.0 resource base feafffff size 0 align 20 gran 20 limit feafffff flags 60081202 index 24 PCI: 00:1c.0 resource base fe500000 size 300000 align 20 gran 20 limit fe7fffff flags 60080202 index 20 PCI: 05:00.0 PCI: 05:00.0 resource base fe500000 size 100000 align 20 gran 20 limit fe5fffff flags 60000200 index 10 PCI: 05:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18 PCI: 05:00.0 resource base fe700000 size 4000 align 14 gran 14 limit fe703fff flags 60000200 index 1c PCI: 05:00.0 resource base fe600000 size 100000 align 20 gran 20 limit fe6fffff flags 60002200 index 30 PCI: 00:1d.0 PCI: 00:1d.0 resource base fea19000 size 400 align 12 gran 10 limit fea193ff flags 60000200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fee00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fee0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.2 PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 10 PCI: 00:1f.2 resource base 2080 size 4 align 2 gran 2 limit 2083 flags 60000100 index 14 PCI: 00:1f.2 resource base 2070 size 8 align 3 gran 3 limit 2077 flags 60000100 index 18 PCI: 00:1f.2 resource base 2084 size 4 align 2 gran 2 limit 2087 flags 60000100 index 1c PCI: 00:1f.2 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 20 PCI: 00:1f.2 resource base fea17000 size 800 align 12 gran 11 limit fea177ff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base fea1a000 size 100 align 12 gran 8 limit fea1a0ff flags 60000201 index 10 PCI: 00:1f.3 resource base 2020 size 20 align 5 gran 5 limit 203f flags 60000100 index 20 PCI: 00:1f.5 PCI: 00:1f.6 PCI: 00:1f.6 resource base fea16000 size 1000 align 12 gran 12 limit fea16fff flags 60000201 index 10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 3643751 exit 0 Enabling resources... PCI: 00:00.0 subsystem <- 8086/6f00 PCI: 00:00.0 cmd <- 400 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 00 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 06 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 00 PCI: 00:05.0 cmd <- 04 PCI: 00:05.1 cmd <- 04 PCI: 00:05.2 cmd <- 04 PCI: 00:05.4 cmd <- 06 PCI: 00:05.6 cmd <- ffff PCI: 00:06.0 cmd <- ffff PCI: 00:06.1 cmd <- ffff PCI: 00:06.2 cmd <- ffff PCI: 00:06.3 cmd <- ffff PCI: 00:06.4 cmd <- ffff PCI: 00:06.5 cmd <- ffff PCI: 00:06.6 cmd <- ffff PCI: 00:06.7 cmd <- ffff PCI: 00:07.0 cmd <- ffff PCI: 00:07.1 cmd <- ffff PCI: 00:07.2 cmd <- ffff PCI: 00:07.3 cmd <- ffff PCI: 00:07.4 cmd <- ffff PCI: 00:14.0 subsystem <- 8086/8c31 PCI: 00:14.0 cmd <- 02 PCI: 00:16.0 cmd <- 06 PCI: 00:16.1 cmd <- 02 PCI: 00:16.2 cmd <- 01 PCI: 00:16.3 cmd <- 03 PCI: 00:1a.0 cmd <- 02 PCI: 00:1b.0 cmd <- 02 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 cmd <- 07 PCI: 00:1d.0 subsystem <- 8086/8c26 PCI: 00:1d.0 cmd <- 02 PCI: 00:1f.2 subsystem <- 8086/8c02 PCI: 00:1f.2 cmd <- 03 PCI: 00:1f.3 cmd <- 03 PCI: 00:1f.6 cmd <- 02 PCI: 02:00.0 cmd <- 06 PCI: 02:00.1 cmd <- 06 PCI: 02:00.2 cmd <- 06 PCI: 02:00.3 cmd <- 06 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 cmd <- 02 PCI: 05:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE times (us): entry 0 run 134542 exit 0 Initializing devices... Root Device init ... 0 init ... Root Device init finished in 3308 usecs CPU_CLUSTER: 0 init ... 0 init ... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x00 done. Setting up SMI for CPU Will perform SMM setup. CPU: Intel(R) Pentium(R) CPU D1507 @ 1.20GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. Waiting for 2nd SIPI to complete...done. AP: slot 1 apic_id 2. Loading module at 00038000 with entry 00038000. filesize: 0x1b0 memsize: 0x1b0 Processing 12 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 0010d75c(00000000) Installing SMM handler to 0x7f800000 Loading module at 7f810000 with entry 7f81002b. filesize: 0x188 memsize: 0x4190 Processing 11 relocs. Offset value of 0x7f810000 Loading module at 7f808000 with entry 7f808000. filesize: 0x1b0 memsize: 0x1b0 Processing 12 relocs. Offset value of 0x7f808000 SMM Module: placing jmp sequence at 7f807c00 rel16 0x03fd SMM Module: stub loaded at 7f808000. Will call 7f81002b(00000000) Initializing Southbridge SMI... ... pmbase = 0x0400 SMI_STS: PM1 PM1_STS: TMROF New SMBASE 0x7f800000 In relocation handler: CPU 0 Relocation complete. Doing parallel SMM relocation. New SMBASE 0x7f800000 In relocation handler: CPU 0 New SMBASE 0x7f7ffc00 In relocation handler: CPU 1 New SMBASE=0x7f7ffc00 IEDBASE=0x7fc00000 New SMBASE=0x7f800000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff900800 Writing SMRR. base = 0x7f800006, mask=0xff900800 Relocation complete. Relocation complete. Initializing CPU #0 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #1 initialized Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 207825 usecs PCI: 00:05.0 init ... 6f28 init ... PCI: 00:05.0 init finished in 3692 usecs PCI: 00:05.1 init ... 6f29 init ... PCI: 00:05.1 init finished in 3692 usecs PCI: 00:05.2 init ... 6f2a init ... PCI: 00:05.2 init finished in 3691 usecs PCI: 00:05.4 init ... 6f2c init ... PCI: 00:05.4 init finished in 3691 usecs PCI: 00:05.6 init ... 6f39 init ... PCI: 00:05.6 init finished in 3690 usecs PCI: 00:06.0 init ... 6f10 init ... PCI: 00:06.0 init finished in 3691 usecs PCI: 00:06.1 init ... 6f11 init ... PCI: 00:06.1 init finished in 3692 usecs PCI: 00:06.2 init ... 6f12 init ... PCI: 00:06.2 init finished in 3690 usecs PCI: 00:06.3 init ... 6f13 init ... PCI: 00:06.3 init finished in 3691 usecs PCI: 00:06.4 init ... 6f14 init ... PCI: 00:06.4 init finished in 3692 usecs PCI: 00:06.5 init ... 6f15 init ... PCI: 00:06.5 init finished in 3691 usecs PCI: 00:06.6 init ... 6f16 init ... PCI: 00:06.6 init finished in 3691 usecs PCI: 00:06.7 init ... 6f17 init ... PCI: 00:06.7 init finished in 3691 usecs PCI: 00:07.0 init ... 6f18 init ... PCI: 00:07.0 init finished in 3691 usecs PCI: 00:07.1 init ... 6f19 init ... PCI: 00:07.1 init finished in 3691 usecs PCI: 00:07.2 init ... 6f1a init ... PCI: 00:07.2 init finished in 3691 usecs PCI: 00:07.3 init ... 6f1b init ... PCI: 00:07.3 init finished in 3691 usecs PCI: 00:07.4 init ... 6f1c init ... PCI: 00:07.4 init finished in 3691 usecs PCI: 00:14.0 init ... 8c31 init ... PCI: 00:14.0 init finished in 3691 usecs PCI: 00:16.0 init ... 8c3a init ... PCI: 00:16.0 init finished in 3691 usecs PCI: 00:16.1 init ... 8c3b init ... PCI: 00:16.1 init finished in 3691 usecs PCI: 00:16.2 init ... 8c3c init ... PCI: 00:16.2 init finished in 3691 usecs PCI: 00:16.3 init ... 8c3d init ... PCI: 00:16.3 init finished in 3691 usecs PCI: 00:1a.0 init ... 8c2d init ... PCI: 00:1a.0 init finished in 3690 usecs PCI: 00:1b.0 init ... 8c20 init ... PCI: 00:1b.0 init finished in 3691 usecs PCI: 00:1d.0 init ... 8c26 init ... PCI: 00:1d.0 init finished in 3691 usecs PCI: 00:1f.0 init ... 8c54 init ... soc: southcluster_init soc: write_pci_config_irqs done soc: isa_dma_init done soc: setup_i8259 done soc: setup_i8254 done PCI: 00:1f.0 init finished in 16048 usecs PCI: 00:1f.2 init ... 8c02 init ... PCI: 00:1f.2 init finished in 3691 usecs PCI: 00:1f.3 init ... 8c22 init ... Enable clock gating