MAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 01:00.0 14 * [0x0 - 0x7ffffff] prefmem PCI: 01:00.0 1c * [0x8000000 - 0x9ffffff] prefmem PCI: 00:02.0 prefmem: base: a000000 size: a000000 align: 27 gran: 20 limit: ffffffffffffffff done PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:02.0 24 * [0x0 - 0x9ffffff] prefmem PCI: 00:00.0 fc * [0xa000000 - 0xa0000ff] prefmem PCI: 00:18.0 prefmem: base: a000100 size: a100000 align: 27 gran: 20 limit: ffffffff done PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem PCI: 00:02.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x1ffff] mem PCI: 03:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:00.0 10 * [0x0 - 0x1ffff] mem PCI: 04:00.0 1c * [0x20000 - 0x23fff] mem PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 07:00.0 10 * [0x0 - 0x3fff] mem PCI: 00:0d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 08:01.0 10 * [0x0 - 0x7fffff] mem PCI: 08:01.0 14 * [0x800000 - 0x81ffff] mem PCI: 08:02.0 10 * [0x820000 - 0x820fff] mem PCI: 08:03.2 10 * [0x821000 - 0x8210ff] mem PCI: 00:14.4 mem: base: 821100 size: 900000 align: 23 gran: 20 limit: ffffffff done PCI: 00:02.0 20 * [0x0 - 0x10fffff] mem PCI: 00:14.4 20 * [0x1800000 - 0x20fffff] mem PCI: 00:09.0 20 * [0x2100000 - 0x21fffff] mem PCI: 00:0a.0 20 * [0x2200000 - 0x22fffff] mem PCI: 00:0d.0 20 * [0x2300000 - 0x23fffff] mem PCI: 00:00.2 44 * [0x2400000 - 0x2403fff] mem PCI: 00:14.2 10 * [0x2404000 - 0x2407fff] mem PCI: 00:12.0 10 * [0x2408000 - 0x2408fff] mem PCI: 00:12.1 10 * [0x2409000 - 0x2409fff] mem PCI: 00:13.0 10 * [0x240a000 - 0x240afff] mem PCI: 00:13.1 10 * [0x240b000 - 0x240bfff] mem PCI: 00:14.5 10 * [0x240c000 - 0x240cfff] mem PCI: 00:11.0 24 * [0x240d000 - 0x240d3ff] mem PCI: 00:12.2 10 * [0x240e000 - 0x240e0ff] mem PCI: 00:13.2 10 * [0x240f000 - 0x240f0ff] mem PCI: 00:14.3 a0 * [0x2410000 - 0x2410000] mem PCI: 00:18.0 mem: base: 2410001 size: 2500000 align: 24 gran: 20 limit: ffffffff done PCI: 00:18.0 110b0 * [0x0 - 0xa0fffff] prefmem PCI: 00:18.3 94 * [0xc000000 - 0xfffffff] mem PCI: 00:18.0 110b8 * [0x10000000 - 0x124fffff] mem DOMAIN: 0000 mem: base: 12500000 size: 12500000 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed) constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed) constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed) constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base e8000000 limit feafffff Setting resources... DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff PCI: 00:18.0 110d8 * [0x1000 - 0x5fff] io DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff PCI: 00:02.0 1c * [0x1000 - 0x1fff] io PCI: 00:09.0 1c * [0x2000 - 0x2fff] io PCI: 00:0a.0 1c * [0x3000 - 0x3fff] io PCI: 00:14.4 1c * [0x4000 - 0x4fff] io PCI: 00:11.0 20 * [0x5000 - 0x500f] io PCI: 00:14.1 20 * [0x5010 - 0x501f] io PCI: 00:11.0 10 * [0x5020 - 0x5027] io PCI: 00:11.0 18 * [0x5028 - 0x502f] io PCI: 00:14.1 10 * [0x5030 - 0x5037] io PCI: 00:14.1 18 * [0x5038 - 0x503f] io PCI: 00:11.0 14 * [0x5040 - 0x5043] io PCI: 00:11.0 1c * [0x5044 - 0x5047] io PCI: 00:14.1 14 * [0x5048 - 0x504b] io PCI: 00:14.1 1c * [0x504c - 0x504f] io PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done PCI: 00:02.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 01:00.0 24 * [0x1000 - 0x107f] io PCI: 00:02.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:09.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff PCI: 03:00.0 18 * [0x2000 - 0x201f] io PCI: 00:09.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff PCI: 04:00.0 18 * [0x3000 - 0x301f] io PCI: 00:0a.0 io: next_base: 3020 size: 1000 align: 12 gran: 12 done PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 io: base:5fff size:0 align:12 gran:12 limit:5fff PCI: 00:0d.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff PCI: 08:01.0 18 * [0x4000 - 0x407f] io PCI: 08:03.0 20 * [0x4080 - 0x409f] io PCI: 08:03.1 20 * [0x40a0 - 0x40bf] io PCI: 00:14.4 io: next_base: 40c0 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:e8000000 size:12500000 align:27 gran:0 limit:feafffff PCI: 00:18.0 110b0 * [0xe8000000 - 0xf20fffff] prefmem PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI: 00:18.0 110b8 * [0xf8000000 - 0xfa4fffff] mem DOMAIN: 0000 mem: next_base: fa500000 size: 12500000 align: 27 gran: 0 done PCI: 00:18.0 prefmem: base:e8000000 size:a100000 align:27 gran:20 limit:f20fffff PCI: 00:02.0 24 * [0xe8000000 - 0xf1ffffff] prefmem PCI: 00:00.0 fc * [0xf2000000 - 0xf20000ff] prefmem PCI: 00:18.0 prefmem: next_base: f2000100 size: a100000 align: 27 gran: 20 done PCI: 00:02.0 prefmem: base:e8000000 size:a000000 align:27 gran:20 limit:f1ffffff PCI: 01:00.0 14 * [0xe8000000 - 0xefffffff] prefmem PCI: 01:00.0 1c * [0xf0000000 - 0xf1ffffff] prefmem PCI: 00:02.0 prefmem: next_base: f2000000 size: a000000 align: 27 gran: 20 done PCI: 00:04.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:04.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:09.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0a.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0b.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0b.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0c.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:0d.0 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 prefmem: base:f20fffff size:0 align:20 gran:20 limit:f20fffff PCI: 00:14.4 prefmem: next_base: f20fffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 mem: base:f8000000 size:2500000 align:24 gran:20 limit:fa4fffff PCI: 00:02.0 20 * [0xf8000000 - 0xf90fffff] mem PCI: 00:14.4 20 * [0xf9800000 - 0xfa0fffff] mem PCI: 00:09.0 20 * [0xfa100000 - 0xfa1fffff] mem PCI: 00:0a.0 20 * [0xfa200000 - 0xfa2fffff] mem PCI: 00:0d.0 20 * [0xfa300000 - 0xfa3fffff] mem PCI: 00:00.2 44 * [0xfa400000 - 0xfa403fff] mem PCI: 00:14.2 10 * [0xfa404000 - 0xfa407fff] mem PCI: 00:12.0 10 * [0xfa408000 - 0xfa408fff] mem PCI: 00:12.1 10 * [0xfa409000 - 0xfa409fff] mem PCI: 00:13.0 10 * [0xfa40a000 - 0xfa40afff] mem PCI: 00:13.1 10 * [0xfa40b000 - 0xfa40bfff] mem PCI: 00:14.5 10 * [0xfa40c000 - 0xfa40cfff] mem PCI: 00:11.0 24 * [0xfa40d000 - 0xfa40d3ff] mem PCI: 00:12.2 10 * [0xfa40e000 - 0xfa40e0ff] mem PCI: 00:13.2 10 * [0xfa40f000 - 0xfa40f0ff] mem PCI: 00:14.3 a0 * [0xfa410000 - 0xfa410000] mem PCI: 00:18.0 mem: next_base: fa410001 size: 2500000 align: 24 gran: 20 done PCI: 00:02.0 mem: base:f8000000 size:1100000 align:24 gran:20 limit:f90fffff PCI: 01:00.0 10 * [0xf8000000 - 0xf8ffffff] mem PCI: 01:00.0 30 * [0xf9000000 - 0xf907ffff] mem PCI: 01:00.1 10 * [0xf9080000 - 0xf9083fff] mem PCI: 00:02.0 mem: next_base: f9084000 size: 1100000 align: 24 gran: 20 done PCI: 00:04.0 mem: base:fa4fffff size:0 align:20 gran:20 limit:fa4fffff PCI: 00:04.0 mem: next_base: fa4fffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 mem: base:fa100000 size:100000 align:20 gran:20 limit:fa1fffff PCI: 03:00.0 10 * [0xfa100000 - 0xfa11ffff] mem PCI: 03:00.0 1c * [0xfa120000 - 0xfa123fff] mem PCI: 00:09.0 mem: next_base: fa124000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 mem: base:fa200000 size:100000 align:20 gran:20 limit:fa2fffff PCI: 04:00.0 10 * [0xfa200000 - 0xfa21ffff] mem PCI: 04:00.0 1c * [0xfa220000 - 0xfa223fff] mem PCI: 00:0a.0 mem: next_base: fa224000 size: 100000 align: 20 gran: 20 done PCI: 00:0b.0 mem: base:fa4fffff size:0 align:20 gran:20 limit:fa4fffff PCI: 00:0b.0 mem: next_base: fa4fffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 mem: base:fa4fffff size:0 align:20 gran:20 limit:fa4fffff PCI: 00:0c.0 mem: next_base: fa4fffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 mem: base:fa300000 size:100000 align:20 gran:20 limit:fa3fffff PCI: 07:00.0 10 * [0xfa300000 - 0xfa303fff] mem PCI: 00:0d.0 mem: next_base: fa304000 size: 100000 align: 20 gran: 20 done PCI: 00:14.4 mem: base:f9800000 size:900000 align:23 gran:20 limit:fa0fffff PCI: 08:01.0 10 * [0xf9800000 - 0xf9ffffff] mem PCI: 08:01.0 14 * [0xfa000000 - 0xfa01ffff] mem PCI: 08:02.0 10 * [0xfa020000 - 0xfa020fff] mem PCI: 08:03.2 10 * [0xfa021000 - 0xfa0210ff] mem PCI: 00:14.4 mem: next_base: fa021100 size: 900000 align: 23 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00400000, limitk=01100000 1: mmio_basek=00300000, basek=01100000, limitk=02100000 2: mmio_basek=00300000, basek=02100000, limitk=03100000 3: mmio_basek=00300000, basek=03100000, limitk=04100000 DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 110b0 <- [0x00e8000000 - 0x00f20fffff] size 0x0a100000 gran 0x14 prefmem PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fa4fffff] size 0x02500000 gran 0x14 mem PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:00.0 sr5690_set_resources sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90 PCI: 00:00.0 fc <- [0x00f2000000 - 0x00f20000ff] size 0x00000100 gran 0x08 prefmem PCI: 00:00.2 44 <- [0x00fa400000 - 0x00fa403fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:02.0 24 <- [0x00e8000000 - 0x00f1ffffff] size 0x0a000000 gran 0x14 bus 01 prefmem PCI: 00:02.0 20 <- [0x00f8000000 - 0x00f90fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:02.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 14 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x1b prefmem64 PCI: 01:00.0 1c <- [0x00f0000000 - 0x00f1ffffff] size 0x02000000 gran 0x19 prefmem64 PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io PCI: 01:00.0 30 <- [0x00f9000000 - 0x00f907ffff] size 0x00080000 gran 0x13 romem PCI: 01:00.1 10 <- [0x00f9080000 - 0x00f9083fff] size 0x00004000 gran 0x0e mem PCI: 00:02.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00fa4fffff - 0x00fa4ffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00fa100000 - 0x00fa1fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x00fa100000 - 0x00fa11ffff] size 0x00020000 gran 0x11 mem PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x00fa120000 - 0x00fa123fff] size 0x00004000 gran 0x0e mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 00:0a.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00fa200000 - 0x00fa2fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 04:00.0 10 <- [0x00fa200000 - 0x00fa21ffff] size 0x00020000 gran 0x11 mem PCI: 04:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io PCI: 04:00.0 1c <- [0x00fa220000 - 0x00fa223fff] size 0x00004000 gran 0x0e mem PCI: 00:0a.0 assign_resources, bus 4 link: 0 PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:0b.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:0b.0 20 <- [0x00fa4fffff - 0x00fa4ffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io PCI: 00:0c.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 06 prefmem PCI: 00:0c.0 20 <- [0x00fa4fffff - 0x00fa4ffffe] size 0x00000000 gran 0x14 bus 06 mem PCI: 00:0d.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 07 io PCI: 00:0d.0 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 07 prefmem PCI: 00:0d.0 20 <- [0x00fa300000 - 0x00fa3fffff] size 0x00100000 gran 0x14 bus 07 mem PCI: 00:0d.0 assign_resources, bus 7 link: 0 PCI: 07:00.0 10 <- [0x00fa300000 - 0x00fa303fff] size 0x00004000 gran 0x0e mem64 PCI: 00:0d.0 assign_resources, bus 7 link: 0 PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00fa40d000 - 0x00fa40d3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00fa408000 - 0x00fa408fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00fa409000 - 0x00fa409fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00fa40e000 - 0x00fa40e0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00fa40a000 - 0x00fa40afff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00fa40b000 - 0x00fa40bfff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00fa40f000 - 0x00fa40f0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00fa404000 - 0x00fa407fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00fa410000 - 0x00fa410000] size 0x00000001 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io PCI: 00:14.4 24 <- [0x00f20fffff - 0x00f20ffffe] size 0x00000000 gran 0x14 bus 08 prefmem PCI: 00:14.4 20 <- [0x00f9800000 - 0x00fa0fffff] size 0x00900000 gran 0x14 bus 08 mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 08:01.0 10 <- [0x00f9800000 - 0x00f9ffffff] size 0x00800000 gran 0x17 mem PCI: 08:01.0 14 <- [0x00fa000000 - 0x00fa01ffff] size 0x00020000 gran 0x11 mem PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io PCI: 08:02.0 10 <- [0x00fa020000 - 0x00fa020fff] size 0x00001000 gran 0x0c mem PCI: 08:03.0 20 <- [0x0000004080 - 0x000000409f] size 0x00000020 gran 0x05 io PCI: 08:03.1 20 <- [0x00000040a0 - 0x00000040bf] size 0x00000020 gran 0x05 io PCI: 08:03.2 10 <- [0x00fa021000 - 0x00fa0210ff] size 0x00000100 gran 0x08 mem PCI: 00:14.4 assign_resources, bus 8 link: 0 PCI: 00:14.5 10 <- [0x00fa40c000 - 0x00fa40cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 assign_resources, bus 0 link: 1 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI: 00:19.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI: 00:1a.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI: 00:1b.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 02 APIC: 03 APIC: 04 APIC: 05 APIC: 06 APIC: 07 APIC: 08 APIC: 09 APIC: 0a APIC: 0b APIC: 0c APIC: 0d APIC: 0e APIC: 0f APIC: 20 APIC: 21 APIC: 22 APIC: 23 APIC: 24 APIC: 25 APIC: 26 APIC: 27 APIC: 28 APIC: 29 APIC: 2a APIC: 2b APIC: 2c APIC: 2d APIC: 2e APIC: 2f DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base e8000000 size 12500000 align 27 gran 0 limit feafffff flags 40040200 index 10000100 DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 DOMAIN: 0000 resource base 100000000 size 340000000 align 0 gran 0 limit 0 flags e0004200 index 30 DOMAIN: 0000 resource base 440000000 size 400000000 align 0 gran 0 limit 0 flags e0004200 index 41 DOMAIN: 0000 resource base 840000000 size 400000000 align 0 gran 0 limit 0 flags e0004200 index 52 DOMAIN: 0000 resource base c40000000 size 400000000 align 0 gran 0 limit 0 flags e0004200 index 63 PCI: 00:18.0 PCI: 00:18.0 resource base e8000000 size a100000 align 27 gran 20 limit f20fffff flags 60081200 index 110b0 PCI: 00:18.0 resource base f8000000 size 2500000 align 24 gran 20 limit fa4fffff flags 60080200 index 110b8 PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8 PCI: 00:00.0 PCI: 00:00.0 resource base f2000000 size 100 align 12 gran 8 limit f20000ff flags 60001200 index fc PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.2 resource base fa400000 size 4000 align 14 gran 14 limit fa403fff flags 70000200 index 44 PCI: 00:02.0 child on link 0 PCI: 01:00.0 PCI: 00:02.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:02.0 resource base e8000000 size a000000 align 27 gran 20 limit f1ffffff flags 60081202 index 24 PCI: 00:02.0 resource base f8000000 size 1100000 align 24 gran 20 limit f90fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f8000000 size 1000000 align 24 gran 24 limit f8ffffff flags 60000200 index 10 PCI: 01:00.0 resource base e8000000 size 8000000 align 27 gran 27 limit efffffff flags 60001201 index 14 PCI: 01:00.0 resource base f0000000 size 2000000 align 25 gran 25 limit f1ffffff flags 60001201 index 1c PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24 PCI: 01:00.0 resource base f9000000 size 80000 align 19 gran 19 limit f907ffff flags 60002200 index 30 PCI: 01:00.1 PCI: 01:00.1 resource base f9080000 size 4000 align 14 gran 14 limit f9083fff flags 60000200 index 10 PCI: 00:03.0 PCI: 00:04.0 PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:04.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:04.0 resource base fa4fffff size 0 align 20 gran 20 limit fa4fffff flags 60080202 index 20 PCI: 00:05.0 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:09.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:09.0 resource base fa100000 size 100000 align 20 gran 20 limit fa1fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fa100000 size 20000 align 17 gran 17 limit fa11ffff flags 60000200 index 10 PCI: 03:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18 PCI: 03:00.0 resource base fa120000 size 4000 align 14 gran 14 limit fa123fff flags 60000200 index 1c PCI: 00:0a.0 child on link 0 PCI: 04:00.0 PCI: 00:0a.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c PCI: 00:0a.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0a.0 resource base fa200000 size 100000 align 20 gran 20 limit fa2fffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fa200000 size 20000 align 17 gran 17 limit fa21ffff flags 60000200 index 10 PCI: 04:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18 PCI: 04:00.0 resource base fa220000 size 4000 align 14 gran 14 limit fa223fff flags 60000200 index 1c PCI: 00:0b.0 PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0b.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0b.0 resource base fa4fffff size 0 align 20 gran 20 limit fa4fffff flags 60080202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0c.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0c.0 resource base fa4fffff size 0 align 20 gran 20 limit fa4fffff flags 60080202 index 20 PCI: 00:0d.0 child on link 0 PCI: 07:00.0 PCI: 00:0d.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c PCI: 00:0d.0 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:0d.0 resource base fa300000 size 100000 align 20 gran 20 limit fa3fffff flags 60080202 index 20 PCI: 07:00.0 PCI: 07:00.0 resource base fa300000 size 4000 align 14 gran 14 limit fa303fff flags 60000201 index 10 PCI: 00:11.0 PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10 PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14 PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18 PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20 PCI: 00:11.0 resource base fa40d000 size 400 align 12 gran 10 limit fa40d3ff flags 60000200 index 24 PCI: 00:12.0 PCI: 00:12.0 resource base fa408000 size 1000 align 12 gran 12 limit fa408fff flags 60000200 index 10 PCI: 00:12.1 PCI: 00:12.1 resource base fa409000 size 1000 align 12 gran 12 limit fa409fff flags 60000200 index 10 PCI: 00:12.2 PCI: 00:12.2 resource base fa40e000 size 100 align 12 gran 8 limit fa40e0ff flags 60000200 index 10 PCI: 00:13.0 PCI: 00:13.0 resource base fa40a000 size 1000 align 12 gran 12 limit fa40afff flags 60000200 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base fa40b000 size 1000 align 12 gran 12 limit fa40bfff flags 60000200 index 10 PCI: 00:13.2 PCI: 00:13.2 resource base fa40f000 size 100 align 12 gran 8 limit fa40f0ff flags 60000200 index 10 PCI: 00:14.0 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74 PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90 PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 I2C: 01:54 I2C: 01:55 I2C: 01:56 I2C: 01:57 I2C: 01:2f PCI: 00:14.1 PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10 PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14 PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18 PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20 PCI: 00:14.2 PCI: 00:14.2 resource base fa404000 size 4000 align 14 gran 14 limit fa407fff flags 60000201 index 10 PCI: 00:14.3 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base fa410000 size 1 align 12 gran 0 limit fa410000 flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.106 PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.107 PNP: 002e.207 PNP: 002e.307 PNP: 002e.407 PNP: 002e.8 PNP: 002e.108 PNP: 002e.9 PNP: 002e.109 PNP: 002e.209 PNP: 002e.309 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60 PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.c PNP: 002e.d PNP: 002e.f PNP: 004e.0 PCI: 00:14.4 child on link 0 PCI: 08:01.0 PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c PCI: 00:14.4 resource base f20fffff size 0 align 20 gran 20 limit f20fffff flags 60081202 index 24 PCI: 00:14.4 resource base f9800000 size 900000 align 23 gran 20 limit fa0fffff flags 60080202 index 20 PCI: 08:01.0 PCI: 08:01.0 resource base f9800000 size 800000 align 23 gran 23 limit f9ffffff flags 60000200 index 10 PCI: 08:01.0 resource base fa000000 size 20000 align 17 gran 17 limit fa01ffff flags 60000200 index 14 PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18 PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 08:02.0 PCI: 08:02.0 resource base fa020000 size 1000 align 12 gran 12 limit fa020fff flags 60000200 index 10 PCI: 08:03.0 PCI: 08:03.0 resource base 4080 size 20 align 5 gran 5 limit 409f flags 60000100 index 20 PCI: 08:03.1 PCI: 08:03.1 resource base 40a0 size 20 align 5 gran 5 limit 40bf flags 60000100 index 20 PCI: 08:03.2 PCI: 08:03.2 resource base fa021000 size 100 align 12 gran 8 limit fa0210ff flags 60000200 index 10 PCI: 00:14.5 PCI: 00:14.5 resource base fa40c000 size 1000 align 12 gran 12 limit fa40cfff flags 60000200 index 10 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94 PCI: 00:18.4 PCI: 00:18.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:19.3 PCI: 00:19.4 PCI: 00:19.5 PCI: 00:1a.0 PCI: 00:1a.1 PCI: 00:1a.2 PCI: 00:1a.3 PCI: 00:1a.4 PCI: 00:1a.5 PCI: 00:1b.0 PCI: 00:1b.1 PCI: 00:1b.2 PCI: 00:1b.3 PCI: 00:1b.4 PCI: 00:1b.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 2747 exit 0 POST: 0x74 Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8163 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8163 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 subsystem <- 1043/8163 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 subsystem <- 1043/8163 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 PCI: 00:19.4 cmd <- 00 PCI: 00:19.5 cmd <- 00 PCI: 00:1a.0 cmd <- 00 PCI: 00:1a.1 subsystem <- 1043/8163 PCI: 00:1a.1 cmd <- 00 PCI: 00:1a.2 subsystem <- 1043/8163 PCI: 00:1a.2 cmd <- 00 PCI: 00:1a.3 cmd <- 00 PCI: 00:1a.4 cmd <- 00 PCI: 00:1a.5 cmd <- 00 PCI: 00:1b.0 cmd <- 00 PCI: 00:1b.1 subsystem <- 1043/8163 PCI: 00:1b.1 cmd <- 00 PCI: 00:1b.2 subsystem <- 1043/8163 PCI: 00:1b.2 cmd <- 00 PCI: 00:1b.3 cmd <- 00 PCI: 00:1b.4 cmd <- 00 PCI: 00:1b.5 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/8163 PCI: 00:00.0 cmd <- 02 Initializing IOMMU PCI: 00:02.0 bridge ctrl <- 000b PCI: 00:02.0 cmd <- 07 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 07 PCI: 00:0b.0 bridge ctrl <- 0003 PCI: 00:0b.0 cmd <- 00 PCI: 00:0c.0 bridge ctrl <- 0003 PCI: 00:0c.0 cmd <- 00 PCI: 00:0d.0 bridge ctrl <- 0003 PCI: 00:0d.0 cmd <- 06 PCI: 00:11.0 subsystem <- 1043/8163 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1043/8163 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1043/8163 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1043/8163 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1043/8163 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1043/8163 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1043/8163 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1043/8163 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1043/8163 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1043/8163 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1043/8163 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291 PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 07 PCI: 00:14.5 subsystem <- 1043/8163 PCI: 00:14.5 cmd <- 02 PCI: 01:00.0 cmd <- 03 PCI: 01:00.1 cmd <- 02 PCI: 03:00.0 cmd <- 03 PCI: 04:00.0 cmd <- 03 PCI: 07:00.0 cmd <- 02 PCI: 08:01.0 cmd <- 03 PCI: 08:02.0 subsystem <- 1043/8163 PCI: 08:02.0 cmd <- 02 PCI: 08:03.0 subsystem <- 1043/8163 PCI: 08:03.0 cmd <- 01 PCI: 08:03.1 cmd <- 01 PCI: 08:03.2 cmd <- 02 done. BS: BS_DEV_ENABLE times (us): entry 0 run 200 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 0 usecs POST: 0x75 CPU_CLUSTER: 0 init ... Enabling probe filter Enabling ATM mode start_eip=0x00001000, code_size=0x00000031 CPU1: stack_base 0014e000, stack_end 0014eff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 POST: 0x60 Enabling cache After Startup. CPU2: stack_base 0014d000, stack_end 0014dff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 2. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU3: stack_base 0014c000, stack_end 0014cff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 3. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU4: stack_base 0014b000, stack_end 0014bff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 4. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU5: stack_base 0014a000, stack_end 0014aff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 5. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU6: stack_base 00149000, stack_end 00149ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 6. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU7: stack_base 00148000, stack_end 00148ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 7. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU8: stack_base 00147000, stack_end 00147ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 8. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU9: stack_base 00146000, stack_end 00146ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 9. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU10: stack_base 00145000, stack_end 00145ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 10. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU11: stack_base 00144000, stack_end 00144ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 11. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU12: stack_base 00143000, stack_end 00143ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... + MTRR check #startup loops: 1. Sending STARTUP #1 to 12. After apic_write. Startup point 1. Fixed MTRRs : Waiting for send to finish... +Enabled Variable MTRRs: Enabled POST: 0x93 After Startup. CPU13: stack_base 00142000, stack_end 00142ff8 Asserting INIT. Waiting for send to finish... + MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Deasserting INIT. Waiting for send to finish... +Setting up local APIC... apic_id: 0x02 done. MTRR check #startup loops: 1. Fixed MTRRs : Sending STARTUP #1 to 13. Enabled After apic_write. Variable MTRRs: Enabled POST: 0x93 CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Disabling SMM ASeg memory Startup point 1. Waiting for send to finish... +CPU #2 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 After Startup. CPU14: stack_base 00141000, stack_end 00141ff8 Setting up local APIC...Asserting INIT. apic_id: 0x04 done. Waiting for send to finish... +Deasserting INIT. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... +siblings = 15, Disabling SMM ASeg memory #startup loops: 1. Sending STARTUP #1 to 14. CPU #4 initialized After apic_write. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Startup point 1. Waiting for send to finish... +Setting up local APIC...Setting up local APIC... apic_id: 0x03 done. After Startup. apic_id: 0x06 CPU model: AMD Opteron(TM) Processor 6272 done. CPU15: stack_base 00140000, stack_end 00140ff8 siblings = 15, Setting up local APIC...Disabling SMM ASeg memory Asserting INIT. CPU #3 initialized apic_id: 0x05 Waiting for send to finish... done. CPU model: AMD Opteron(TM) Processor 6272 +Deasserting INIT. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... siblings = 15, siblings = 15, +Disabling SMM ASeg memory #startup loops: 1. CPU #5 initialized Sending STARTUP #1 to 15. Disabling SMM ASeg memory After apic_write. CPU #6 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Startup point 1. Waiting for send to finish... +After Startup. CPU16: stack_base 0013f000, stack_end 0013fff8 Asserting INIT. Waiting for send to finish... +Setting up local APIC...Deasserting INIT. Waiting for send to finish... apic_id: 0x07 done. CPU model: AMD Opteron(TM) Processor 6272 +siblings = 15, Disabling SMM ASeg memory CPU #7 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 #startup loops: 1. Sending STARTUP #1 to 32. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU17: stack_base 0013e000, stack_end 0013eff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 33. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU18: stack_base 0013d000, stack_end 0013dff8 Asserting INIT. Setting up local APIC...Waiting for send to finish... + apic_id: 0x08 done. Deasserting INIT. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... +siblings = 15, #startup loops: 1. Disabling SMM ASeg memory Sending STARTUP #1 to 34. CPU #8 initialized After apic_write. Startup point 1. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Waiting for send to finish... +After Startup. CPU19: stack_base 0013c000, stack_end 0013cff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 35. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU20: stack_base 0013b000, stack_end 0013bff8 Setting up local APIC...Asserting INIT. apic_id: 0x09 done. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... siblings = 15, Setting up local APIC...Disabling SMM ASeg memory +Deasserting INIT. apic_id: 0x0a done. CPU #9 initialized Waiting for send to finish... CPU model: AMD Opteron(TM) Processor 6272 +#startup loops: 1. siblings = 15, Sending STARTUP #1 to 36. After apic_write. Disabling SMM ASeg memory MTRR check CPU #10 initialized Startup point 1. MTRR check Fixed MTRRs : Fixed MTRRs : Enabled Enabled Variable MTRRs: Enabled POST: 0x93 Waiting for send to finish... +nodeid = 01, coreid = 05 Variable MTRRs: Enabled POST: 0x93 After Startup. CPU21: stack_base 0013a000, stack_end 0013aff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 37. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Setting up local APIC...CPU22: stack_base 00139000, stack_end 00139ff8 apic_id: 0x0b done. Asserting INIT. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... +POST: 0x60 siblings = 15, Setting up local APIC...Enabling cache Deasserting INIT. apic_id: 0x0c done. Disabling SMM ASeg memory Waiting for send to finish... +CPU #11 initialized #startup loops: 1. CPU model: AMD Opteron(TM) Processor 6272 Sending STARTUP #1 to 38. siblings = 15, After apic_write. Startup point 1. Disabling SMM ASeg memory Waiting for send to finish... +CPU #12 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 After Startup. CPU23: stack_base 00138000, stack_end 00138ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... Setting up local APIC... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled apic_id: 0x0d done. POST: 0x93 +#startup loops: 1. CPU model: AMD Opteron(TM) Processor 6272 Sending STARTUP #1 to 39. siblings = 15, After apic_write. Startup point 1. Disabling SMM ASeg memory Waiting for send to finish... +CPU #13 initialized MTRR check After Startup. CPU24: stack_base 00137000, stack_end 00137ff8 nodeid = 02, coreid = 01 Asserting INIT. Fixed MTRRs : Enabled Variable MTRRs: Enabled Waiting for send to finish... POST: 0x60 +POST: 0x93 Setting up local APIC...Deasserting INIT. Waiting for send to finish... + apic_id: 0x0e done. #startup loops: 1. CPU model: AMD Opteron(TM) Processor 6272 Sending STARTUP #1 to 40. After apic_write. siblings = 15, Disabling SMM ASeg memory Startup point 1. Waiting for send to finish... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 +After Startup. CPU25: stack_base 00136000, stack_end 00136ff8 Asserting INIT. Waiting for send to finish... +Enabling cache Deasserting INIT. Waiting for send to finish... Setting up local APIC...+ apic_id: 0x20 done. CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Disabling SMM ASeg memory MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 #startup loops: 1. Sending STARTUP #1 to 41. After apic_write. Startup point 1. Waiting for send to finish... +Setting up local APIC...After Startup. apic_id: 0x0f done. CPU #14 initialized CPU26: stack_base 00135000, stack_end 00135ff8 CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Asserting INIT. Disabling SMM ASeg memory MTRR check CPU #15 initialized Waiting for send to finish... Setting up local APIC...CPU #16 initialized apic_id: 0x21 done. +Deasserting INIT. CPU model: AMD Opteron(TM) Processor 6272 Waiting for send to finish... siblings = 15, Disabling SMM ASeg memory +Enabling cache CPU #17 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 #startup loops: 1. Sending STARTUP #1 to 42. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU27: stack_base 00134000, stack_end 00134ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 43. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. CPU28: stack_base 00133000, stack_end 00133ff8 Setting up local APIC... apic_id: 0x22 done. Asserting INIT. Waiting for send to finish... +CPU model: AMD Opteron(TM) Processor 6272 Deasserting INIT. siblings = 15, Waiting for send to finish... +#startup loops: 1. Disabling SMM ASeg memory Sending STARTUP #1 to 44. After apic_write. MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Startup point 1. Waiting for send to finish... +After Startup. CPU29: stack_base 00132000, stack_end 00132ff8 Asserting INIT. Waiting for send to finish... +Deasserting INIT. POST: 0x60 Waiting for send to finish... + MTRR check Enabling cache Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 #startup loops: 1. Sending STARTUP #1 to 45. After apic_write. Startup point 1. Waiting for send to finish... +Setting up local APIC...Setting up local APIC...CPU #18 initialized apic_id: 0x23 done. apic_id: 0x24 done. After Startup. CPU model: AMD Opteron(TM) Processor 6272 CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, siblings = 15, CPU30: stack_base 00131000, stack_end 00131ff8 Disabling SMM ASeg memory Disabling SMM ASeg memory Asserting INIT. CPU #19 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Sending STARTUP #1 to 46. After apic_write. Startup point 1. Waiting for send to finish... + MTRR check After Startup. CPU31: stack_base 00130000, stack_end 00130ff8 CPU: family 15, model 01, stepping 02 Asserting INIT. Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 1. Setting up local APIC...CPU #20 initialized apic_id: 0x25 done. CPU model: AMD Opteron(TM) Processor 6272 Sending STARTUP #1 to 47. After apic_write. nodeid = 02, coreid = 07 siblings = 15, Setting up local APIC...Disabling SMM ASeg memory Startup point 1. CPU #21 initialized Waiting for send to finish... + apic_id: 0x26 POST: 0x60 done. After Startup. Enabling cache Initializing CPU #0 CPU model: AMD Opteron(TM) Processor 6272 CPU: vendor AMD device 600f12 CPU: family 15, model 01, stepping 02 siblings = 15, nodeid = 00, coreid = 00 Disabling SMM ASeg memory POST: 0x60 Enabling cache MTRR check CPU #22 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 CPU ID 0x80000001: 600f12 CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1 0x93 Setting up local APIC... apic_id: 0x27 done. CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Setting up local APIC...Disabling SMM ASeg memory apic_id: 0x28 done. CPU #23 initialized CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Disabling SMM ASeg memory MTRR check CPU #24 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 ??????????????????????????????????????????????????????????????????????????????????????????????????????????????D????????????????????????????????????????}?? ??????????????????@??????????????????????????????????????????????@????????????????????????????????@????????????????????????????????????????????????????{?????????????????????????????????????????????@???????????????????????????????????????????@???????????????????????????????????????????????????????????~???????????????????????????????????????????????????????H?????????@??????????????????????????????? ?????????????????????????????{?@???????g???~?????????????????3???!???????????????????????????w????????????????????????????????? ???????????????@???????l????????????????????????????????????????????????????????@????????????????????????????????????H????w?????????????????????????????????????? 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?????????? ?????????????????????????_?????????? ????????? ??????????????????????????????? ???????~??????????????????????? ??????????????????????????????????????????????????????????????????????????????????????????????????????@??????????????????????????? ??????????????????????????????@????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????@??????????????????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????D???????????????@?????????????????????????????????????????????????????????????????????????????????????????????????w???????????????????????@???? ?????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????????????????????????????????????? ???????????????????????????@?????????????????????????????_??????????????????????????????????????????????????????? ?odeid = 03, coreid = 07 Setting up local APIC...Setting up local APIC...Setting up local APIC... apic_id: 0x2d apic_id: 0x2b done. apic_id: 0x00 done. done. POST: 0x60 CPU model: AMD AMD ron(TM) Processor 6272 CPU model: essor 6272 CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, siblings = 15, siblings = 15, Disabling SMM ASeg memory Disabling SMM ASeg memory Disabling SMM ASeg memory CPU #27 initialized CPU #0 initialized MTRR check CPU #29 initialized Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Enabling cache MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 CPU_CLUSTER: 0 init finished in 85446 usecs Setting up local APIC...POST: 0x75 apic_id: 0x01 done. POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 CPU model: AMD Opteron(TM) Processor 6272 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 siblings = 15, POST: 0x75 Disabling SMM ASeg memory PCI: 00:18.0 init ... CPU #1 initialized PCI: 00:18.0 init finished in 3 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 0 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 0 usecs POST: 0x75 PCI: 00:18.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:18.3 init finished in 2 usecs POST: 0x75 PCI: 00:18.4 init ... NB: Function 4 Link Control.. done. PCI: 00:18.4 init finished in 2 usecs POST: 0x75 PCI: 00:18.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:18.5 init finished in 1 usecs POST: 0x75 PCI: 00:19.0 init ... PCI: 00:19.0 init finished in 0 usecs POST: 0x75 PCI: 00:19.1 init ... PCI: 00:19.1 init finished in 0 usecs POST: 0x75 PCI: 00:19.2 init ... PCI: 00:19.2 init finished in 0 usecs POST: 0x75 PCI: 00:19.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:19.3 init finished in 1 usecs POST: 0x75 PCI: 00:19.4 init ... NB: Function 4 Link Control.. done. PCI: 00:19.4 init finished in 2 usecs POST: 0x75 PCI: 00:19.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:19.5 init finished in 1 usecs POST: 0x75 PCI: 00:1a.0 init ... PCI: 00:1a.0 init finished in 0 usecs POST: 0x75 PCI: 00:1a.1 init ... PCI: 00:1a.1 init finished in 0 usecs POST: 0x75 PCI: 00:1a.2 init ... PCI: 00:1a.2 init finished in 0 usecs POST: 0x75 PCI: 00:1a.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:1a.3 init finished in 2 usecs POST: 0x75 PCI: 00:1a.4 init ... NB: Function 4 Link Control.. done. PCI: 00:1a.4 init finished in 2 usecs POST: 0x75 PCI: 00:1a.5 init ... NB: Function 5 Northbridge Control.. done. PCI: 00:1a.5 init finished in 1 usecs POST: 0x75 PCI: 00:1b.0 init ... PCI: 00:1b.0 init finished in 0 usecs POST: 0x75 PCI: 00:1b.1 init ... PCI: 00:1b.1 init finished in 0 usecs POST: 0x75 PCI: 00:1b.2 init ... PCI: 00:1b.2 init finished in 0 usecs POST: 0x75 PCI: 00:1b.3 init ... NB: Function 3 Misc Control.. done. PCI: 00:1b.3 init finished in 2 usecs POST: 0x75 PCI: 00:1b.4 init ... NB: Function 4 Link Control.. done. PCI: 00:1b.4 init finished in 2 usecs POST: 0x75 Setting up local APIC...PCI: 00:1b.5 init ... NB: Function 5 Northbridge Control.. apic_id: 0x2e done. done. PCI: 00:1b.5 init finished in 5 usecs POST: 0x75 PCI: 00:00.0 init ... pcie_init in sr5650_ht.c IOAPIC: Initializing IOAPIC at 0xf2000000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x01 CPU model: AMD Opteron(TM) Processor 6272 IOAPIC: Dumping registers reg 0x0000: 0x01000000 siblings = 15, reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB Disabling SMM ASeg memory IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 CPU #30 initialized MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:00.0 init finished in 47 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:11.0 init ... rev_id=15 sata_bar0=5020 sata_bar1=5040 sata_bar2=5028 sata_bar3=5044 sata_bar4=5000 sata_bar5=fa40d000 ide_bar0=5030 ide_bar1=5048 ide_bar2=5038 ide_bar3=504c Maximum SATA port count supported by silicon: 4 Setting up local APIC... apic_id: 0x2f done. CPU model: AMD Opteron(TM) Processor 6272 siblings = 15, Disabling SMM ASeg memory CPU #31 initialized SATA port 0 status = 23 drive detection done after 0 ms Primary Master device is ready after 1 tries SATA port 1 status = 23 drive detection done after 0 ms Primary Slave device is ready after 1 tries SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 PCI: 00:11.0 init finished in 5665 usecs POST: 0x75 PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 22 usecs POST: 0x75 PCI: 00:12.1 init ... PCI: 00:12.1 init finished in 21 usecs POST: 0x75 PCI: 00:12.2 init ... usb2_bar0=0xfa40e000 rpr 6.23, final dword=809e03c8 PCI: 00:12.2 init finished in 14 usecs POST: 0x75 PCI: 00:13.0 init ... PCI: 00:13.0 init finished in 21 usecs POST: 0x75 PCI: 00:13.1 init ... PCI: 00:13.1 init finished in 21 usecs POST: 0x75 PCI: 00:13.2 init ... usb2_bar0=0xfa40f000 rpr 6.23, final dword=809e03c8 PCI: 00:13.2 init finished in 14 usecs POST: 0x75 PCI: 00:14.0 init ... sm_init(). IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: Dumping registers reg 0x0000: 0x00000000 reg 0x0001: 0x00178021 reg 0x0002: 0x00000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 set power "on" after power fail ++++++++++no set NMI+++++ RTC Init sm_init() end PCI: 00:14.0 init finished in 246 usecs POST: 0x75 PCI: 00:14.1 init ... PCI: 00:14.1 init finished in 3 usecs POST: 0x75 PCI: 00:14.2 init ... base = 0xfa404000 codec_mask = 01 0(th) codec viddid: 10ec0892 PCI: 00:14.2 init finished in 2145 usecs POST: 0x75 PCI: 00:14.3 init ... lpc_init PCI: 00:14.3 init finished in 68 usecs POST: 0x75 PCI: 00:14.4 init ... PCI: 00:14.4 init finished in 17 usecs POST: 0x75 PCI: 00:14.5 init ... PCI: 00:14.5 init finished in 22 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 0 usecs POST: 0x75 PCI: 01:00.1 init ... PCI: 01:00.1 init finished in 0 usecs POST: 0x75 PCI: 03:00.0 init ... PCI: 03:00.0 init finished in 0 usecs POST: 0x75 PCI: 04:00.0 init ... PCI: 04:00.0 init finished in 0 usecs POST: 0x75 PCI: 07:00.0 init ... PCI: 07:00.0 init finished in 0 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 smbus: PCI: 00:14.0[0]->I2C: 01:2f init ... Set SMBUS controller to channel 1 Found 64 pin W83795G Nuvoton H/W Monitor W83795G/ADG work in Thermal Cruise Mode Fan CTFS(celsius) TTTI(celsius) 1 80 80 2 80 80 3 80 80 4 80 80 5 80 80 6 80 80 DTS1 current value: 2f DTS2 current value: 27 DTS3 current value: 0 DTS4 current value: 0 DTS5 current value: 0 DTS6 current value: 0 DTS7 current value: 0 DTS8 current value: 0 Set SMBUS controller to channel 0 I2C: 01:2f init finished in 244060 usecs POST: 0x75 POST: 0x75 POST: 0x75 PNP: 002e.2 init ... PNP: 002e.2 init finished in 0 usecs POST: 0x75 PNP: 002e.3 init ... PNP: 002e.3 init finished in 0 usecs POST: 0x75 PNP: 002e.5 init ... PNP: 002e.5 init finished in 16 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PNP: 002e.a init ... set power on after power fail PNP: 002e.a init finished in 11 usecs POST: 0x75 PNP: 002e.b init ... PNP: 002e.b init finished in 0 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 08:01.0 init ... ASpeed AST2050: initializing video device ast_detect_chip: AST 1100 detected ast_detect_chip: VGA not enabled on entry, requesting chip POST ast_detect_chip: Analog VGA only ast_driver_load: dram 1068000000 0 32 00800000 ASpeed VGA text mode initialized PCI: 08:01.0 init finished in 33171 usecs POST: 0x75 PCI: 08:02.0 init ... PCI: 08:02.0 init finished in 0 usecs POST: 0x75 PCI: 08:03.0 init ... PCI: 08:03.0 init finished in 0 usecs POST: 0x75 PCI: 08:03.1 init ... PCI: 08:03.1 init finished in 0 usecs POST: 0x75 PCI: 08:03.2 init ... PCI: 08:03.2 init finished in 0 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 0 PCI: 00:00.2: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 0 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:08.0: enabled 0 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:11.0: enabled 1 PCI: 00:12.0: enabled 1 PCI: 00:12.1: enabled 1 PCI: 00:12.2: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:13.2: enabled 1 PCI: 00:14.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 I2C: 01:54: enabled 1 I2C: 01:55: enabled 1 I2C: 01:56: enabled 1 I2C: 01:57: enabled 1 I2C: 01:2f: enabled 1 PCI: 00:14.1: enabled 1 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 0 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.106: enabled 0 PNP: 002e.107: enabled 0 PNP: 002e.207: enabled 0 PNP: 002e.307: enabled 0 PNP: 002e.407: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.108: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.109: enabled 0 PNP: 002e.209: enabled 0 PNP: 002e.309: enabled 0 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PNP: 002e.c: enabled 0 PNP: 002e.d: enabled 0 PNP: 002e.f: enabled 0 PNP: 004e.0: enabled 1 PCI: 00:14.4: enabled 1 PCI: 08:01.0: enabled 1 PCI: 08:02.0: enabled 1 PCI: 08:03.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 1 PCI: 00:19.3: enabled 1 PCI: 00:19.4: enabled 1 PCI: 00:19.5: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1a.1: enabled 1 PCI: 00:1a.2: enabled 1 PCI: 00:1a.3: enabled 1 PCI: 00:1a.4: enabled 1 PCI: 00:1a.5: enabled 1 PCI: 00:1b.0: enabled 1 PCI: 00:1b.1: enabled 1 PCI: 00:1b.2: enabled 1 PCI: 00:1b.3: enabled 1 PCI: 00:1b.4: enabled 1 PCI: 00:1b.5: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 05: enabled 1 APIC: 06: enabled 1 APIC: 07: enabled 1 APIC: 08: enabled 1 APIC: 09: enabled 1 APIC: 0a: enabled 1 APIC: 0b: enabled 1 APIC: 0c: enabled 1 APIC: 0d: enabled 1 APIC: 0e: enabled 1 APIC: 0f: enabled 1 APIC: 20: enabled 1 APIC: 21: enabled 1 APIC: 22: enabled 1 APIC: 23: enabled 1 APIC: 24: enabled 1 APIC: 25: enabled 1 APIC: 26: enabled 1 APIC: 27: enabled 1 APIC: 28: enabled 1 APIC: 29: enabled 1 APIC: 2a: enabled 1 APIC: 2b: enabled 1 APIC: 2c: enabled 1 APIC: 2d: enabled 1 APIC: 2e: enabled 1 APIC: 2f: enabled 1 PCI: 01:00.0: enabled 1 PCI: 01:00.1: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:00.0: enabled 1 PCI: 07:00.0: enabled 1 PCI: 08:03.1: enabled 1 PCI: 08:03.2: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 373077 exit 0 POST: 0x76 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 2 exit 0 POST: 0x77 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 POST: 0x79 POST: 0x9a Writing IRQ routing tables to 0xf0000...done. Writing IRQ routing tables to 0xbfcbf000...done. PIRQ table: 48 bytes. POST: 0x9b Wrote the mp table end at: 000f0410 - 000f08ac Wrote the mp table end at: bfcbe010 - bfcbe4ac MP table: 1196 bytes. POST: 0x9c CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 2b280 size 266b CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at bfc9a000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT pm_base: 0x0800 ACPI: added table 1/32, length now 40 ACPI: * SSDT processor_brand=AMD Opteron(TM) Processor 6272 Pstates algorithm ... Pstate_freq[0] = 2100MHz Pstate_power[0] = 5842mw Pstate_latency[0] = 5us Pstate_freq[1] = 1900MHz Pstate_power[1] = 5135mw Pstate_latency[1] = 5us Pstate_freq[2] = 1700MHz Pstate_power[2] = 4523mw Pstate_latency[2] = 5us Pstate_freq[3] = 1500MHz Pstate_power[3] = 3990mw Pstate_latency[3] = 5us Pstate_freq[4] = 1400MHz Pstate_power[4] = 3656mw Pstate_latency[4] = 5us PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 PSS: 2100MHz power 5842 control 0x0 status 0x0 PSS: 1900MHz power 5135 control 0x1 status 0x1 PSS: 1700MHz power 4523 control 0x2 status 0x2 PSS: 1500MHz power 3990 control 0x3 status 0x3 PSS: 1400MHz power 3656 control 0x4 status 0x4 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at bfc8a000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = bfc9f830 ACPI: * SRAT at bfc9f830 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=01100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=02100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=03100000, sizek=01000000 ACPI: added table 6/32, length now 60 ACPI: * SLIT at bfc9fb50 ACPI: added table 7/32, length now 64 ACPI: * IVRS at bfc9fb90 Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x01 @ 0x60 Capability: type 0x05 @ 0x68 Capability: type 0x10 @ 0x78 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0xc8 Capability: type 0x05 @ 0xd0 Capability: type 0x10 @ 0xe0 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x40 Capability: type 0x01 @ 0x44 Capability: type 0x01 @ 0x80 Capability: type 0x01 @ 0x80 Capability: type 0x01 @ 0x80 ACPI: added table 8/32, length now 68 ACPI: * HPET ACPI: added table 9/32, length now 72 ACPI: * SRAT at bfc9fca0 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=01100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=02100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=03100000, sizek=01000000 ACPI: added table 10/32, length now 76 ACPI: * SLIT at bfc9ffc0 ACPI: added table 11/32, length now 80 ACPI: * SRAT at bfca0000 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=01100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=02100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=03100000, sizek=01000000 ACPI: added table 12/32, length now 84 ACPI: * SLIT at bfca0320 ACPI: added table 13/32, length now 88 ACPI: * SRAT at bfca0360 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 SRAT: lapic cpu_index=04, node_id=00, apic_id=04 SRAT: lapic cpu_index=05, node_id=00, apic_id=05 SRAT: lapic cpu_index=06, node_id=00, apic_id=06 SRAT: lapic cpu_index=07, node_id=00, apic_id=07 SRAT: lapic cpu_index=08, node_id=01, apic_id=08 SRAT: lapic cpu_index=09, node_id=01, apic_id=09 SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f SRAT: lapic cpu_index=10, node_id=02, apic_id=20 SRAT: lapic cpu_index=11, node_id=02, apic_id=21 SRAT: lapic cpu_index=12, node_id=02, apic_id=22 SRAT: lapic cpu_index=13, node_id=02, apic_id=23 SRAT: lapic cpu_index=14, node_id=02, apic_id=24 SRAT: lapic cpu_index=15, node_id=02, apic_id=25 SRAT: lapic cpu_index=16, node_id=02, apic_id=26 SRAT: lapic cpu_index=17, node_id=02, apic_id=27 SRAT: lapic cpu_index=18, node_id=03, apic_id=28 SRAT: lapic cpu_index=19, node_id=03, apic_id=29 SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00d00000 set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=01100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=02100000, sizek=01000000 set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=03100000, sizek=01000000 ACPI: added table 14/32, length now 92 ACPI: * SLIT at bfca0680 ACPI: added table 15/32, length now 96 CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'pci10de,1081.rom' CBFS: 'pci10de,1081.rom' not found. PCI Option ROM loading disabled for PCI: 01:00.0 ACPI: done. ACPI tables: 26304 bytes. smbios_write_tables: bfc89000 Root Device (ASUS KGPE-D16) CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex) APIC: 00 (unknown) DOMAIN: 0000 (AMD Family 10h/15h Root Complex) PCI: 00:18.0 (AMD Family 10h/15h Northbridge) PCI: 00:00.0 (ATI SR5650) PCI: 00:00.1 (ATI SR5650) PCI: 00:00.2 (ATI SR5650) PCI: 00:02.0 (ATI SR5650) PCI: 00:03.0 (ATI SR5650) PCI: 00:04.0 (ATI SR5650) PCI: 00:05.0 (ATI SR5650) PCI: 00:06.0 (ATI SR5650) PCI: 00:07.0 (ATI SR5650) PCI: 00:08.0 (ATI SR5650) PCI: 00:09.0 (ATI SR5650) PCI: 00:0a.0 (ATI SR5650) PCI: 00:0b.0 (ATI SR5650) PCI: 00:0c.0 (ATI SR5650) PCI: 00:0d.0 (ATI SR5650) PCI: 00:11.0 (ATI SP5100) PCI: 00:12.0 (ATI SP5100) PCI: 00:12.1 (ATI SP5100) PCI: 00:12.2 (ATI SP5100) PCI: 00:13.0 (ATI SP5100) PCI: 00:13.1 (ATI SP5100) PCI: 00:13.2 (ATI SP5100) PCI: 00:14.0 (ATI SP5100) I2C: 01:50 (unknown) I2C: 01:51 (unknown) I2C: 01:52 (unknown) I2C: 01:53 (unknown) I2C: 01:54 (unknown) I2C: 01:55 (unknown) I2C: 01:56 (unknown) I2C: 01:57 (unknown) I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor) PCI: 00:14.1 (ATI SP5100) PCI: 00:14.2 (ATI SP5100) PCI: 00:14.3 (ATI SP5100) PNP: 002e.0 (WINBOND W83667HG-A Super I/O) PNP: 002e.1 (WINBOND W83667HG-A Super I/O) PNP: 002e.2 (WINBOND W83667HG-A Super I/O) PNP: 002e.3 (WINBOND W83667HG-A Super I/O) PNP: 002e.5 (WINBOND W83667HG-A Super I/O) PNP: 002e.106 (WINBOND W83667HG-A Super I/O) PNP: 002e.107 (WINBOND W83667HG-A Super I/O) PNP: 002e.207 (WINBOND W83667HG-A Super I/O) PNP: 002e.307 (WINBOND W83667HG-A Super I/O) PNP: 002e.407 (WINBOND W83667HG-A Super I/O) PNP: 002e.8 (WINBOND W83667HG-A Super I/O) PNP: 002e.108 (WINBOND W83667HG-A Super I/O) PNP: 002e.9 (WINBOND W83667HG-A Super I/O) PNP: 002e.109 (WINBOND W83667HG-A Super I/O) PNP: 002e.209 (WINBOND W83667HG-A Super I/O) PNP: 002e.309 (WINBOND W83667HG-A Super I/O) PNP: 002e.a (WINBOND W83667HG-A Super I/O) PNP: 002e.b (WINBOND W83667HG-A Super I/O) PNP: 002e.c (WINBOND W83667HG-A Super I/O) PNP: 002e.d (WINBOND W83667HG-A Super I/O) PNP: 002e.f (WINBOND W83667HG-A Super I/O) PNP: 004e.0 (unknown) PCI: 00:14.4 (ATI SP5100) PCI: 08:01.0 (ATI SP5100) PCI: 08:02.0 (ATI SP5100) PCI: 08:03.0 (ATI SP5100) PCI: 00:14.5 (ATI SP5100) PCI: 00:18.1 (AMD Family 10h/15h Northbridge) PCI: 00:18.2 (AMD Family 10h/15h Northbridge) PCI: 00:18.3 (AMD Family 10h/15h Northbridge) PCI: 00:18.4 (AMD Family 10h/15h Northbridge) PCI: 00:18.5 (AMD Family 10h/15h Northbridge) PCI: 00:19.0 (AMD Family 10h/15h Northbridge) PCI: 00:19.1 (AMD Family 10h/15h Northbridge) PCI: 00:19.2 (AMD Family 10h/15h Northbridge) PCI: 00:19.3 (AMD Family 10h/15h Northbridge) PCI: 00:19.4 (AMD Family 10h/15h Northbridge) PCI: 00:19.5 (AMD Family 10h/15h Northbridge) PCI: 00:1a.0 (AMD Family 10h/15h Northbridge) PCI: 00:1a.1 (AMD Family 10h/15h Northbridge) PCI: 00:1a.2 (AMD Family 10h/15h Northbridge) PCI: 00:1a.3 (AMD Family 10h/15h Northbridge) PCI: 00:1a.4 (AMD Family 10h/15h Northbridge) PCI: 00:1a.5 (AMD Family 10h/15h Northbridge) PCI: 00:1b.0 (AMD Family 10h/15h Northbridge) PCI: 00:1b.1 (AMD Family 10h/15h Northbridge) PCI: 00:1b.2 (AMD Family 10h/15h Northbridge) PCI: 00:1b.3 (AMD Family 10h/15h Northbridge) PCI: 00:1b.4 (AMD Family 10h/15h Northbridge) PCI: 00:1b.5 (AMD Family 10h/15h Northbridge) APIC: 01 (unknown) APIC: 02 (unknown) APIC: 03 (unknown) APIC: 04 (unknown) APIC: 05 (unknown) APIC: 06 (unknown) APIC: 07 (unknown) APIC: 08 (unknown) APIC: 09 (unknown) APIC: 0a (unknown) APIC: 0b (unknown) APIC: 0c (unknown) APIC: 0d (unknown) APIC: 0e (unknown) APIC: 0f (unknown) APIC: 20 (unknown) APIC: 21 (unknown) APIC: 22 (unknown) APIC: 23 (unknown) APIC: 24 (unknown) APIC: 25 (unknown) APIC: 26 (unknown) APIC: 27 (unknown) APIC: 28 (unknown) APIC: 29 (unknown) APIC: 2a (unknown) APIC: 2b (unknown) APIC: 2c (unknown) APIC: 2d (unknown) APIC: 2e (unknown) APIC: 2f (unknown) PCI: 01:00.0 (unknown) PCI: 01:00.1 (unknown) PCI: 03:00.0 (unknown) PCI: 04:00.0 (unknown) PCI: 07:00.0 (unknown) PCI: 08:03.1 (unknown) PCI: 08:03.2 (unknown) SMBIOS tables: 1746 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4012 Writing coreboot table at 0xbfcc0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000bffff: RESERVED 3. 00000000000c0000-00000000bfc88fff: RAM 4. 00000000bfc89000-00000000bfffffff: CONFIGURATION TABLES 5. 00000000c0000000-00000000cfffffff: RESERVED 6. 00000000fa400000-00000000fa403fff: RESERVED 7. 00000000feb00000-00000000feb00fff: RESERVED 8. 00000000fec00000-00000000fec00fff: RESERVED 9. 00000000fed00000-00000000fed00fff: RESERVED 10. 0000000100000000-000000103fffffff: RAM Manufacturer: ef SF: Detected W25Q16 with sector size 0x1000, total 0x200000 CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = ffe00000 size = 200000 #areas = 3 Wrote coreboot table at: bfcc0000, 0x2f4 bytes, checksum 1dcd coreboot table: 780 bytes. IMD ROOT 0. bffff000 00001000 IMD SMALL 1. bfffe000 00001000 CAR GLOBALS 2. bfff3000 0000a6c0 CONSOLE 3. bffd3000 00020000 AMDMEM INFO 4. bffc9000 000093fc ACPI RESUME 5. bfcc8000 00301000 COREBOOT 6. bfcc0000 00008000 IRQ TABLE 7. bfcbf000 00001000 SMP TABLE 8. bfcbe000 00001000 ACPI 9. bfc9a000 00024000 TCPA LOG 10. bfc8a000 00010000 SMBIOS 11. bfc89000 00000800 IMD small region: IMD ROOT 0. bfffec00 00000400 ROMSTAGE 1. bfffebe0 00000004 GDT 2. bfffe9e0 00000200 Writing AMD DCT configuration to Flash CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 's3nv' CBFS: Found @ offset 2fec0 size 10000 Manufacturer: ef SF: Detected W25Q16 with sector size 0x1000, total 0x200000 SF: Successfully erased 32768 bytes @ 0x38000 BS: BS_WRITE_TABLES times (us): entry 0 run 463365 exit 0 POST: 0x7a CBFS: 'Master Header Locator' located CBFS at [100:1fffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 54980 size 1076a Loading segment from ROM address 0xffe54ab8 code (compression=1) New segment dstaddr 0xe0ae0 memsize 0x1f520 srcaddr 0xffe54af0 filesize 0x10732 Loading segment from ROM address 0xffe54ad4 Entry Point 0x000fec22 Bounce Buffer at bfa5e000, 2269728 bytes Loading Segment: addr: 0x00000000000e0ae0 memsz: 0x000000000001f520 filesz: 0x0000000000010732 lb: [0x0000000000100000, 0x0000000000215110) Post relocation: addr: 0x00000000000e0ae0 memsz: 0x000000000001f520 filesz: 0x0000000000010732 using LZMA [ 0x000e0ae0, 00100000, 0x00100000) <- ffe54af0 dest 000e0ae0, end 00100000, bouncebuffer bfa5e000 Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 27147 exit 0 POST: 0x7b Jumping to boot code at 000fec22(bfcc0000) POST: 0xf8 CPU0: stack: 0014f000 - 00150000, lowest used address 0014f9d0, stack used: 1584 bytes entry = 0x000fec22 lb_start = 0x00100000 lb_size = 0x00115110 buffer = 0xbfa5e000 SeaBIOS (version rel-1.11.0-4-g844b864) BUILD: gcc: (coreboot toolchain v1.46 July 27th, 2017) 6.3.0 binutils: (GNU Binutils) 2.28 Found coreboot cbmem console @ bffd3000 Found mainboard ASUS KGPE-D16 Relocating init from 0x000e2120 to 0xbfc3c300 (size 52320) Found CBFS header at 0xffe00138 multiboot: eax=0, ebx=0 Found 56 PCI devices (max PCI bus is 08) Copying SMBIOS entry point from 0xbfc89000 to 0x000f66e0 Copying ACPI RSDP from 0xbfc9a000 to 0x000f66b0 Skipping MPTABLE copy due to large size (1196 bytes) Copying PIR from 0xbfcbf000 to 0x000f6680 Using pmtimer, ioport 0x820 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version rel-1.11.0-4-g844b864) EHCI init on dev 00:12.2 (regs=0xfa40e020) EHCI init on dev 00:13.2 (regs=0xfa40f020) EHCI init on dev 08:03.2 (regs=0xfa021010) UHCI init on dev 08:03.0 (io=4080) UHCI init on dev 08:03.1 (io=40a0) OHCI init on dev 00:12.0 (regs=0xfa408000) OHCI init on dev 00:12.1 (regs=0xfa409000) OHCI init on dev 00:13.0 (regs=0xfa40a000) OHCI init on dev 00:13.1 (regs=0xfa40b000) OHCI init on dev 00:14.5 (regs=0xfa40c000) ATA controller 1 at 5020/5040/0 (irq 0 dev 88) ATA controller 2 at 5028/5044/0 (irq 0 dev 88) ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1) ATA controller 4 at 170/374/0 (irq 15 dev a1) Found 0 lpt ports Found 2 serial ports ata0-0: Samsung SSD 850 PRO 256GB ATA-9 Hard-Disk (238 GiBytes) Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0 Got ps2 nak (status=51) ata1-0: ST2000DM001-1ER164 ATA-9 Hard-Disk (1863 GiBytes) Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0 Searching bootorder for: /pci@i0cf8/pci-bridge@d/*@0 USB keyboard initialized All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f6590: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=500118192 drive 0x000f6560: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=3907029168 drive 0x000f65c0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=488397168 Space available for UMB: ce000-ee000, f5f00-f6560 Returned 204800 bytes of ZoneHigh e820 map has 10 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 00000000bfc7b000 = 1 RAM 4: 00000000bfc7b000 - 00000000d0000000 = 2 RESERVED 5: 00000000fa400000 - 00000000fa404000 = 2 RESERVED 6: 00000000feb00000 - 00000000feb01000 = 2 RESERVED 7: 00000000fec00000 - 00000000fec01000 = 2 RESERVED 8: 00000000fed00000 - 00000000fed01000 = 2 RESERVED 9: 0000000100000000 - 0000001040000000 = 1 RAM enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00