<div dir="ltr">Hi,<div><br></div><div>Please try with CONFIG_FSP_M_XIP=y</div><div><br></div><div>I guess you are splitting the Fsp.fd file(python SplitFspBin.py split -f FSP_M.fd).</div><div><br></div><div>If so you can verify FSP_M.fd containing the signature.( hexdump -C FSP_M.fd | less ) Look for KBLUPD_M. I found it at offset 0x5a6cc.</div><div><br></div><div>Consider using config.kblrvp as reference : <a href="https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/refs/heads/master/sys-boot/coreboot/files/configs/config.kblrvp">https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/refs/heads/master/sys-boot/coreboot/files/configs/config.kblrvp</a></div><div><br></div><div><br></div><div>Regards,</div><div>Naresh</div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Nov 4, 2017 at 11:25 PM, Nico Huber <span dir="ltr"><<a href="mailto:nico.h@gmx.de" target="_blank">nico.h@gmx.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<span class=""><br>
On 04.11.2017 17:18, Jay Talbott wrote:<br>
> I added a post code as part of the if to confirm that the signature<br>
> mis-match was where the code was hanging. So I'm 100% certain that the<br>
> mis-match exists with this particular FSP. Also, although the signature is<br>
> the same, there are a few other differences between the header files<br>
> included with the FSP and those currently in coreboot, but nothing that<br>
> would seemingly account for this issue.<br>
<br>
</span>coreboot likely is just looking at the wrong offset. Try what Matt<br>
suggested, enable XIP. IIRC, it was necessary but I never looked into<br>
it. (Kconfig options for FSP are a mess, often only one value for an<br>
option works, sometimes it's not the default. Some ppl working on core-<br>
boot for Intel don't understand the concept of options.)<br>
<span class=""><br>
><br>
> Note that this particular FSP release on GitHub does NOT include any release<br>
> notes to indicate for which SkyLake/Kaby Lake variants (-H, -U, -Y, etc.) it<br>
> is applicable,<br>
<br>
</span>I've never seen FSP release notes that indicate it. FSP releases are<br>
rather undocumented. The idea seems to be to hide as much as possible<br>
and they succeeded: The UPDs of FSP are less documented than the regis-<br>
ters it sets.<br>
<span class=""><br>
> but someone from Intel suggested that it's only applicable to<br>
> -H.<br>
<br>
</span>I was told it would be working for -S, -H, -U and -Y, and it likely is.<br>
Maybe that someone meant it's only validated for -H?<br>
<span class=""><br>
> If that's the case, then how was the RVP7 support ever validated prior<br>
> to integration into the coreboot tree? Which FSP was actually used? And does<br>
> that even have anything to do with the signature mis-match issue? Nobody<br>
> seems to know.<br>
<br>
</span>They (Intel/OEMs/ODMs/IBVs) use a completely different line of binaries<br>
that only get published as part of their device' firmware. The interes-<br>
ting part: If you are a member of the club, you likely also have access<br>
to the FSP sources and don't need documentation that much.<br>
<span class=""><br>
><br>
> I've been trying to get support on this through various channels at Intel<br>
> that so far have not been particularly helpful, and it's extremely<br>
> frustrating. I've sent several e-mails to various folks, including the<br>
> individual that upstreamed the RVP7 support to coreboot and the individual<br>
> who published the FSP to GitHub, which remain unanswered.<br>
<br>
</span>Heh, welcome to (Intel based) coreboot. I just went through the same<br>
pain, without success. We ended up with weird workarounds because what<br>
Intel delivers lacks any sense of firmware security. Not sure if we'll<br>
end up sandboxing or rewriting FSP. (If I'd do the latter it likely<br>
won't be GPL code. Pairing that one with blobs obviously failed the<br>
project.)<br>
<div class="HOEnZb"><div class="h5"><br>
Nico<br>
<br>
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