<div dir="ltr"><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt 18pt"><span><br></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Hi Craig,
coreboot folks,<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Short answer
is no, I have not had any luck, I am still stuck!<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt">As per
suggestions from the coreboot community, I tried the following, which results
in no change (i.e. no serial debug console output and no graphics output once
coreboot transitions to payload):<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><u>Tianocore<span></span></u></p><p class="gmail-MsoListParagraphCxSpFirst" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Ensure UDK2017 CorebootPayloadPkg sets up serial
console port with 115200 bps baud, 8 data bits, no parity, 1 stop bit to match
coreboot config – However I am unsure if the com port matches coreboot’s config
(COM2)<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Compile UDK2017 with the same toolchain as
coreboot (previously compiled using VS2015 toolchain)… After this didn’t work I’m
now just using plain GCC5<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Compile UDK2017 32-bit version (as my previous
attempts focused on 64-bit). After this didn’t work I reverted back to 64-bit
version, since I would like to run 64-bit Windows 10 IoT (amongst others)<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Try using VGA BIOS Option ROM, to no avail<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>The only relevant files I could find were
vbt.bin and vbt.dat variants. I believe this is the type of video “drivers”
required by a UEFI payload (as opposed to vbios)?<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>I could not find any vbios file compatible with
Leaf Hill<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Intel provides a tool to create your own vbios
file from a template, but this seemed error-prone to me, so I have not yet
tried this<span></span></p><p class="gmail-MsoListParagraphCxSpLast" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>I managed to find a “gop_10.0_1035_64bit.zip” which
contains an IntelGopDriver.efi, but I have not tried to integrate this into the
Tianocore build because I don’t know how (yet)<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><u>SeaBIOS<span></span></u></p><p class="gmail-MsoListParagraphCxSpFirst" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>The SeaBIOS config previously used the wrong COM
port for serial console output – I changed it to COM 2 to match coreboot’s
config. The rest of the serial console settings looked fine to me<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>The SeaBIOS serial debug level was previously
set to 1, which I changed to 8<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>As per above Tianocore efforts, I was not able
to obtain a compatible VGA BIOS Option ROM, so could not try this<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Even without graphics, I would have expected the
COM port config update to show me output on the serial console, which is not
the case<span></span></p><p class="gmail-MsoListParagraphCxSpLast" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Qemu does work using SeaBIOS<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Following
discussion on another coreboot thread (“Intel Leaf Hill Coreboot Trouble”), I
tried the following: <span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><u>U-Boot<span></span></u></p><p class="gmail-MsoListParagraphCxSpFirst" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Following discussion with Craig, I realised
U-Boot requires some updates to incorporate coreboot’s device tree. <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>I followed U-Boot’s readme instructions and am
fairly certain it is now set up correctly. <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt">(see <a href="https://github.com/qemu/u-boot/blob/master/doc/README.x86">https://github.com/qemu/u-boot/blob/master/doc/README.x86</a>)<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span><span style="font-family:Arial,sans-serif;background-image:initial;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial">I tried including uboot payload directly in
coreboot's make menuconfig as well as loading it through running the cbfs
command to add it - does not seem to make a difference)</span><span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>I also applied Intel’s provided patch to support
Leaf Hill <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>The U-Boot payload gets further than Tianocore
and SeaBIOS – there is serial console output, and U-Boot loads its command line
interface<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>When running the “pci” command, the output seems
to match the coreboot device tree<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>When running “usb start” I get “no controllers
found”<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>When running “sf probe 0” I get <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt;line-height:normal;background-image:initial;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial">“Invalid bus 0
(err=-19)<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt;line-height:normal;background-image:initial;background-position:initial;background-size:initial;background-repeat:initial;background-origin:initial;background-clip:initial">Failed to
initialize SPI flash at 0:0 (error -19)”<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>I tried to poke around in the U-Boot .config. <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Manually enabling USB and SPI flash support in
this config file results in “redeclaration” of variables warnings<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Following up on these warnings, it really does
seem that USB and SPI flash is already enabled by other deeper level config
files<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>No idea why USB does not work, and have not yet
tested to see what else also does not work<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Verified that SSD SATA device works, but unable
to load Yocto from SDD (due to some strange System D initialization errors)<span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>My Yocto build was verified to work using the
precompiled payload obtained from Intel <span></span></p><p class="gmail-MsoListParagraphCxSpMiddle" style="margin-bottom:0.0001pt"><span style="font-family:Symbol">·<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>When you say U-Boot would require a lot of work,
have you identified in detail what needs to be done? Is most of it not already
done in the Intel U-Boot patch? <span></span></p><p class="gmail-MsoListParagraphCxSpLast" style="margin:0cm 0cm 0.0001pt 72pt"><span style="font-family:"Courier New"">o<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman"">
</span></span>Does the GPL license extend to code patches for
GPL projects? Am I allowed for instance to share a U-Boot code patch if it was
obtained from an Intel website that requires CNDA access?<span></span></p><p class="MsoNormal" style="margin-bottom:0.0001pt"><span> </span></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Various
payload config files attached with accompanying coreboot configs and serial
output logs. Also attached coreboot device tree (to compare to uboot's "pci" command output).</p><p class="MsoNormal" style="margin-bottom:0.0001pt"><br></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Any ideas what I'm doing wrong?</p><p class="MsoNormal" style="margin-bottom:0.0001pt"><br></p><p class="MsoNormal" style="margin-bottom:0.0001pt">Regards,</p><p class="MsoNormal" style="margin-bottom:0.0001pt">Tahnia </p></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Oct 24, 2017 at 4:51 PM, Cameron Craig <span dir="ltr"><<a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Tahnia et al,<br>
<br>
Have you had any luck with Tianocore or SeaBIOS on Leaf Hill?<br>
<br>
I would be interested to know if you (or anyone!) have managed to get any of these working on Leaf Hill.<br>
We are now also considering these, as U-Boot on Leaf Hill looks like a fair bit of work.<br>
<br>
Cheers,<br>
Cameron<br>
<br>
><br>
<br>
Cameron Craig | Graduate Software Engineer | Exterity Limited<br>
tel: <a href="tel:%2B44%201383%20828%20250" value="+441383828250">+44 1383 828 250</a> | fax: | mobile:<br>
e: <a href="mailto:Cameron.Craig@exterity.com">Cameron.Craig@exterity.com</a> | w: <a href="http://www.exterity.com" rel="noreferrer" target="_blank">www.exterity.com</a><br>
<div><div class="h5"><br>
<br>
-----Original Message-----<br>
>From: coreboot [mailto:<a href="mailto:coreboot-bounces@coreboot.org">coreboot-bounces@<wbr>coreboot.org</a>] On Behalf Of Nico<br>
>Huber<br>
>Sent: 10 October 2017 15:12<br>
>To: Tahnia Lichtenstein; <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
>Subject: Re: [coreboot] Problems changing payload on Intel Leaf Hill<br>
><br>
>Hi Tahnia,<br>
><br>
>On 10.10.2017 10:29, Tahnia Lichtenstein wrote:<br>
>> ...<br>
>><br>
>> Then I built this version of coreboot with a self-compiled payload,<br>
>> such as Tianocore UDK2017 CorebootPayloadPkg or SeaBIOS, using the<br>
>> .confg files provided by Intel for UEFI payloads or legacy payloads<br>
>> respectively (just modified for specific payload type and path, and<br>
>> disabling verified and measured boot). I stitched the coreboot output<br>
>> with the Intel-provided blobs using the exact same method as before.<br>
>> Then, in run-time, coreboot transitions to the payload and nothing<br>
>> happens from then on (i.e. no further serial debug messages, no change to<br>
>display monitor).<br>
><br>
>you've only attached config files for your coreboot but not for the payloads.<br>
>It's hard to tell what output to expect without that (e.g.<br>
>do you have serial output enabled in your SeaBIOS build? if you let the<br>
>coreboot build environment configure SeaBIOS it is enabled expli- citly). So<br>
>with the current information you've provided, it could just be that the<br>
>payloads don't try to output anything on serial.<br>
><br>
>Output on a monitor is a little more complicated and depends on each<br>
>payload. SeaBIOS expects a Video BIOS to be present. This can either be an<br>
>option ROM from a gfx adapter card (looking at your logs, you don't seem to<br>
>have one), a Video BIOS file in CBFS matching the inte- grated gfx adapter, or,<br>
>in case coreboot already configured a frame- buffer, a Video BIOS shim called<br>
>SeaVGABIOS (aka. cbvga in this case, it's a separate component in the SeaBIOS<br>
>source).<br>
><br>
>Current CorebootPayloadPkg *should* be able to use a preconfigured<br>
>framebuffer. I never tried it, though, and there are reports that it doesn't<br>
>always work... It's generally possible that Intel's precom- piled UEFI payload<br>
>has it's own gfx driver (GOP) built in.<br>
><br>
>> ...<br>
>> Am I not specifying the correct configuration options for Tianocore<br>
>> and SeaBIOS? I.e. is there more to it than just selecting the payload<br>
>> type and specifying the payload path? Do I need to configure or update<br>
>> memory addresses or ranges to match payload sizes, or some such? Do I<br>
>> need to make specific changes to the payloads' source code to support<br>
>> the platform? Any advice on how/where to start debugging?<br>
><br>
>Usually there is nothing more to specify. The best option, IMO, is to get one of<br>
>the simpler payloads (SeaBIOS should do) to output on serial.<br>
>You can also test your SeaBIOS binary in QEMU to make sure it does out- put<br>
>something.<br>
><br>
>Hope that helps,<br>
>Nico<br>
><br>
</div></div><span class="">>--<br>
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><a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/<wbr>mailman/listinfo/coreboot</a><br>
><br>
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