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<p class="MsoNormal">Hi all,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I have enabled post codes and all the debug config options in coreboot that looked useful.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">As Paul has already done, I have narrowed down the latest issue to the FspSiliconInit() stage (FSP-S).<o:p></o:p></p>
<p class="MsoNormal">The 0x93 post code is the last message I get on the serial console, and signifies that FspSiliconInit() has started but not completed.<o:p></o:p></p>
<p class="MsoNormal">See (https://github.com/coreboot/coreboot/blob/master/src/include/console/post_codes.h).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I have attached the full serial log.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I can’t see how the actual FSP blob could be at fault here.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I don’t know if this is of help, but I came across this document:<o:p></o:p></p>
<p class="MsoNormal">https://github.com/IntelFsp/FSP/raw/ApolloLake/ApolloLakeFspBinPkg/Docs/Apollo_Lake_FSP_Integration_Guide.pdf<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Specifically section 3.5.4:<o:p></o:p></p>
<p class="MsoNormal">“It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.”<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This “boot performance” may be part of the issue?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Any thoughts would be appreciated, this mailing list has been helpful so far!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Cheers,<o:p></o:p></p>
<p class="MsoNormal">Cameron<o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="ImprintUniqueID"><font style="font-family:Arial;font-size:12pt;color:#005CAB;font-weight:bold;">Cameron Craig</font><font color="#005cab" face="Arial"> |
</font><font style="font-family:Arial;font-size:12pt;color:#005CAB;">Graduate Software Engineer</font><font color="#005cab" face="Arial"> |
</font><font style="font-family:Arial;font-size:12pt;color:#005CAB;font-weight:bold;">Exterity Limited</font><br>
<font color="#005cab" size="2" face="Arial">tel: </font><font style="font-family:Arial;font-size:10pt;color:#005CAB;font-weight:normal;">+44 1383 828 250</font><font color="#005cab" size="2" face="Arial"> | fax:
</font><font color="#005cab" size="2" face="Arial"> </font> <font style="font-family:Arial;font-size:10pt;color:#005CAB;"></font> <br>
<font color="#005cab" size="2" face="Arial">e: </font><font style="font-family:Arial;font-size:10pt;color:#005CAB;">Cameron.Craig@exterity.com</font><font color="#005cab" size="2" face="Arial"> | w:
</font><font style="font-family:Arial;font-size:10pt;color:#005CAB;">www.exterity.com</font> <font style="font-family:Arial;font-size:10pt;color:#005CAB;"></font> <br>
<font style="font-family:Arial;font-size:8pt;color:#005CAB;"></font><br>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB"> Cameron
Craig <br>
<b>Sent:</b> 02 October 2017 11:19<br>
<b>To:</b> Cameron Craig; 'Paul Penz'; coreboot@coreboot.org<br>
<b>Subject:</b> RE: Re: [coreboot] Intel Leaf Hill Coreboot Trouble<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">Hi Paul,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Those changes to the IFWI blob worked great, thanks!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">I have attached the serial console log. It looks like we are in similar situations now.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">I got a hang of around 45s at “MRC: region file invalid in 'RW_VAR_MRC_CACHE”,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">and then it hangs indefinitely at the end of the log.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">I tracked the MRC cache message down to this line:
<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><a href="https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_cache.c#L272">https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/mrc_cache.c#L272</a><o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">I’m stuck again for the moment. Thanks again Paul for getting me one step closer.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">Cameron<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";mso-fareast-language:EN-GB"> coreboot
[<a href="mailto:coreboot-bounces@coreboot.org">mailto:coreboot-bounces@coreboot.org</a>]
<b>On Behalf Of </b>Cameron Craig<br>
<b>Sent:</b> 28 September 2017 16:51<br>
<b>To:</b> 'Paul Penz'; <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Intel Leaf Hill Coreboot Trouble<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">Hi Paul,</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">Great to hear I’m not the only one in this situation
</span><span style="font-family:Wingdings;color:#1F497D">J</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">I’ve just been using the IWFI file from Intel with no modifications, so I’ll look out the FIT tool and give that a go.</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">Thanks,</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D">Cameron</span><o:p></o:p></p>
<p class="MsoNormal"><span style="color:#1F497D"> </span><o:p></o:p></p>
<p class="imprintuniqueid"> <o:p></o:p></p>
<p class="imprintuniqueid" style="margin-bottom:12.0pt"><b><span style="font-family:"Arial","sans-serif";color:#005CAB">Cameron Craig</span></b><span style="font-family:"Arial","sans-serif";color:#005CAB"> | Graduate Software Engineer |
<b>Exterity Limited</b></span><br>
<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005CAB">tel: +44 1383 828 250 | fax: </span> <br>
<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005CAB">e: <a href="mailto:Cameron.Craig@exterity.com">
Cameron.Craig@exterity.com</a> | w: <a href="http://www.exterity.com">www.exterity.com</a></span> <br>
<br>
<span style="font-size:7.5pt;font-family:"Arial","sans-serif";color:#005CAB"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:#005CAB;mso-fareast-language:EN-GB">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:#005CAB;mso-fareast-language:EN-GB">
coreboot [<a href="mailto:coreboot-bounces@coreboot.org">mailto:coreboot-bounces@coreboot.org</a>]
<b>On Behalf Of </b>Paul Penz<br>
<b>Sent:</b> 28 September 2017 15:35<br>
<b>To:</b> <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Intel Leaf Hill Coreboot Trouble</span><span style="color:#005CAB"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:#005CAB"> <o:p></o:p></span></p>
<p class="MsoNormal"><span lang="DE" style="font-family:"Arial","sans-serif";color:#005CAB">Hi Cameron,</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="DE" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">I had the same problem.</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Had you modified the intel IFWI file ?</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">If not, I had done this additional:</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Download 522538_apl txe hf 3.0.11.1131 (th2 & rs1).zip from intel</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Start fit.exe</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Load the IFWI file</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Change at Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Change at Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Save</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Now I get output on the console and postcodes, but during FSP_M a long pause of ca. 45s exists and it hangs later during FSP_P initialization.</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Good luck</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-family:"Arial","sans-serif";color:#005CAB">Paul</span><span style="color:#005CAB"><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005CAB;mso-fareast-language:DE"> </span><span style="color:#005CAB"><o:p></o:p></span></p>
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<p class="MsoNormal"><span lang="DE" style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005CAB;mso-fareast-language:DE">Paul Penz</span><span style="color:#005CAB"><o:p></o:p></span></p>
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Aufsichtsratsvorsitzender: Andreas Kochhäuser<br>
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Registergericht: Amtsgericht Mainz<br>
Registernummer: HRB 7038<br>
Ust-ID: DE 149 049 790<br>
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