<div dir="ltr"><div>What a mess, Good Lord!</div><div><br></div>I am not entirely sure what you are trying to do, all of you trying to use IFWI, then Coreboot, and them U-boot. It seems to me way overkill, used for some academical purposes (as I managed to run Virtual Box VMM on Fedora VM, on the top of Virtual Box VMM on Fedora VM, on the top of VMWare Workstation, on WIN10 64). Three nested VMMs inside each other? What for (the purpose was to learn setup, and nothing more)?!<div><br></div><div>Here is what I found on the net: <a href="https://github.com/al177/edbian/wiki/edison_boot_n_dfu">https://github.com/al177/edbian/wiki/edison_boot_n_dfu</a></div><div><br></div><div>Important points: <span style="color:rgb(36,41,46);font-family:-apple-system,BlinkMacSystemFont,"Segoe UI",Helvetica,Arial,sans-serif,"Apple Color Emoji","Segoe UI Emoji","Segoe UI Symbol";font-size:16px">IFWI is the Intel FirmWare Interface, a binary blob loaded from the eMMC boot partition that executes a secondary loader from the main eMMC. IFWI blobs for the APL-I are provided by Intel and are specific for different flavors of the MID silicon.</span></div><div><br></div><div>In this lieu, what is written here, the following is my proposal (as stated in the article):</div><div><h4 style="box-sizing:border-box;margin-top:24px;margin-bottom:16px;font-size:16px;line-height:1.25;color:rgb(36,41,46);font-family:-apple-system,BlinkMacSystemFont,"Segoe UI",Helvetica,Arial,sans-serif,"Apple Color Emoji","Segoe UI Emoji","Segoe UI Symbol"">Normal IFWI eMMC boot process</h4><ol style="box-sizing:border-box;padding-left:2em;margin-top:0px;margin-bottom:16px;color:rgb(36,41,46);font-family:-apple-system,BlinkMacSystemFont,"Segoe UI",Helvetica,Arial,sans-serif,"Apple Color Emoji","Segoe UI Emoji","Segoe UI Symbol";font-size:16px"><li style="box-sizing:border-box">On-chip boot rom inits eMMC and loads IFWI from the MMC boot partitions</li><li style="box-sizing:border-box;margin-top:0.25em">IFWI looks for OSIP header at top of eMMC (MBR boot block)</li><li style="box-sizing:border-box;margin-top:0.25em">The header directs IFWI to the start, size, load address, and entry of U-Boot in eMMC</li><li style="box-sizing:border-box;margin-top:0.25em">(need clarification) If u-boot is not found, try the alt u-boot image at 5MB into the eMMC</li><li style="box-sizing:border-box;margin-top:0.25em">U-Boot is loaded into RAM and executed</li></ol></div><div>For you all, OSIP stands for OS Image Profile, and it is nothing more and less than INTEL name for very known old fashion MBR, considering DATA structure (INTEL always tend to complicate, in order to intimidate customers and force them to obey to some phony philosophy, thus making customers very dependent for the stuff which are normal and relative simplistic).</div><div><br></div><div><pre style="padding:0px;margin-top:0px;margin-bottom:0px;color:rgb(255,255,255);font-size:13.3333px;background-color:rgb(51,51,51)"><code># This is what a full OSIP header contains
# Its size is 512 bytes
# Offset Size (bytes) Description
# 0x000 4 OSIP Signature "$OS$"
# 0x004 1 Reserved
# 0x005 1 Header minor revision
# 0x006 1 Header major revision
# 0x007 1 Header checksum
# 0x008 1 Number of pointers
# 0x009 1 Number of images
# 0x00a 2 Header size
# 0x00c 20 Reserved
# 0x020 24 1st bootable image descriptor (OSII)
# 0x038 24 2nd bootable image descriptor (OSII)
# ... ... ...
# 0x170 24 15th bootable image descriptor (OSII)
# 0x188 48 Not used
# 0x1B8 4 Disk signature
# 0x1BC 2 Null (0x0000)
# 0x1BE 16 1st primary partition descriptor
# 0x1CE 16 2nd primary partition descriptor
# 0x1DE 16 3rd primary partition descriptor
# 0x1EE 16 4th primary partition descriptor
# 0x1FE 1 0x55
# 0x1FF 1 0xaa
</code></pre></div><div><code><br></code></div><div><code><font face="arial, helvetica, sans-serif">Ron (Minnich), you are added to this email, since I finally start understanding from where you are coming from (I needed two years, really to clear some obstacles)! ;-)</font></code></div><div><code><font face="arial, helvetica, sans-serif"><br></font></code></div><div><font face="arial, helvetica, sans-serif">For the rest, someone can, while using APL-I with Coreboot, and U-Boot as payload, simply skip the Coreboot phase and make his/her life much easier!</font></div><div><font face="arial, helvetica, sans-serif"><br></font></div><div><font face="arial, helvetica, sans-serif">Said that, you can all conclude what is actually IFWI, and that the FSP blob is actually redundant, Coreboot is seconday bootloader in this case. Either use Coreboot, either U-boot, you do not need both!</font></div><div><font face="arial, helvetica, sans-serif"><br></font></div><div><font face="arial, helvetica, sans-serif">IMHO.</font></div><div><code><font face="arial, helvetica, sans-serif"><br></font></code></div><div><code><font face="arial, helvetica, sans-serif">Best Regards,</font></code></div><div><code><font face="arial, helvetica, sans-serif">Zoran Stojsavljevic</font></code></div><div>_______</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Sep 28, 2017 at 6:13 PM, Cameron Craig <span dir="ltr"><<a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-GB" link="blue" vlink="purple">
<p class="m_-5927275520279805093ImprintUniqueID"></p>
<div class="m_-5927275520279805093WordSection1">
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Hi Zoran,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Thanks for the advice, I had a glimpse at your config and noticed a few differences:<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">-You target CONFIG_BOARD_INTEL_APOLLOLAKE_<wbr>RVP2 rather than CONFIG_BOARD_INTEL_LEAFHILL. Insignificant I think.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">-You include a TXE blob, I do not. This may be quite significant! I have tried including a TXE blob, only to be presented with an error (txe_error.txt)<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Once I get the FIT tool going I may be able to enable the Intel ME region and fix that error.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Cheers,<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Cameron<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">
<u></u><u></u></span></p>
<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Zoran Stojsavljevic [mailto:<a href="mailto:zoran.stojsavljevic@gmail.com" target="_blank">zoran.stojsavljevic@<wbr>gmail.com</a>]
<br>
<b>Sent:</b> 27 September 2017 20:11<br>
<b>To:</b> Cameron Craig; Martin Roth<br>
<b>Cc:</b> <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><span class=""><br>
<b>Subject:</b> Re: [coreboot] Intel Leaf Hill Coreboot Trouble<u></u><u></u></span></span></p>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/<a href="http://kernel.org" target="_blank">kernel.org</a> and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle
in Y2015, but mortally crashed somewhere in the process - For Good)!:<u></u><u></u></p><div><div class="h5">
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">[1] I did assemble APL-I Coreboot based upon <a href="http://www.intel.com/fsp" target="_blank">
www.intel.com/fsp</a> (please, choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean compilation, but there are two catches 22 to what I did (significant credits/courtesy to Martin Roth, Martin really pulled me up and survived me in this
weird FSP 2.0 crazy business of INTEL's)... ;-)<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> [A] The Coreboot release I played with is: [user@localhost coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6);<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"> [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, Deaf Hill or you name it... But I did attach my .config/CONFIG!<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">[2] As my .config (attached CONFIG) suggests, please, try with some other payload (SeaBIOS as for example, which I used);<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">[3] You need to compare my .config with yours (I have neither any time, neither any desire to do this).<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent enthusiast (I can still advise out of desperation, if you investigate and continue posting results here).<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">P.S. Martin (Roth), once again, thank you for unselfish help (I do remember)! :-)<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Zoran<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal">_______<u></u><u></u></p>
</div>
</div></div></div><div><div class="h5">
<div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <<a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a>> wrote:<u></u><u></u></p>
<div>
<div>
<p class="MsoNormal">Hi All,<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">I’m currently trying to get coreboot working on an Intel Leaf Hill development board, we are using U-Boot as a payload.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">I have managed to create a bootable image using an out of date copy of coreboot and U-Boot, provided by Intel under NDA.<u></u><u></u></p>
<p class="MsoNormal">The stitching process used to generate the image is a little ugly: a set of Windows tools are provided (or pointed at) by Intel to stitch the various blobs together to create an
8MB image.<u></u><u></u></p>
<p class="MsoNormal">We would like to move away from this process. Using the cbfs tool it looks like we are getting a legacy image composed entirely of a single CBFS.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">However, as far as I understand, the latest coreboot release (v4.6) should be capable of producing a 16MB working image without the use of external tools.<u></u><u></u></p>
<p class="MsoNormal">This is of course dependent on the provision of the correct binary blobs such as the FSP, flash descriptor and IFWI.<u></u><u></u></p>
<p class="MsoNormal">I have attached the descriptor of the IFWI image being used.<u></u><u></u></p>
<p class="MsoNormal">
<u></u><u></u></p>
<p class="MsoNormal">This is the process I have followed in order to generate a coreboot image:<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">1.<span style="font-size:7.0pt">
</span>Clone coreboot (v4.6)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">2.<span style="font-size:7.0pt">
</span>Obtain Apollo Lake FSP from Intel (<a href="https://github.com/IntelFSP/FSP" target="_blank">https://github.com/IntelFSP/<wbr>FSP</a>)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">3.<span style="font-size:7.0pt">
</span>Split FSP into its constituent parts (<a href="https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/SplitFspBin.py" target="_blank">https://raw.<wbr>githubusercontent.com/<wbr>tianocore/edk2/master/<wbr>IntelFsp2Pkg/Tools/<wbr>SplitFspBin.py</a>)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">4.<span style="font-size:7.0pt">
</span>Extract Flash Descriptor from an existing Leaf Hill UEFI image (./ifdtool --extract leaf_hill_ref_board_uefi.bin)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">5.<span style="font-size:7.0pt">
</span>Obtain IFWI image from Intel (Apollo Lake Technical Library)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">6.<span style="font-size:7.0pt">
</span>make menuconfig (config file is attached)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:72.0pt">a.<span style="font-size:7.0pt">
</span>Mainboard<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr> <wbr>
</span>i.<span style="font-size:7.0pt"> </span>Mainboard vendor (Intel)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>ii.<span style="font-size:7.0pt"> </span>Mainboard model (Leafhill)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>iii.<span style="font-size:7.0pt"> </span>[*] Use IFWI Stitching<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>iv.<span style="font-size:7.0pt"> </span>(IFWI) section in .fmd file to place IFWI blob<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>v.<span style="font-size:7.0pt"> </span>(IFWI_SPI.bin) Path to image coming from FIT Tool<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>vi.<span style="font-size:7.0pt"> </span>(descriptor.bin) path to descriptor.bin<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>vii.<span style="font-size:7.0pt"> </span>(Fsp_M.fd) path to FSP-M.Fv blob<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>viii.<span style="font-size:7.0pt"> </span>(Fsp_S.fd) path to FSP-S.Fv<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:72.0pt">b.<span style="font-size:7.0pt">
</span>Payload<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr> <wbr>
</span>i.<span style="font-size:7.0pt"> </span>Add a payload (U-Boot (Experimental))<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>ii.<span style="font-size:7.0pt"> </span>U-Boot version (v2016.1)<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt"> <wbr>
</span>iii.<span style="font-size:7.0pt"> </span>(coreboot-x86_defconfig) U-Boot config file<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph" style="margin-left:72.0pt">c.<span style="font-size:7.0pt">
</span>The rest are at Leaf Hill defaults.<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">7.<span style="font-size:7.0pt">
</span>make<u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437msolistparagraph">8.<span style="font-size:7.0pt">
</span>Flash image to Leaf Hill SPI flash<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">As far as I can tell, this process should produce a working image.<u></u><u></u></p>
<p class="MsoNormal">However it does not. My most recent attempt has managed to blink the PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages.<u></u><u></u></p>
<p class="MsoNormal">Other than that, I currently have no working theories as to what the root cause is
<span style="font-family:Wingdings">L</span><u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">Is there anything obviously wrong with this process?<u></u><u></u></p>
<p class="MsoNormal">Are there any bugs that I should be aware of relating to coreboot on an Apollo Lake platform?<u></u><u></u></p>
<p class="MsoNormal">I haven’t found a lot of documentation online to describe the exact configuration and blob usage, are there any relevant sources of documentation you could point me towards?<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">Any help to answer the above, or any other advice would be greatly appreciated.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">Cheers,<u></u><u></u></p>
<p class="MsoNormal">Cameron<u></u><u></u></p>
</div>
<p class="m_-5927275520279805093m-214314034319128437imprintuniqueid"> <u></u><u></u></p>
<p class="m_-5927275520279805093m-214314034319128437imprintuniqueid"><b><span style="font-family:"Arial","sans-serif";color:#005cab">Cameron Craig</span></b><span style="font-family:"Arial","sans-serif";color:#005cab"> | Graduate Software Engineer |
<b>Exterity Limited</b></span><br>
<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005cab">tel:
<a href="tel:+44%201383%20828250" target="_blank">+44 1383 828 250</a> | fax: </span> <br>
<span style="font-size:10.0pt;font-family:"Arial","sans-serif";color:#005cab">e: <a href="mailto:Cameron.Craig@exterity.com" target="_blank">
Cameron.Craig@exterity.com</a> | w: <a href="http://www.exterity.com" target="_blank">
www.exterity.com</a></span> <br>
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<span style="font-size:8.0pt;font-family:"Arial","sans-serif";color:#005cab">Exterity is a leading provider of IP Video and Digital Signage solutions that helps organizations to harness the power of video to communicate, educate and entertain. Our end-to-end
solutions enable you to take TV and video content directly from any source and manage its delivery, live or on demand, to any connected device via your existing network. For more information or to schedule a product demonstration, contact Exterity on
<a href="tel:+44%201383%20828250" target="_blank">+44(0)1383 828 250</a> or visit
<a href="http://www.exterity.com" target="_blank">www.exterity.com</a><br>
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Exterity Limited is registered in Scotland under No. 225313 with its registered office at St Davids House, St Davids Drive, Dalgety Bay, KY11 9NB</span><u></u><u></u></p>
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<p class="m_-5927275520279805093ImprintUniqueID"> </p>
<p class="m_-5927275520279805093ImprintUniqueID"><font style="font-family:Arial;font-size:12pt;color:#005cab;font-weight:bold">Cameron Craig</font><font color="#005cab" face="Arial"> |
</font><font style="font-family:Arial;font-size:12pt;color:#005cab">Graduate Software Engineer</font><font color="#005cab" face="Arial"> |
</font><font style="font-family:Arial;font-size:12pt;color:#005cab;font-weight:bold">Exterity Limited</font><br>
<font color="#005cab" size="2" face="Arial">tel: </font><font style="font-family:Arial;font-size:10pt;color:#005cab;font-weight:normal"><a href="tel:+44%201383%20828250" value="+441383828250" target="_blank">+44 1383 828 250</a></font><font color="#005cab" size="2" face="Arial"> | fax:
</font><font color="#005cab" size="2" face="Arial"> </font> <font style="font-family:Arial;font-size:10pt;color:#005cab"></font> <br>
<font color="#005cab" size="2" face="Arial">e: </font><font style="font-family:Arial;font-size:10pt;color:#005cab"><a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a></font><font color="#005cab" size="2" face="Arial"> | w:
</font><font style="font-family:Arial;font-size:10pt;color:#005cab"><a href="http://www.exterity.com" target="_blank">www.exterity.com</a></font> <font style="font-family:Arial;font-size:10pt;color:#005cab"></font> <br>
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