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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Zoran,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks for the advice, I had a glimpse at your config and noticed a few differences:<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">-You target CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 rather than CONFIG_BOARD_INTEL_LEAFHILL. Insignificant I think.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">-You include a TXE blob, I do not. This may be quite significant! I have tried including a TXE blob, only to be presented with an error (txe_error.txt)<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Once I get the FIT tool going I may be able to enable the Intel ME region and fix that error.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Cheers,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Cameron<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
<o:p></o:p></span></p>
<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Zoran Stojsavljevic [mailto:zoran.stojsavljevic@gmail.com]
<br>
<b>Sent:</b> 27 September 2017 20:11<br>
<b>To:</b> Cameron Craig; Martin Roth<br>
<b>Cc:</b> coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Intel Leaf Hill Coreboot Trouble<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/<a href="http://kernel.org">kernel.org</a> and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle
in Y2015, but mortally crashed somewhere in the process - For Good)!:<o:p></o:p></p>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">[1] I did assemble APL-I Coreboot based upon <a href="http://www.intel.com/fsp">
www.intel.com/fsp</a> (please, choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean compilation, but there are two catches 22 to what I did (significant credits/courtesy to Martin Roth, Martin really pulled me up and survived me in this
weird FSP 2.0 crazy business of INTEL's)... ;-)<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> [A] The Coreboot release I played with is: [user@localhost coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6);<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"> [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, Deaf Hill or you name it... But I did attach my .config/CONFIG!<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">[2] As my .config (attached CONFIG) suggests, please, try with some other payload (SeaBIOS as for example, which I used);<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">[3] You need to compare my .config with yours (I have neither any time, neither any desire to do this).<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent enthusiast (I can still advise out of desperation, if you investigate and continue posting results here).<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">P.S. Martin (Roth), once again, thank you for unselfish help (I do remember)! :-)<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
</div>
<div>
<p class="MsoNormal">Zoran<o:p></o:p></p>
</div>
<div>
<p class="MsoNormal">_______<o:p></o:p></p>
</div>
</div>
<div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<p class="MsoNormal">On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <<a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a>> wrote:<o:p></o:p></p>
<div>
<div>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Hi All,<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">I’m currently trying to get coreboot working on an Intel Leaf Hill development board, we are using U-Boot as a payload.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">I have managed to create a bootable image using an out of date copy of coreboot and U-Boot, provided by Intel under NDA.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">The stitching process used to generate the image is a little ugly: a set of Windows tools are provided (or pointed at) by Intel to stitch the various blobs together to create an
8MB image.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">We would like to move away from this process. Using the cbfs tool it looks like we are getting a legacy image composed entirely of a single CBFS.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">However, as far as I understand, the latest coreboot release (v4.6) should be capable of producing a 16MB working image without the use of external tools.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">This is of course dependent on the provision of the correct binary blobs such as the FSP, flash descriptor and IFWI.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">I have attached the descriptor of the IFWI image being used.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">
<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">This is the process I have followed in order to generate a coreboot image:<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">1.<span style="font-size:7.0pt">
</span>Clone coreboot (v4.6)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">2.<span style="font-size:7.0pt">
</span>Obtain Apollo Lake FSP from Intel (<a href="https://github.com/IntelFSP/FSP" target="_blank">https://github.com/IntelFSP/FSP</a>)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">3.<span style="font-size:7.0pt">
</span>Split FSP into its constituent parts (<a href="https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/SplitFspBin.py" target="_blank">https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/SplitFspBin.py</a>)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">4.<span style="font-size:7.0pt">
</span>Extract Flash Descriptor from an existing Leaf Hill UEFI image (./ifdtool --extract leaf_hill_ref_board_uefi.bin)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">5.<span style="font-size:7.0pt">
</span>Obtain IFWI image from Intel (Apollo Lake Technical Library)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">6.<span style="font-size:7.0pt">
</span>make menuconfig (config file is attached)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:72.0pt">a.<span style="font-size:7.0pt">
</span>Mainboard<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>i.<span style="font-size:7.0pt"> </span>Mainboard vendor (Intel)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>ii.<span style="font-size:7.0pt"> </span>Mainboard model (Leafhill)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>iii.<span style="font-size:7.0pt"> </span>[*] Use IFWI Stitching<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>iv.<span style="font-size:7.0pt"> </span>(IFWI) section in .fmd file to place IFWI blob<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>v.<span style="font-size:7.0pt"> </span>(IFWI_SPI.bin) Path to image coming from FIT Tool<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>vi.<span style="font-size:7.0pt"> </span>(descriptor.bin) path to descriptor.bin<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>vii.<span style="font-size:7.0pt"> </span>(Fsp_M.fd) path to FSP-M.Fv blob<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>viii.<span style="font-size:7.0pt"> </span>(Fsp_S.fd) path to FSP-S.Fv<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:72.0pt">b.<span style="font-size:7.0pt">
</span>Payload<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>i.<span style="font-size:7.0pt"> </span>Add a payload (U-Boot (Experimental))<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>ii.<span style="font-size:7.0pt"> </span>U-Boot version (v2016.1)<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:108.0pt"><span style="font-size:7.0pt">
</span>iii.<span style="font-size:7.0pt"> </span>(coreboot-x86_defconfig) U-Boot config file<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph" style="margin-left:72.0pt">c.<span style="font-size:7.0pt">
</span>The rest are at Leaf Hill defaults.<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">7.<span style="font-size:7.0pt">
</span>make<o:p></o:p></p>
<p class="m-214314034319128437msolistparagraph">8.<span style="font-size:7.0pt">
</span>Flash image to Leaf Hill SPI flash<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">As far as I can tell, this process should produce a working image.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">However it does not. My most recent attempt has managed to blink the PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Other than that, I currently have no working theories as to what the root cause is
<span style="font-family:Wingdings">L</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Is there anything obviously wrong with this process?<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Are there any bugs that I should be aware of relating to coreboot on an Apollo Lake platform?<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">I haven’t found a lot of documentation online to describe the exact configuration and blob usage, are there any relevant sources of documentation you could point me towards?<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Any help to answer the above, or any other advice would be greatly appreciated.<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Cheers,<o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Cameron<o:p></o:p></p>
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<p class="ImprintUniqueID"><font style="font-family:Arial;font-size:12pt;color:#005CAB;font-weight:bold;">Cameron Craig</font><font color="#005cab" face="Arial"> |
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