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<p>Thanks. Your advice is quite helpful.</p>
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<p>I got the BMP and BSF, created a vBIOS which enables the DDI2 as DP. The vBIOS has been</p>
<p>validated by IBV(AMI) BIOS.</p>
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<p>But the VBIOS can not enable DDI2 in Coreboot. I assume I still miss something.</p>
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<p>Zheng<br>
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<div id="x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Nico Huber <nico.h@gmx.de><br>
<b>Sent:</b> Wednesday, August 9, 2017 6:29 PM<br>
<b>To:</b> Zheng Bao; coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] [Broadwell-U]How the eDP, DDI1, DDI2 are enabled?</font>
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<div class="PlainText">On 08.08.2017 05:39, Zheng Bao wrote:<br>
> In text mode,<br>
> only one display can be enabled.<br>
> <br>
> <br>
> Can this enabled display port be DDI1 or DDI2?<br>
> <br>
> I just extracted VBIOS from BIOS provided on board. I assume the display ports are enabled based on the board settings.<br>
> <br>
> Can I just set register "gpu_panel_port_select" = "2" to enable DDI1?<br>
<br>
No, unfortunately not. This setting only affects the panel power sequen-<br>
cer (i.e. which port needs special care because it hosts a panel whose<br>
power is controlled by us). It shouldn't affect the VBIOS.<br>
<br>
Again, the VBIOS has many options, set in the binary. I know free tools<br>
to dump them partially, but none to set them. The regular way is to ask<br>
Intel for their Binary Modification Program (BMP, may be compatible with<br>
Intel's Binary Configuration Tool [1]) *and* a description file for the<br>
Video BIOS Table format (.bsf IIRC). That .bsf file is specific to the<br>
chipset generation (I can't find one for Broadwell, sadly), though, one<br>
for another generation might work too. Sometimes these files can be<br>
found in graphics driver packages or FSP [2].<br>
<br>
If you happen to get the Intel tool running, I advice to double check<br>
the result in a hex editor (e.g. there should be only the change you<br>
made, plus about two checksums).<br>
<br>
Nico<br>
<br>
[1] <a href="https://github.com/IntelFsp/BCT" id="LPlnk38106" previewremoved="true">
https://github.com/IntelFsp/BCT</a>
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<a id="LPImageAnchor_15023755632970.4444907747175241" style="display: table-cell; text-align: center;" href="https://github.com/IntelFsp/BCT" target="_blank"><img style="display: inline-block; max-width: 250px; max-height: 250px; height: 250px; width: 250px; border-width: 0px; vertical-align: bottom;" id="LPThumbnailImageID_15023755632970.7179467194992716" width="250" height="250" src="https://avatars1.githubusercontent.com/u/19785541?v=4&s=400"></a></div>
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<a id="LPUrlAnchor_15023755632980.6575941522681296" style="text-decoration: none;" href="https://github.com/IntelFsp/BCT" target="_blank">GitHub - IntelFsp/BCT: Binary Configuration Tool for Intel ...</a></div>
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github.com</div>
<div id="LPDescription_15023755632990.04627612554365024" style="display: block; color: rgb(102, 102, 102); font-weight: 400; font-family: "wf_segoe-ui_normal","Segoe UI","Segoe WP",Tahoma,Arial,sans-serif; font-size: 14px; line-height: 20px; max-height: 100px; overflow: hidden;">
BCT - Binary Configuration Tool for Intel(R) FSP</div>
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[2] Here is one for Kabylake (the closest I could find, might be<br>
incompatible though):<br>
<br>
<a href="https://github.com/IntelFsp/FSP/blob/Kabylake/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bsf" id="LPlnk491316" previewremoved="true">https://github.com/IntelFsp/FSP/blob/Kabylake/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bsf</a>
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<a id="LPImageAnchor_15023756241070.6452217535047734" style="display: table-cell; text-align: center;" href="https://github.com/IntelFsp/FSP/blob/Kabylake/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bsf" target="_blank"><img style="display: inline-block; max-width: 250px; max-height: 250px; height: 250px; width: 250px; border-width: 0px; vertical-align: bottom;" id="LPThumbnailImageID_15023756241080.46313013807665027" width="250" height="250" src="https://avatars1.githubusercontent.com/u/19785541?v=4&s=400"></a></div>
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<div id="LPRemovePreviewContainer_15023756241100.9083110117359879"></div>
<div id="LPTitle_15023756241100.2914971620432686" style="top: 0px; color: rgb(0, 120, 215); font-weight: 400; font-size: 21px; font-family: "wf_segoe-ui_light","Segoe UI Light","Segoe WP Light","Segoe UI","Segoe WP",Tahoma,Arial,sans-serif; line-height: 21px;">
<a id="LPUrlAnchor_15023756241100.3589715944196624" style="text-decoration: none;" href="https://github.com/IntelFsp/FSP/blob/Kabylake/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bsf" target="_blank">IntelFsp/FSP</a></div>
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github.com</div>
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Repository of FSP binaries posted by Intel</div>
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