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<p></p>
<div><span>src/soc/intel/broadwell/</span>lpc.c<br>
/* Initialize power management */<br>
// pch_power_options(dev);<br>
// pch_pm_init(dev);<br>
printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__);<br>
// pch_cg_init(dev);<br>
printk(BIOS_INFO, "%s,%d.\n", __func__, __LINE__);<br>
<br>
// pch_set_acpi_mode();<br>
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<p>I need to skip all these 4 functions to run through, otherwise it hangs. What causes this? or what setting is not right?</p>
<p><br>
</p>
<p>Zheng<br>
</p>
<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> coreboot <coreboot-bounces@coreboot.org> on behalf of Zheng Bao <fishbaoz@hotmail.com><br>
<b>Sent:</b> Tuesday, August 1, 2017 1:51 PM<br>
<b>To:</b> Matt DeVillier<br>
<b>Cc:</b> Nico Huber; stefan.reinauer@coreboot.org; coreboot@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Broadwell-U hangs at VGA init (update)</font>
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<div style="color:rgb(0,0,0)">Refcode is added and VGA BIOS passes.<br>
hangs at "<span>Set power off after power failure. </span>"<br>
<br>
It seems that the ME is not 100% right.<br>
<br>
<br>
Zheng<br>
<br>
<div>
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<div>coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 romstage starting...<br>
PM1_STS: 0000<br>
PM1_EN: 0000<br>
PM1_CNT: 00000000<br>
TCO_STS: 0000 0000<br>
GPE0_STS: 08fe08fc 10000f35 6005e200 00000000<br>
GPE0_EN: 00000000 00000000 00000000 00000000<br>
GEN_PMCON: 0200 2024 4206<br>
Previous Sleep State: S5<br>
CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz<br>
CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001f<br>
CPU: AES supported, TXT supported, VT supported<br>
MCH: device id 1604 (rev 09) is Broadwell F0<br>
PCH: device id 9cc3 (rev 03) is Broadwell U Premium<br>
IGD: device id 1626 (rev 09) is Broadwell U GT3 (15W)<br>
CPU: frequency set to 2200 MHz<br>
SPD: index 0 (GPIO65=0 GPIO67=0 GPIO68=0 GPIO69=0)<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'spd.bin'<br>
CBFS: Found @ offset 6b080 size 1000<br>
SPD: module type is DDR3<br>
SPD: module part is 99U5469-011.A01LF<br>
SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb<br>
SPD: device width 16 bits, bus width 64 bits<br>
SPD: module size is 4096 MB (per channel)<br>
<br>
ME: FW Partition Table : OK<br>
ME: Bringup Loader Failure : NO<br>
ME: Firmware Init Complete : NO<br>
ME: Manufacturing Mode : YES<br>
ME: Boot Options Present : NO<br>
ME: Update In Progress : NO<br>
ME: Current Working State : Initializing<br>
ME: Current Operation State : Bring up<br>
ME: Current Operation Mode : Security Override via Jumper<br>
ME: Error Code : Debug Failure<br>
ME: Progress Phase : BUP Phase<br>
ME: Power Management Event : Pseudo-global reset<br>
ME: Progress Phase State : 0x7b<br>
ERROR: ME failed to respond<br>
FMAP: Found "FLASH" version 1.1 at 300000.<br>
FMAP: base = ffc00000 size = 400000 #areas = 3<br>
MRC: no data in 'RW_MRC_CACHE'<br>
No MRC cache found.<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'mrc.bin'<br>
CBFS: Found @ offset 9fec0 size 36998<br>
Starting Memory Reference Code<br>
Initializing Policy<br>
Installing common PPI<br>
MRC: Starting...<br>
Initializing Memory<br>
MRC: Done.<br>
MRC Version 2.6.0 Build 0<br>
memcfg DDR3 clock 1600 MHz<br>
memcfg channel assignment: A: 0, B 1, C 2<br>
memcfg channel[0] config (00780010):<br>
enhanced interleave mode on<br>
rank interleave on<br>
DIMMA 4096 MB width x16 single rank, selected<br>
DIMMB 0 MB width x16 single rank<br>
memcfg channel[1] config (00780010):<br>
enhanced interleave mode on<br>
rank interleave on<br>
DIMMA 4096 MB width x16 single rank, selected<br>
DIMMB 0 MB width x16 single rank<br>
CBMEM:<br>
IMD: root @ 7cfff000 254 entries.<br>
IMD: root @ 7cffec00 62 entries.<br>
External stage cache:<br>
IMD: root @ 7d3ff000 254 entries.<br>
IMD: root @ 7d3fec00 62 entries.<br>
MRC data at ff7d0d9c 6246 bytes<br>
create cbmem for dimm information<br>
MLB: board version Unknown<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'fallback/ramstage'<br>
CBFS: Found @ offset 1c400 size 144b9<br>
Decompressing stage fallback/ramstage @ 0x7cf97fc0 (257104 bytes)<br>
Loading module at 7cf98000 with entry 7cf98000. filesize: 0x2c380 memsize: 0x3ec10<br>
Processing 2817 relocs. Offset value of 0x7ce98000<br>
<br>
<br>
coreboot-4.6-891-gca74434-dirty Fri Jul 28 06:45:02 UTC 2017 ramstage starting...<br>
Normal boot.<br>
BS: BS_PRE_DEVICE times (us): entry 5 run 7 exit 5<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'fallback/refcode'<br>
CBFS: Found @ offset 30900 size 1274b<br>
Decompressing stage fallback/refcode @ 0x7cf62fc0 (201528 bytes)<br>
Loading module at 7cf63000 with entry 7cf63000. filesize: 0x29b38 memsize: 0x312f8<br>
Processing 1695 relocs. Offset value of 0x7cf63000<br>
Initializing Policy<br>
Installing common PPI<br>
PEI: Starting...<br>
Initializing System Agent<br>
Initializing PCH<br>
PEI: Done.<br>
BS: BS_DEV_INIT_CHIPS times (us): entry 5 run 94299 exit 5<br>
Enumerating buses...<br>
Show all devs... Before device enumeration.<br>
Root Device: enabled 1<br>
CPU_CLUSTER: 0: enabled 1<br>
APIC: 00: enabled 1<br>
DOMAIN: 0000: enabled 1<br>
PCI: 00:00.0: enabled 1<br>
PCI: 00:02.0: enabled 1<br>
PCI: 00:03.0: enabled 1<br>
PCI: 00:13.0: enabled 1<br>
PCI: 00:14.0: enabled 1<br>
PCI: 00:15.0: enabled 1<br>
PCI: 00:15.1: enabled 1<br>
PCI: 00:15.2: enabled 1<br>
PCI: 00:15.3: enabled 1<br>
PCI: 00:15.4: enabled 0<br>
PCI: 00:15.5: enabled 0<br>
PCI: 00:15.6: enabled 0<br>
PCI: 00:16.0: enabled 1<br>
PCI: 00:16.1: enabled 0<br>
PCI: 00:16.2: enabled 0<br>
PCI: 00:16.3: enabled 0<br>
PCI: 00:17.0: enabled 0<br>
PCI: 00:19.0: enabled 0<br>
PCI: 00:1b.0: enabled 0<br>
PCI: 00:1c.0: enabled 0<br>
PCI: 00:1c.1: enabled 0<br>
PCI: 00:1c.2: enabled 1<br>
PCI: 00:1c.3: enabled 0<br>
PCI: 00:1c.4: enabled 0<br>
PCI: 00:1c.5: enabled 0<br>
PCI: 00:1d.0: enabled 0<br>
PCI: 00:1e.0: enabled 0<br>
PCI: 00:1f.0: enabled 1<br>
PNP: 0c31.0: enabled 1<br>
PCI: 00:1f.2: enabled 1<br>
PCI: 00:1f.3: enabled 0<br>
PCI: 00:1f.6: enabled 1<br>
Compare with tree...<br>
Root Device: enabled 1<br>
CPU_CLUSTER: 0: enabled 1<br>
APIC: 00: enabled 1<br>
DOMAIN: 0000: enabled 1<br>
PCI: 00:00.0: enabled 1<br>
PCI: 00:02.0: enabled 1<br>
PCI: 00:03.0: enabled 1<br>
PCI: 00:13.0: enabled 1<br>
PCI: 00:14.0: enabled 1<br>
PCI: 00:15.0: enabled 1<br>
PCI: 00:15.1: enabled 1<br>
PCI: 00:15.2: enabled 1<br>
PCI: 00:15.3: enabled 1<br>
PCI: 00:15.4: enabled 0<br>
PCI: 00:15.5: enabled 0<br>
PCI: 00:15.6: enabled 0<br>
PCI: 00:16.0: enabled 1<br>
PCI: 00:16.1: enabled 0<br>
PCI: 00:16.2: enabled 0<br>
PCI: 00:16.3: enabled 0<br>
PCI: 00:17.0: enabled 0<br>
PCI: 00:19.0: enabled 0<br>
PCI: 00:1b.0: enabled 0<br>
PCI: 00:1c.0: enabled 0<br>
PCI: 00:1c.1: enabled 0<br>
PCI: 00:1c.2: enabled 1<br>
PCI: 00:1c.3: enabled 0<br>
PCI: 00:1c.4: enabled 0<br>
PCI: 00:1c.5: enabled 0<br>
PCI: 00:1d.0: enabled 0<br>
PCI: 00:1e.0: enabled 0<br>
PCI: 00:1f.0: enabled 1<br>
PNP: 0c31.0: enabled 1<br>
PCI: 00:1f.2: enabled 1<br>
PCI: 00:1f.3: enabled 0<br>
PCI: 00:1f.6: enabled 1<br>
Root Device scanning...<br>
root_dev_scan_bus for Root Device<br>
CPU_CLUSTER: 0 enabled<br>
DOMAIN: 0000 enabled<br>
DOMAIN: 0000 scanning...<br>
PCI: pci_scan_bus for bus 00<br>
PCI: 00:00.0 [8086/0000] ops<br>
PCI: 00:00.0 [8086/1604] enabled<br>
PCI: 00:02.0 [8086/0000] ops<br>
PCI: 00:02.0 [8086/1626] enabled<br>
PCI: 00:03.0 [8086/0000] ops<br>
PCI: 00:03.0 [8086/160c] enabled<br>
PCI: 00:13.0 [8086/0000] ops<br>
PCI: 00:13.0 [8086/9cb6] enabled<br>
PCI: 00:14.0 [8086/0000] ops<br>
PCI: 00:14.0 [8086/9cb1] enabled<br>
PCI: 00:15.0 [8086/0000] ops<br>
PCI: 00:15.0 [8086/9ce0] enabled<br>
PCI: 00:15.1 [8086/0000] ops<br>
PCI: 00:15.1 [8086/9ce1] enabled<br>
PCI: 00:15.2 [8086/0000] ops<br>
PCI: 00:15.2 [8086/9ce2] enabled<br>
PCI: 00:15.3 [8086/0000] ops<br>
PCI: 00:15.3 [8086/9ce5] enabled<br>
PCI: 00:15.4: Disabling device<br>
PCI: 00:15.5: Disabling device<br>
PCI: 00:15.6: Disabling device<br>
PCI: 00:16.0 [8086/0000] ops<br>
PCI: 00:16.0 [8086/9cba] enabled<br>
PCI: 00:16.1: Disabling device<br>
PCI: 00:16.2: Disabling device<br>
PCI: 00:16.3: Disabling device<br>
PCI: 00:17.0: Disabling device<br>
PCI: 00:19.0: Disabling device<br>
PCI: 00:1b.0 [8086/0000] ops<br>
HDA disabled, I/O buffers routed to ADSP<br>
PCI: 00:1b.0 [8086/9ca0] disabled<br>
PCI: 00:1c.0 [8086/0000] bus ops<br>
PCI: 00:1c.0 [8086/9c90] disabled<br>
PCI: 00:1c.1 [8086/0000] bus ops<br>
PCI: 00:1c.1 [8086/9c92] disabled<br>
PCI: 00:1c.2 [8086/0000] bus ops<br>
PCIe Root Port 3 ASPM is enabled<br>
PCI: 00:1c.2 [8086/9c94] enabled<br>
PCI: 00:1c.3 [8086/0000] bus ops<br>
PCI: 00:1c.3 [8086/9c96] disabled<br>
PCI: 00:1c.4 [8086/0000] bus ops<br>
PCI: 00:1c.4 [8086/9c98] disabled<br>
PCI: 00:1c.5 [8086/0000] bus ops<br>
PCI: 00:1c.0: Disabling device<br>
PCI: 00:1c.1: Disabling device<br>
PCI: 00:1c.3: Disabling device<br>
PCI: 00:1c.4: Disabling device<br>
PCI: 00:1c.4: Timeout waiting for 328h<br>
PCI: 00:1c.5: Disabling device<br>
PCI: 00:1c.5: Timeout waiting for 328h<br>
PCH: PCIe map 1c.2 -> 1c.0<br>
PCH: PCIe map 1c.0 -> 1c.1<br>
PCH: PCIe map 1c.1 -> 1c.2<br>
PCH: RPFN 0x00543210 -> 0x00dcb0a9<br>
PCI: 00:1c.5 [8086/9c9a] disabled<br>
PCI: 00:1e.0: Disabling device<br>
PCI: 00:1f.0 [8086/0000] bus ops<br>
PCI: 00:1f.0 [8086/9cc3] enabled<br>
PCI: 00:1f.2 [8086/0000] ops<br>
PCI: 00:1f.2 [8086/9c83] enabled<br>
PCI: 00:1f.3: Disabling device<br>
PCI: 00:1f.6 [8086/9ca4] enabled<br>
PCI: 00:1c.0 scanning...<br>
do_pci_scan_bridge for PCI: 00:1c.0<br>
PCI: pci_scan_bus for bus 01<br>
scan_bus: scanning of bus PCI: 00:1c.0 took 8121 usecs<br>
PCI: 00:1f.0 scanning...<br>
scan_lpc_bus for PCI: 00:1f.0<br>
PNP: 0c31.0 enabled<br>
scan_lpc_bus for PCI: 00:1f.0 done<br>
scan_bus: scanning of bus PCI: 00:1f.0 took 9898 usecs<br>
scan_bus: scanning of bus DOMAIN: 0000 took 220433 usecs<br>
root_dev_scan_bus for Root Device done<br>
scan_bus: scanning of bus Root Device took 238194 usecs<br>
done<br>
BS: BS_DEV_ENUMERATE times (us): entry 5 run 412960 exit 4<br>
found VGA at PCI: 00:02.0<br>
Setting up VGA for PCI: 00:02.0<br>
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000<br>
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device<br>
Allocating resources...<br>
Reading resources...<br>
Root Device read_resources bus 0 link: 0<br>
CPU_CLUSTER: 0 read_resources bus 0 link: 0<br>
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done<br>
DOMAIN: 0000 read_resources bus 0 link: 0<br>
mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xe0000000-0xe3ffffff.<br>
mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.<br>
mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.<br>
mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.<br>
mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.<br>
mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.<br>
MC MAP: TOM: 0x200000000<br>
MC MAP: TOUUD: 0x280000000<br>
MC MAP: MESEG_BASE: 0x7ffff00000<br>
MC MAP: MESEG_LIMIT: 0xfffff<br>
MC MAP: REMAP_BASE: 0x200000000<br>
MC MAP: REMAP_LIMIT: 0x27fffffff<br>
MC MAP: TOLUD: 0x80000000<br>
MC MAP: BGSM: 0x7d800000<br>
MC MAP: BDSM: 0x7e000000<br>
MC MAP: TESGMB: 0x7d000000<br>
MC MAP: GGC: 0x1c1<br>
PCI: 00:1c.0 read_resources bus 1 link: 0<br>
PCI: 00:1c.0 read_resources bus 1 link: 0 done<br>
PCI: 00:1f.0 read_resources bus 0 link: 0<br>
PNP: 0c31.0 missing read_resources<br>
PCI: 00:1f.0 read_resources bus 0 link: 0 done<br>
DOMAIN: 0000 read_resources bus 0 link: 0 done<br>
Root Device read_resources bus 0 link: 0 done<br>
Done reading resources.<br>
Show resources in subtree (Root Device)...After reading.<br>
Root Device child on link 0 CPU_CLUSTER: 0<br>
CPU_CLUSTER: 0 child on link 0 APIC: 00<br>
APIC: 00<br>
DOMAIN: 0000 child on link 0 PCI: 00:00.0<br>
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000<br>
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100<br>
PCI: 00:00.0<br>
PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60<br>
PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48<br>
PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68<br>
PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40<br>
PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420<br>
PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408<br>
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0<br>
PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1<br>
PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2<br>
PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3<br>
PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4<br>
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5<br>
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6<br>
PCI: 00:02.0<br>
PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10<br>
PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18<br>
PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20<br>
PCI: 00:03.0<br>
PCI: 00:03.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10<br>
PCI: 00:13.0<br>
PCI: 00:13.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10<br>
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14<br>
PCI: 00:14.0<br>
PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10<br>
PCI: 00:15.0<br>
PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10<br>
PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14<br>
PCI: 00:15.1<br>
PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10<br>
PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14<br>
PCI: 00:15.2<br>
PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10<br>
PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14<br>
PCI: 00:15.3<br>
PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10<br>
PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14<br>
PCI: 00:15.4<br>
PCI: 00:15.5<br>
PCI: 00:15.6<br>
PCI: 00:16.0<br>
PCI: 00:16.0 resource base 0 size 20 align 12 gran 5 limit ffffffffffffffff flags 201 index 10<br>
PCI: 00:16.1<br>
PCI: 00:16.2<br>
PCI: 00:16.3<br>
PCI: 00:17.0<br>
PCI: 00:19.0<br>
PCI: 00:1b.0<br>
PCI: 00:1c.1<br>
PCI: 00:1c.2<br>
PCI: 00:1c.0<br>
PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c<br>
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24<br>
PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20<br>
PCI: 00:1c.3<br>
PCI: 00:1c.4<br>
PCI: 00:1c.5<br>
PCI: 00:1d.0<br>
PCI: 00:1e.0<br>
PCI: 00:1f.0 child on link 0 PNP: 0c31.0<br>
PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe<br>
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0<br>
PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48<br>
PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40<br>
PNP: 0c31.0<br>
PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70<br>
PCI: 00:1f.2<br>
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10<br>
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14<br>
PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18<br>
PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c<br>
PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20<br>
PCI: 00:1f.2 resource base 0 size 8000 align 15 gran 15 limit ffffffff flags 200 index 24<br>
PCI: 00:1f.3<br>
PCI: 00:1f.6<br>
PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10<br>
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff<br>
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff<br>
PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done<br>
PCI: 00:02.0 20 * [0x0 - 0x3f] io<br>
PCI: 00:1f.2 20 * [0x40 - 0x5f] io<br>
PCI: 00:1f.2 10 * [0x60 - 0x67] io<br>
PCI: 00:1f.2 18 * [0x68 - 0x6f] io<br>
PCI: 00:1f.2 14 * [0x70 - 0x73] io<br>
PCI: 00:1f.2 1c * [0x74 - 0x77] io<br>
DOMAIN: 0000 io: base: 78 size: 78 align: 6 gran: 0 limit: ffff done<br>
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff<br>
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff<br>
PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done<br>
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff<br>
PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done<br>
PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem<br>
PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem<br>
PCI: 00:13.0 10 * [0x11000000 - 0x110fffff] mem<br>
PCI: 00:14.0 10 * [0x11100000 - 0x1110ffff] mem<br>
PCI: 00:1f.2 24 * [0x11110000 - 0x11117fff] mem<br>
PCI: 00:03.0 10 * [0x11118000 - 0x1111bfff] mem<br>
PCI: 00:13.0 14 * [0x1111c000 - 0x1111cfff] mem<br>
PCI: 00:15.0 10 * [0x1111d000 - 0x1111dfff] mem<br>
PCI: 00:15.0 14 * [0x1111e000 - 0x1111efff] mem<br>
PCI: 00:15.1 10 * [0x1111f000 - 0x1111ffff] mem<br>
PCI: 00:15.1 14 * [0x11120000 - 0x11120fff] mem<br>
PCI: 00:15.2 10 * [0x11121000 - 0x11121fff] mem<br>
PCI: 00:15.2 14 * [0x11122000 - 0x11122fff] mem<br>
PCI: 00:15.3 10 * [0x11123000 - 0x11123fff] mem<br>
PCI: 00:15.3 14 * [0x11124000 - 0x11124fff] mem<br>
PCI: 00:1f.6 10 * [0x11125000 - 0x11125fff] mem<br>
PCI: 00:16.0 10 * [0x11126000 - 0x1112601f] mem<br>
DOMAIN: 0000 mem: base: 11126020 size: 11126020 align: 28 gran: 0 limit: ffffffff done<br>
avoid_fixed_resources: DOMAIN: 0000<br>
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff<br>
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff<br>
constrain_resources: PCI: 00:00.0 60 base e0000000 limit e3ffffff mem (fixed)<br>
constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)<br>
constrain_resources: PCI: 00:00.0 01 base 000c0000 limit 7cffffff mem (fixed)<br>
constrain_resources: PCI: 00:00.0 02 base 7d000000 limit 7d7fffff mem (fixed)<br>
constrain_resources: PCI: 00:00.0 03 base 7d800000 limit 7fffffff mem (fixed)<br>
constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)<br>
constrain_resources: PCI: 00:1f.0 48 base 00001400 limit 000017ff io (fixed)<br>
skipping PNP: 0c31.0@70 fixed resource, size=0!<br>
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001800 limit 0000ffff<br>
avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff<br>
Setting resources...<br>
DOMAIN: 0000 io: base:1800 size:78 align:6 gran:0 limit:ffff<br>
PCI: 00:02.0 20 * [0x1800 - 0x183f] io<br>
PCI: 00:1f.2 20 * [0x1840 - 0x185f] io<br>
PCI: 00:1f.2 10 * [0x1860 - 0x1867] io<br>
PCI: 00:1f.2 18 * [0x1868 - 0x186f] io<br>
PCI: 00:1f.2 14 * [0x1870 - 0x1873] io<br>
PCI: 00:1f.2 1c * [0x1874 - 0x1877] io<br>
DOMAIN: 0000 io: next_base: 1878 size: 78 align: 6 gran: 0 done<br>
PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff<br>
PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done<br>
DOMAIN: 0000 mem: base:c0000000 size:11126020 align:28 gran:0 limit:dfffffff<br>
PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem<br>
PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem<br>
PCI: 00:13.0 10 * [0xd1000000 - 0xd10fffff] mem<br>
PCI: 00:14.0 10 * [0xd1100000 - 0xd110ffff] mem<br>
PCI: 00:1f.2 24 * [0xd1110000 - 0xd1117fff] mem<br>
PCI: 00:03.0 10 * [0xd1118000 - 0xd111bfff] mem<br>
PCI: 00:13.0 14 * [0xd111c000 - 0xd111cfff] mem<br>
PCI: 00:15.0 10 * [0xd111d000 - 0xd111dfff] mem<br>
PCI: 00:15.0 14 * [0xd111e000 - 0xd111efff] mem<br>
PCI: 00:15.1 10 * [0xd111f000 - 0xd111ffff] mem<br>
PCI: 00:15.1 14 * [0xd1120000 - 0xd1120fff] mem<br>
PCI: 00:15.2 10 * [0xd1121000 - 0xd1121fff] mem<br>
PCI: 00:15.2 14 * [0xd1122000 - 0xd1122fff] mem<br>
PCI: 00:15.3 10 * [0xd1123000 - 0xd1123fff] mem<br>
PCI: 00:15.3 14 * [0xd1124000 - 0xd1124fff] mem<br>
PCI: 00:1f.6 10 * [0xd1125000 - 0xd1125fff] mem<br>
PCI: 00:16.0 10 * [0xd1126000 - 0xd112601f] mem<br>
DOMAIN: 0000 mem: next_base: d1126020 size: 11126020 align: 28 gran: 0 done<br>
PCI: 00:1c.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff<br>
PCI: 00:1c.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done<br>
PCI: 00:1c.0 mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff<br>
PCI: 00:1c.0 mem: next_base: dfffffff size: 0 align: 20 gran: 20 done<br>
Root Device assign_resources, bus 0 link: 0<br>
DOMAIN: 0000 assign_resources, bus 0 link: 0<br>
PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64<br>
PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64<br>
PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io<br>
PCI: 00:03.0 10 <- [0x00d1118000 - 0x00d111bfff] size 0x00004000 gran 0x0e mem64<br>
PCI: 00:13.0 10 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 mem<br>
PCI: 00:13.0 14 <- [0x00d111c000 - 0x00d111cfff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:14.0 10 <- [0x00d1100000 - 0x00d110ffff] size 0x00010000 gran 0x10 mem64<br>
PCI: 00:15.0 10 <- [0x00d111d000 - 0x00d111dfff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.0 14 <- [0x00d111e000 - 0x00d111efff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.1 10 <- [0x00d111f000 - 0x00d111ffff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.1 14 <- [0x00d1120000 - 0x00d1120fff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.2 10 <- [0x00d1121000 - 0x00d1121fff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.2 14 <- [0x00d1122000 - 0x00d1122fff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.3 10 <- [0x00d1123000 - 0x00d1123fff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:15.3 14 <- [0x00d1124000 - 0x00d1124fff] size 0x00001000 gran 0x0c mem<br>
PCI: 00:16.0 10 <- [0x00d1126000 - 0x00d112601f] size 0x00000020 gran 0x05 mem64<br>
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io<br>
PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem<br>
PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem<br>
PCI: 00:1f.0 assign_resources, bus 0 link: 0<br>
PNP: 0c31.0 missing set_resources<br>
PCI: 00:1f.0 assign_resources, bus 0 link: 0<br>
PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io<br>
PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io<br>
PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io<br>
PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io<br>
PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io<br>
PCI: 00:1f.2 24 <- [0x00d1110000 - 0x00d1117fff] size 0x00008000 gran 0x0f mem<br>
PCI: 00:1f.6 10 <- [0x00d1125000 - 0x00d1125fff] size 0x00001000 gran 0x0c mem64<br>
DOMAIN: 0000 assign_resources, bus 0 link: 0<br>
Root Device assign_resources, bus 0 link: 0<br>
Done setting resources.<br>
Show resources in subtree (Root Device)...After assigning values.<br>
Root Device child on link 0 CPU_CLUSTER: 0<br>
CPU_CLUSTER: 0 child on link 0 APIC: 00<br>
APIC: 00<br>
DOMAIN: 0000 child on link 0 PCI: 00:00.0<br>
DOMAIN: 0000 resource base 1800 size 78 align 6 gran 0 limit ffff flags 40040100 index 10000000<br>
DOMAIN: 0000 resource base c0000000 size 11126020 align 28 gran 0 limit dfffffff flags 40040200 index 10000100<br>
PCI: 00:00.0<br>
PCI: 00:00.0 resource base e0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60<br>
PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 48<br>
PCI: 00:00.0 resource base fed18000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 68<br>
PCI: 00:00.0 resource base fed19000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 40<br>
PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 5420<br>
PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5408<br>
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0<br>
PCI: 00:00.0 resource base c0000 size 7cf40000 align 0 gran 0 limit 0 flags e0004200 index 1<br>
PCI: 00:00.0 resource base 7d000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 2<br>
PCI: 00:00.0 resource base 7d800000 size 2800000 align 0 gran 0 limit 0 flags f0000200 index 3<br>
PCI: 00:00.0 resource base 100000000 size 180000000 align 0 gran 0 limit 0 flags e0004200 index 4<br>
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 5<br>
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 6<br>
PCI: 00:02.0<br>
PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10<br>
PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18<br>
PCI: 00:02.0 resource base 1800 size 40 align 6 gran 6 limit 183f flags 60000100 index 20<br>
PCI: 00:03.0<br>
PCI: 00:03.0 resource base d1118000 size 4000 align 14 gran 14 limit d111bfff flags 60000201 index 10<br>
PCI: 00:13.0<br>
PCI: 00:13.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60000200 index 10<br>
PCI: 00:13.0 resource base d111c000 size 1000 align 12 gran 12 limit d111cfff flags 60000200 index 14<br>
PCI: 00:14.0<br>
PCI: 00:14.0 resource base d1100000 size 10000 align 16 gran 16 limit d110ffff flags 60000201 index 10<br>
PCI: 00:15.0<br>
PCI: 00:15.0 resource base d111d000 size 1000 align 12 gran 12 limit d111dfff flags 60000200 index 10<br>
PCI: 00:15.0 resource base d111e000 size 1000 align 12 gran 12 limit d111efff flags 60000200 index 14<br>
PCI: 00:15.1<br>
PCI: 00:15.1 resource base d111f000 size 1000 align 12 gran 12 limit d111ffff flags 60000200 index 10<br>
PCI: 00:15.1 resource base d1120000 size 1000 align 12 gran 12 limit d1120fff flags 60000200 index 14<br>
PCI: 00:15.2<br>
PCI: 00:15.2 resource base d1121000 size 1000 align 12 gran 12 limit d1121fff flags 60000200 index 10<br>
PCI: 00:15.2 resource base d1122000 size 1000 align 12 gran 12 limit d1122fff flags 60000200 index 14<br>
PCI: 00:15.3<br>
PCI: 00:15.3 resource base d1123000 size 1000 align 12 gran 12 limit d1123fff flags 60000200 index 10<br>
PCI: 00:15.3 resource base d1124000 size 1000 align 12 gran 12 limit d1124fff flags 60000200 index 14<br>
PCI: 00:15.4<br>
PCI: 00:15.5<br>
PCI: 00:15.6<br>
PCI: 00:16.0<br>
PCI: 00:16.0 resource base d1126000 size 20 align 12 gran 5 limit d112601f flags 60000201 index 10<br>
PCI: 00:16.1<br>
PCI: 00:16.2<br>
PCI: 00:16.3<br>
PCI: 00:17.0<br>
PCI: 00:19.0<br>
PCI: 00:1b.0<br>
PCI: 00:1c.1<br>
PCI: 00:1c.2<br>
PCI: 00:1c.0<br>
PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c<br>
PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24<br>
PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20<br>
PCI: 00:1c.3<br>
PCI: 00:1c.4<br>
PCI: 00:1c.5<br>
PCI: 00:1d.0<br>
PCI: 00:1e.0<br>
PCI: 00:1f.0 child on link 0 PNP: 0c31.0<br>
PCI: 00:1f.0 resource base fec00000 size 1400000 align 0 gran 0 limit 0 flags c0000200 index 31fe<br>
PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0<br>
PCI: 00:1f.0 resource base 1400 size 400 align 0 gran 0 limit 0 flags c0000100 index 48<br>
PCI: 00:1f.0 resource base 1000 size 100 align 0 gran 0 limit 0 flags c0000100 index 40<br>
PNP: 0c31.0<br>
PNP: 0c31.0 resource base a size 0 align 0 gran 0 limit 0 flags c0000400 index 70<br>
PCI: 00:1f.2<br>
PCI: 00:1f.2 resource base 1860 size 8 align 3 gran 3 limit 1867 flags 60000100 index 10<br>
PCI: 00:1f.2 resource base 1870 size 4 align 2 gran 2 limit 1873 flags 60000100 index 14<br>
PCI: 00:1f.2 resource base 1868 size 8 align 3 gran 3 limit 186f flags 60000100 index 18<br>
PCI: 00:1f.2 resource base 1874 size 4 align 2 gran 2 limit 1877 flags 60000100 index 1c<br>
PCI: 00:1f.2 resource base 1840 size 20 align 5 gran 5 limit 185f flags 60000100 index 20<br>
PCI: 00:1f.2 resource base d1110000 size 8000 align 15 gran 15 limit d1117fff flags 60000200 index 24<br>
PCI: 00:1f.3<br>
PCI: 00:1f.6<br>
PCI: 00:1f.6 resource base d1125000 size 1000 align 12 gran 12 limit d1125fff flags 60000201 index 10<br>
Done allocating resources.<br>
BS: BS_DEV_RESOURCES times (us): entry 4 run 1651122 exit 4<br>
Enabling resources...<br>
PCI: 00:00.0 subsystem <- 8086/1604<br>
PCI: 00:00.0 cmd <- 06<br>
PCI: 00:02.0 subsystem <- 8086/1626<br>
PCI: 00:02.0 cmd <- 07<br>
PCI: 00:03.0 subsystem <- 8086/160c<br>
PCI: 00:03.0 cmd <- 07<br>
PCI: 00:13.0 subsystem <- 8086/9cb6<br>
PCI: 00:13.0 cmd <- 107<br>
PCI: 00:14.0 subsystem <- 8086/9cb1<br>
PCI: 00:14.0 cmd <- 107<br>
PCI: 00:15.0 subsystem <- 8086/9ce0<br>
PCI: 00:15.0 cmd <- 107<br>
PCI: 00:15.1 subsystem <- 8086/9ce1<br>
PCI: 00:15.1 cmd <- 107<br>
PCI: 00:15.2 subsystem <- 8086/9ce2<br>
PCI: 00:15.2 cmd <- 107<br>
PCI: 00:15.3 subsystem <- 8086/9ce5<br>
PCI: 00:15.3 cmd <- 107<br>
PCI: 00:16.0 subsystem <- 8086/9cba<br>
PCI: 00:16.0 cmd <- 07<br>
PCI: 00:1c.0 bridge ctrl <- 0003<br>
PCI: 00:1c.0 subsystem <- 8086/9c94<br>
PCI: 00:1c.0 cmd <- 05<br>
PCI: 00:1f.0 subsystem <- 8086/9cc3<br>
PCI: 00:1f.0 cmd <- 107<br>
PCI: 00:1f.2 subsystem <- 8086/9c83<br>
PCI: 00:1f.2 cmd <- 107<br>
PCI: 00:1f.6 subsystem <- 8086/9ca4<br>
PCI: 00:1f.6 cmd <- 107<br>
done.<br>
BS: BS_DEV_ENABLE times (us): entry 5 run 80526 exit 4<br>
Initializing devices...<br>
Root Device init ...<br>
mainboard_init<br>
mainboard_ec_init<br>
Chrome EC: Set WAKE mask to 0x00000000<br>
Missing Chromium EC memory map.<br>
Root Device init finished in 11316 usecs<br>
CPU_CLUSTER: 0 init ...<br>
MTRR: Physical address space:<br>
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6<br>
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0<br>
0x00000000000c0000 - 0x000000007d800000 size 0x7d740000 type 6<br>
0x000000007d800000 - 0x00000000c0000000 size 0x42800000 type 0<br>
0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1<br>
0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0<br>
0x0000000100000000 - 0x0000000280000000 size 0x180000000 type 6<br>
MTRR: Fixed MSR 0x250 0x0606060606060606<br>
MTRR: Fixed MSR 0x258 0x0606060606060606<br>
MTRR: Fixed MSR 0x259 0x0000000000000000<br>
MTRR: Fixed MSR 0x268 0x0606060606060606<br>
MTRR: Fixed MSR 0x269 0x0606060606060606<br>
MTRR: Fixed MSR 0x26a 0x0606060606060606<br>
MTRR: Fixed MSR 0x26b 0x0606060606060606<br>
MTRR: Fixed MSR 0x26c 0x0606060606060606<br>
MTRR: Fixed MSR 0x26d 0x0606060606060606<br>
MTRR: Fixed MSR 0x26e 0x0606060606060606<br>
MTRR: Fixed MSR 0x26f 0x0606060606060606<br>
call enable_fixed_mtrr()<br>
CPU physical address size: 39 bits<br>
MTRR: default type WB/UC MTRR counts: 6/6.<br>
MTRR: UC selected as default type.<br>
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6<br>
MTRR: 1 base 0x000000007d800000 mask 0x0000007fff800000 type 0<br>
MTRR: 2 base 0x000000007e000000 mask 0x0000007ffe000000 type 0<br>
MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1<br>
MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6<br>
MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6<br>
<br>
MTRR check<br>
Fixed MTRRs : Enabled<br>
Variable MTRRs: Enabled<br>
<br>
Initializing VR config.<br>
PCODE: 24MHz BLCK calibration response: 0<br>
PCODE: 24MHz BLCK calibration value: 0x850609d3<br>
PCH Power: PCODE Levels 0x3f245102 0x0058f38a<br>
CPU has 2 cores, 4 threads enabled.<br>
Setting up SMI for CPU<br>
Will perform SMM setup.<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'cpu_microcode_blob.bin'<br>
CBFS: Found @ offset af40 size 11440<br>
microcode: sig=0x306d4 pf=0x40 revision=0x1f<br>
CPU: Intel(R) Core(TM) i7-5650U CPU @ 2.20GHz.<br>
Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130<br>
Processing 16 relocs. Offset value of 0x00030000<br>
Attempting to start 3 APs<br>
Waiting for 10ms after sending INIT.<br>
Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.<br>
AP: slot 3 apic_id 3.<br>
AP: slot 2 apic_id 2.<br>
done.<br>
Waiting for 2nd SIPI to complete...done.<br>
Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8<br>
Processing 12 relocs. Offset value of 0x00038000<br>
SMM Module: stub loaded at 00038000. Will call 7cfaee31(00000000)<br>
Installing SMM handler to 0x7d000000<br>
Loading module at 7d010000 with entry 7d010070. filesize: 0xe48 memsize: 0x4e68<br>
Processing 35 relocs. Offset value of 0x7d010000<br>
Loading module at 7d008000 with entry 7d008000. filesize: 0x1a8 memsize: 0x1a8<br>
Processing 12 relocs. Offset value of 0x7d008000<br>
SMM Module: placing jmp sequence at 7d007c00 rel16 0x03fd<br>
SMM Module: placing jmp sequence at 7d007800 rel16 0x07fd<br>
SMM Module: placing jmp sequence at 7d007400 rel16 0x0bfd<br>
SMM Module: stub loaded at 7d008000. Will call 7d010070(00000000)<br>
Initializing Southbridge SMI... ... pmbase = 0x1000<br>
<br>
SMI_STS: TCO PM1<br>
PM1_STS: TMROF<br>
New SMBASE 0x7d000000<br>
In relocation handler: CPU 0<br>
New SMBASE=0x7d000000 IEDBASE=0x7d400000<br>
Writing SMRR. base = 0x7d000006, mask=0xff800800<br>
Relocation complete.<br>
New SMBASE 0x7cfffc00<br>
In relocation handler: CPU 1<br>
New SMBASE=0x7cfffc00 IEDBASE=0x7d400000<br>
Writing SMRR. base = 0x7d000006, mask=0xff800800<br>
Relocation complete.<br>
New SMBASE 0x7cfff400<br>
In relocation handler: CPU 3<br>
New SMBASE=0x7cfff400 IEDBASE=0x7d400000<br>
Writing SMRR. base = 0x7d000006, mask=0xff800800<br>
Relocation complete.<br>
New SMBASE 0x7cfff800<br>
In relocation handler: CPU 2<br>
New SMBASE=0x7cfff800 IEDBASE=0x7d400000<br>
Writing SMRR. base = 0x7d000006, mask=0xff800800<br>
Relocation complete.<br>
Initializing CPU #0<br>
CPU: vendor Intel device 306d4<br>
CPU: family 06, model 3d, stepping 04<br>
Setting up local APIC... apic_id: 0x00 done.<br>
VMX status: disabled, unlocked<br>
cpu: energy policy set to 6<br>
Turbo is available but hidden<br>
Turbo has been enabled<br>
CPU #0 initialized<br>
Initializing CPU #1<br>
Initializing CPU #2<br>
Initializing CPU #3<br>
CPU: vendor Intel device 306d4<br>
CPU: family 06, model 3d, stepping 04<br>
CPU: vendor Intel device 306d4<br>
CPU: family 06, model 3d, stepping 04<br>
Setting up local APIC...Setting up local APIC... apic_id: 0x02 done.<br>
apic_id: 0x03 done.<br>
VMX status: disabled, unlocked<br>
VMX status: disabled, unlocked<br>
cpu: energy policy set to 6<br>
cpu: energy policy set to 6<br>
CPU #2 initialized<br>
CPU #3 initialized<br>
CPU: vendor Intel device 306d4<br>
CPU: family 06, model 3d, stepping 04<br>
Setting up local APIC... apic_id: 0x01 done.<br>
VMX status: disabled, unlocked<br>
cpu: energy policy set to 6<br>
CPU #1 initialized<br>
cpu: frequency set to 3200<br>
Enabling SMIs.<br>
Locking SMM.<br>
CPU_CLUSTER: 0 init finished in 443935 usecs<br>
PCI: 00:00.0 init ...<br>
Set BIOS_RESET_CPL<br>
CPU TDP: 15 Watts<br>
PCI: 00:00.0 init finished in 6390 usecs<br>
PCI: 00:02.0 init ...<br>
<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'pci8086,1626.rom'<br>
CBFS: 'pci8086,1626.rom' not found.<br>
CBFS: 'Master Header Locator' located CBFS at [300100:3fffc0)<br>
CBFS: Locating 'pci8086,0406.rom'<br>
CBFS: Found @ offset 47900 size 10000<br>
In CBFS, ROM address for PCI: 00:02.0 = fff47a48<br>
PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040<br>
PCI ROM image, vendor ID 8086, device ID 0406,<br>
PCI ROM image, Class Code 030000, Code Type 00<br>
Copying VGA ROM Image from fff47a48 to 0xc0000, 0x10000 bytes<br>
pci_dev_init, 2<br>
Real mode stub @00000600: 867 bytes<br>
Calling Option ROM...<br>
intel_vga_int15_handler: AX=5f35 BX=c000 CX=0002 DX=03da<br>
... Option ROM returned.<br>
VGA Option ROM was run<br>
<br>
PCI: 00:02.0 init finished in 1309735 usecs<br>
PCI: 00:03.0 init ...<br>
Mini-HD: base = d1118000<br>
HDA: Initializing codec #0<br>
HDA: codec viddid: 80862808<br>
HDA: No verb table entry found<br>
PCI: 00:03.0 init finished in 14983 usecs<br>
PCI: 00:13.0 init ...<br>
ADSP: Enable ACPI Mode IRQ3<br>
PCI: 00:13.0 init finished in 4616 usecs<br>
PCI: 00:14.0 init ...<br>
PCI: 00:14.0 init finished in 1999 usecs<br>
PCI: 00:15.0 init ...<br>
Initializing Serial IO device<br>
PCI: 00:15.0 init finished in 4769 usecs<br>
PCI: 00:15.1 init ...<br>
Initializing Serial IO device<br>
PCI: 00:15.1 init finished in 4718 usecs<br>
PCI: 00:15.2 init ...<br>
Initializing Serial IO device<br>
PCI: 00:15.2 init finished in 4717 usecs<br>
PCI: 00:15.3 init ...<br>
Initializing Serial IO device<br>
PCI: 00:15.3 init finished in 4716 usecs<br>
PCI: 00:16.0 init ...<br>
ME: FW Partition Table : OK<br>
ME: Bringup Loader Failure : NO<br>
ME: Firmware Init Complete : NO<br>
ME: Manufacturing Mode : YES<br>
ME: Boot Options Present : NO<br>
ME: Update In Progress : NO<br>
ME: Current Working State : Initializing<br>
ME: Current Operation State : Bring up<br>
ME: Current Operation Mode : Security Override via Jumper<br>
ME: Error Code : Debug Failure<br>
ME: Progress Phase : BUP Phase<br>
ME: Power Management Event : Pseudo-global reset<br>
ME: Progress Phase State : 0x7b<br>
intel_me_path: mbp is not ready!<br>
ME: BIOS path: Error<br>
ME: MBP not ready<br>
PCI: 00:16.0 init finished in 53821 usecs<br>
PCI: 00:1c.0 init ...<br>
Initializing PCH PCIe bridge.<br>
PCI: 00:1c.0 init finished in 4689 usecs<br>
PCI: 00:1f.0 init ...<br>
rtc_failed = 0x4<br>
RTC Init<br>
RTC: Clear requested zeroing cmos<br>
IOAPIC: Initializing IOAPIC at 0xfec00000<br>
IOAPIC: Bootstrap Processor Local APIC = 0x00<br>
IOAPIC: ID = 0x02<br>
IOAPIC: Dumping registers<br>
reg 0x0000: 0x02000000<br>
reg 0x0001: 0x00170020<br>
reg 0x0002: 0x00000000<br>
Set power off after power failure.</div>
<br>
</div>
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</div>
<br>
<p></p>
<br>
<br>
<div style="color:rgb(0,0,0)">
<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Matt DeVillier <matt.devillier@gmail.com><br>
<b>Sent:</b> Monday, July 31, 2017 7:06 PM<br>
<b>To:</b> Zheng Bao<br>
<b>Cc:</b> Nico Huber; coreboot@coreboot.org; stefan.reinauer@coreboot.org<br>
<b>Subject:</b> Re: [coreboot] Broadwell-U hangs at VGA init</font>
<div> </div>
</div>
<div>
<div dir="ltr">you want to extract the refcode blob as so:<br>
<br>
cbfstool shellball.rom extract -r BOOT_STUB -n fallback/refcode -f refcode.elf -m x86<br>
<div><br>
</div>
<div>then add it into your build</div>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Mon, Jul 31, 2017 at 8:43 AM, Zheng Bao <span dir="ltr">
<<a href="mailto:fishbaoz@hotmail.com" target="_blank">fishbaoz@hotmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex; border-left:1px #ccc solid; padding-left:1ex">
<div dir="ltr">
<div id="m_1773105490435710431divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Arial,Helvetica,sans-serif">
<p>Thanks. That really helps.</p>
<p><br>
</p>
<p>About the <font size="2"><span style="font-size:10pt">REFCODE_BLOB</span></font>, the BLOB I extracted from ball-rom is BIN, instead of ELF which is required by current CBFS and rmodule in source. (And revision in ball-rom is not in main tree of repository.)<br>
</p>
<br>
<p>Any idea to get <font size="2"><span style="font-size:10pt">REFCODE_BLOB</span></font>?</p>
<p><br>
</p>
<p>Thanks.</p>
<p><br>
</p>
<p>Zheng<br>
</p>
<div style="color:rgb(0,0,0)">
<div>
<hr style="display:inline-block; width:98%">
<div id="m_1773105490435710431x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Nico Huber <<a href="mailto:nico.huber@secunet.com" target="_blank">nico.huber@secunet.com</a>><br>
<b>Sent:</b> Monday, July 31, 2017 10:52 AM<br>
<b>To:</b> Zheng Bao; <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>; Matt DeVillier;
<a href="mailto:stefan.reinauer@coreboot.org" target="_blank">stefan.reinauer@coreboot.org</a><br>
<b>Subject:</b> Re: [coreboot] Broadwell-U hangs at VGA init</font>
<div> </div>
</div>
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<div>
<div class="h5"><font size="2"><span style="font-size:10pt">
<div class="m_1773105490435710431PlainText">Hi Zheng,<br>
<br>
On 30.07.2017 16:13, Zheng Bao wrote:<br>
> I have got the mrc.bin and mem init has got passed.<br>
> Now the new problem is that it hangs at VGA init.<br>
> <br>
> static void igd_setup_panel(struct device *dev)<br>
> {<br>
> config_t *conf = dev->chip_info;<br>
> u32 reg32;<br>
> <br>
> /* Setup Digital Port Hotplug */<br>
> reg32 = gtt_read(PCH_PORT_HOTPLUG); <------- It hangs here.<br>
> if (!reg32) {<br>
> reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;<br>
> reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;<br>
> reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;<br>
> gtt_write(PCH_PORT_HOTPLUG, reg32);<br>
> }<br>
> <br>
> It turns out as soon as i access VGA bar0+0xc4030, it hangs.<br>
> while accessing bar0 + 0xa00a is ok.<br>
<br>
sounds like the PCH part of the display engine isn't operational (pro-<br>
bably not all, but most register offsets with bit 19 set reside in the<br>
PCH). There are few steps to enable it [1], yet the Broadwell port seems<br>
to rely on the blob to do it. The datasheet [2] suggests that the same<br>
settings should be done for Broadwell too, but I can't find it in the<br>
source. So that leads to the conclusion: You forgot to add the second<br>
blob (HAVE_REFCODE_BLOB, it's BS, it's annoying, but you need it).<br>
<br>
That publicly documented settings move from the open source code into<br>
blobs is a very bad sign, IMO. Now, anybody tell me again, that things<br>
with Intel are getting better and they might become more open (the sta-<br>
tistics seem to say the opposite: the blobs get bigger, weirder, take<br>
over more responsibilities _and_ do a lot of stuff we already had open<br>
source for earlier platforms).<br>
<br>
Nico<br>
<br>
[1] src/southbridge/intel/<wbr>lynxpoint/lpc.c:725<br>
[2] Intel Document Number: 330837<br>
</div>
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