<div dir="ltr">Hi, <br>
Thanks for the steps, I appreciate it. If I understand correctly I would be able to use this tool when Linux boots with coreboot.<br>
But the issue I have is, coreboot not coming up on the board rather I am not sure if it's coming up because I don't see anything on the screen and there is no serial port on the board(except the cpu fan running). Any insight/suggestions would be appreciated.</div><span>
</span><br><div class="gmail_quote"><div dir="ltr">On Tue, Apr 25, 2017, 10:53 PM Haleigh Novak <<a href="mailto:haleigh@edt.com" target="_blank">haleigh@edt.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Hello ,<br>
<br>
cbmem is a utility located in .../coreboot/util/cbmem.<br>
You will have to fully boot into linux to use this coreboot utility.<br>
You will also have to have the ability to re-flash your coreboot rom because<br>
there are some coreboot configuration changes.<br>
<br>
What I do to install and run is as follows:<br>
<br>
(Install)<br>
1) Mount your coreboot source folder to the running system you wish to<br>
use the cbmem utility on.<br>
2) Navigate to .../coreboot/util/cbmem folder.<br>
3) Type "$ make install" into your terminal.<br>
(cbmem should install on the system in the /usr/local/sbin folder.)<br>
<br>
(Use - coreboot setup; requires a re-flash of your coreboot rom.)<br>
1) In your coreboot folder run "$ make menuconfig".<br>
2) Under the console tab: (explanations are above the configuration line<br>
and //[commented].)<br>
//[Enable console output (below) by highlighting and typing 'y'.]<br>
[*] Send console output to a CBMEM buffer<br>
//[I had to increase the size for debugging (below).]<br>
(0x40000) Room allocated for console output in CBMEM<br>
//[Set the default level to SPEW (everything) if it is not set like that already.]<br>
Default console log level (8: SPEW) ---><br>
With those settings you should be able to successfully run the cbmem utility<br>
and get all the output you could need. If you wish to add debug statements<br>
anywhere you can do that as well, though it will require a re-flash of your<br>
coreboot rom again. All you need to do is add the following replacing <...><br>
as desired anywhere in the coreboot code and it will be displayed in the<br>
cbmem output.<br>
"printk(BIOS_INFO, "<statement> <variable print> <statement>.\n", <variable>);"<br>
<br>
(Use - Run cbmem utility, you will need to be root for this.)<br>
1) "cbmem -c" -or- "/usr/local/sbin/cbmem -c"<br>
<br>
HN<br>
<br>
<br>
From: coreboot <<a href="mailto:coreboot-bounces@coreboot.org" target="_blank">coreboot-bounces@coreboot.org</a>> on behalf of Nagabhushan Shastry <<a href="mailto:bhushansastry@gmail.com" target="_blank">bhushansastry@gmail.com</a>><br>
Sent: Tuesday, April 25, 2017 9:41 AM<br>
To: ron minnich<br>
Cc: Idwer Vollering; coreboot<br>
Subject: Re: [coreboot] Booting issue --AMD Olive Hill plus mainboard<br>
<br>
<br>
<br>
I included the microcode updates but no luck.<br>
<br>
<br>
<br>
The PCI IDs seem to be correct for Mullins [Radeon R3 Graphics] (<a href="http://pci-ids.ucw.cz/read/PC/1002" rel="noreferrer" target="_blank">http://pci-ids.ucw.cz/read/PC/1002</a>).<br>
There is no serial port in the Olive Hill Plus board. What are my options?<br>
Also how do i use this tool in util/cbmem/ ? I am using the default SeaBios as the payload.<br>
<br>
<br>
<br>
<br>
On Tue, Apr 25, 2017 at 3:15 AM, ron minnich <<a href="mailto:rminnich@gmail.com" target="_blank">rminnich@gmail.com</a>> wrote:<br>
<br>
unless you're dead certain you don't need them, include microcode updates. <br>
did you hook up a serial port?<br>
<br>
<br>
On Mon, Apr 24, 2017 at 2:44 PM Idwer Vollering <<a href="mailto:vidwer@gmail.com" target="_blank">vidwer@gmail.com</a>> wrote:<br>
2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <<a href="mailto:bhushansastry@gmail.com" target="_blank">bhushansastry@gmail.com</a>>:<br>
> Hi,<br>
><br>
> I am trying to bring up the AMD G series Olive hill plus mainboard with<br>
> coreboot.<br>
><br>
> These are the options i have enabled in make menuconfig but I am not able<br>
> to see anything on the screen when i power on the board.<br>
> Could someone please let me know if I am missing something.<br>
><br>
> • General / Use CMOS for configuration values = enable (CMOS defaults are<br>
> located in your boards directory src/mainboard/OEM/MODEL/cmos.default)<br>
> • General / Include the coreboot .config file into the ROM image<br>
> • General / Compress ramstage with LZMA<br>
> • Mainboard / Mainboard vendor = AMD<br>
> • Mainboard / Mainboard model = Olive Hill plus<br>
> • Mainboard / ROM chip size = 8 MB<br>
> • Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br>
> (NOTE: you probably want to enable it on some systems)<br>
> • Chipset / Enable Hudson XHCI Controller<br>
> • Chipset / Add xhci firmware<br>
> • (3rdparty/blobs/southbridge/amd/avalon/xhci.bin) XHCI firmware path and<br>
> filename<br>
> (3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin) AMD public Key<br>
> • Devices / Run VGA Option ROMs<br>
> • Devices / Add a VGA BIOS image<br>
> (3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin) VGA BIOS path and<br>
> filename<br>
> (1002,9850) VGA device PCI IDs<br>
<br>
These PCI IDs, are they correct? Is the VBIOS, which I don't know<br>
anything about, executed? You need to have a way to see console<br>
output, either using the board's serial port or - presuming the<br>
mainboard boots to linux - through the utility found in util/cbmem/<br>
<br>
> • Display / Keep VESA framebuffer = disable (disable for text-mode graphics,<br>
> enable for coreboot vesa framebuffer)<br>
> • Generic Drivers / Serial port on SuperIO<br>
> • Generic Drivers / Support Intel PCI-e WiFi adapters<br>
> • Console / Squelch AP CPUs from early console.<br>
> • Console / Serial port console output<br>
> • Console / Use onboard VGA as primary video device<br>
> • Console / Send console output to a CBMEM buffer<br>
> • Console / Send POST codes to an external device<br>
> • Console / Send POST codes to an IO port<br>
> • System tables / [*] Generate an MP table<br>
> • System tables / [*] Generate a PIRQ table<br>
> • System tables / [*] Generate SMBIOS tables<br>
> • Payload / SeaBIOS version (1.10.2) ---><br>
> • Payload / Use LZMA compression for payloads<br>
><br>
> --<br>
> coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
> <a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/mailman/listinfo/coreboot</a><br>
<br>
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<br>
</blockquote></div>