<div dir="ltr"><div>I included the microcode updates but no luck.<br></div><div><br></div><div>The PCI IDs seem to be correct for Mullins [Radeon R3 Graphics] (<a href="http://pci-ids.ucw.cz/read/PC/1002">http://pci-ids.ucw.cz/read/PC/1002</a>).</div><div><b>There is no serial port in the Olive Hill Plus board</b>. <b>What are my options</b>?</div><div>Also how do i use this tool in util/cbmem/ ? I am using the default SeaBios as the payload.</div><div><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Apr 25, 2017 at 3:15 AM, ron minnich <span dir="ltr"><<a href="mailto:rminnich@gmail.com" target="_blank">rminnich@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr"><span style="background-color:rgb(255,255,0)">unless you're dead certain you don't need them, include microcode updates. </span><div><span style="background-color:rgb(255,255,0)">did you hook up a serial port?</span></div></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Apr 24, 2017 at 2:44 PM Idwer Vollering <<a href="mailto:vidwer@gmail.com" target="_blank">vidwer@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">2017-04-24 21:08 GMT+02:00 Nagabhushan Shastry <<a href="mailto:bhushansastry@gmail.com" target="_blank">bhushansastry@gmail.com</a>>:<br>
> Hi,<br>
><br>
> I am trying to bring up the AMD G series Olive hill plus mainboard with<br>
> coreboot.<br>
><br>
> These are the options i have enabled in make menuconfig but I am not able<br>
> to see anything on the screen when i power on the board.<br>
> Could someone please let me know if I am missing something.<br>
><br>
> • General / Use CMOS for configuration values = enable (CMOS defaults are<br>
> located in your boards directory src/mainboard/OEM/MODEL/cmos.<wbr>default)<br>
> • General / Include the coreboot .config file into the ROM image<br>
> • General / Compress ramstage with LZMA<br>
> • Mainboard / Mainboard vendor = AMD<br>
> • Mainboard / Mainboard model = Olive Hill plus<br>
> • Mainboard / ROM chip size = 8 MB<br>
> • Chipset / Include CPU microcode in CBFS = Do not include microcode updates<br>
> (NOTE: you probably want to enable it on some systems)<br>
> • Chipset / Enable Hudson XHCI Controller<br>
> • Chipset / Add xhci firmware<br>
> • (3rdparty/blobs/southbridge/<wbr>amd/avalon/xhci.bin) XHCI firmware path and<br>
> filename<br>
> (3rdparty/blobs/southbridge/<wbr>amd/avalon/PSP/AmdPubKey.bin) AMD public Key<br>
> • Devices / Run VGA Option ROMs<br>
> • Devices / Add a VGA BIOS image<br>
> (3rdparty/blobs/northbridge/<wbr>amd/00730F01/VBIOS.bin) VGA BIOS path and<br>
> filename<br>
> (1002,9850) VGA device PCI IDs<br>
<br><span style="background-color:rgb(255,255,0)">
These PCI IDs, are they correct? Is the VBIOS, which I don't know<br>
anything about, executed? You need to have a way to see console<br>
output, either using the board's serial port or - presuming the<br>
mainboard boots to linux - through the utility found in util/cbmem/</span><br>
<br>
> • Display / Keep VESA framebuffer = disable (disable for text-mode graphics,<br>
> enable for coreboot vesa framebuffer)<br>
> • Generic Drivers / Serial port on SuperIO<br>
> • Generic Drivers / Support Intel PCI-e WiFi adapters<br>
> • Console / Squelch AP CPUs from early console.<br>
> • Console / Serial port console output<br>
> • Console / Use onboard VGA as primary video device<br>
> • Console / Send console output to a CBMEM buffer<br>
> • Console / Send POST codes to an external device<br>
> • Console / Send POST codes to an IO port<br>
> • System tables / [*] Generate an MP table<br>
> • System tables / [*] Generate a PIRQ table<br>
> • System tables / [*] Generate SMBIOS tables<br>
> • Payload / SeaBIOS version (1.10.2) ---><br>
> • Payload / Use LZMA compression for payloads<br>
><br>
> --<br>
> coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
> <a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/<wbr>mailman/listinfo/coreboot</a><span class="gmail-HOEnZb"><font color="#888888"><br>
<br>
--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br>
<a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/<wbr>mailman/listinfo/coreboot</a></font></span></blockquote></div>
<br>--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/<wbr>mailman/listinfo/coreboot</a><br></blockquote></div><br></div></div></div>