[coreboot] New patch to review for coreboot: 435578d Unify setting i82801e LPC
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Feb 27 21:15:20 CET 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2545
-gerrit
commit 435578deea8cd4137a6696bf1abef8c1bb853594
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting i82801e LPC
Make it more similar to i82801d LPC init.
Change-Id: I7b32747ee8012c220c8628994d749999c144b716
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/intel/i82801ex/lpc.c | 65 +++++++++++++++++++++++++-----------
1 file changed, 45 insertions(+), 20 deletions(-)
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index d0d5978..fb1586e 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -21,6 +21,45 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801ex_enable_acpi(struct device *dev)
+{
+ u8 gpio_cntl;
+
+ /* Enable ACPI I/O range decode and ACPI power management. */
+ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+ /* Enable the GPIO bar */
+ gpio_cntl = pci_read_config8(dev, GPIO_CNTL);
+ gpio_cntl |= GPIO_EN;
+ pci_write_config8(dev, GPIO_CNTL, gpio_cntl);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC configuration registers
+ */
+static void i82801ex_general_cntl(struct device *dev)
+{
+ u32 reg32;
+
+ reg32 = pci_read_config32(dev, GEN_CNTL);
+ reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
+ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
+ pci_write_config32(dev, GEN_CNTL, reg32);
+ printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32);
+
+ reg32 = pci_read_config32(dev, GEN_STS);
+ reg32 |= (1<<1);
+ pci_write_config32(dev, GEN_STS, reg32);
+
+}
+
#define SERIRQ_CNTL 0x64
static void i82801ex_enable_serial_irqs(device_t dev)
{
@@ -237,16 +276,11 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
uint8_t byte;
- uint32_t value;
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- /* IO APIC initialization */
- value = pci_read_config32(dev, 0xd0);
- value |= (1 << 8)|(1<<7)|(1<<1);
- pci_write_config32(dev, 0xd0, value);
- value = pci_read_config32(dev, 0xd4);
- value |= (1<<1);
- pci_write_config32(dev, 0xd4, value);
+ i82801ex_general_cntl(dev);
+
+ /* IO APIC initialization. */
setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
@@ -319,20 +353,11 @@ static void i82801ex_lpc_read_resources(device_t dev)
static void i82801ex_lpc_enable_resources(device_t dev)
{
- uint8_t acpi_cntl, gpio_cntl;
-
- /* Enable the normal pci resources */
+ /* Enable the normal PCI resources. */
pci_dev_enable_resources(dev);
- /* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
- acpi_cntl |= (1 << 4);
- pci_write_config8(dev, 0x44, acpi_cntl);
-
- /* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x5c);
- gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x5c, gpio_cntl);
+ /* Enable ACPI and GPIO BARs. */
+ i82801ex_enable_acpi(dev);
}
static struct pci_operations lops_pci = {
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