[coreboot] New patch to review for coreboot: 3d3abb2 Remove old AMD fam10 fixme comment
Marc Jones (marcj303@gmail.com)
gerrit at coreboot.org
Wed Feb 22 01:55:49 CET 2012
Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/672
-gerrit
commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b
Author: Marc Jones <marc.jones at se-eng.com>
Date: Tue Feb 21 17:53:13 2012 -0700
Remove old AMD fam10 fixme comment
The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.
Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/mainboard/amd/mahogany_fam10/romstage.c | 1 -
.../amd/serengeti_cheetah_fam10/romstage.c | 1 -
src/mainboard/amd/tilapia_fam10/romstage.c | 1 -
src/mainboard/asus/m4a78-em/romstage.c | 1 -
src/mainboard/asus/m4a785-m/romstage.c | 1 -
src/mainboard/gigabyte/ma785gmt/romstage.c | 1 -
src/mainboard/gigabyte/ma78gm/romstage.c | 1 -
src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 -
src/mainboard/jetway/pa78vm5/romstage.c | 1 -
src/mainboard/msi/ms9652_fam10/romstage.c | 1 -
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 -
src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 -
src/mainboard/tyan/s2912_fam10/romstage.c | 1 -
13 files changed, 0 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 04a9e45..dce9baa 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index b41230d..29b00b2 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -331,7 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 52cab42..f316395 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 76449cb..a96592d 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 76449cb..a96592d 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 4572169..68f3dcc 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index bd81e67..6c25a9e 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 54b364a..f51b3ec 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -222,7 +222,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index b2d4ecb..ba3b208 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -227,7 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index fc8120b..0bf6d11 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -241,7 +241,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index c9fb928..4e243c2 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -240,7 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
- // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 870125d..d9d5218 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -290,7 +290,6 @@ post_code(0x40);
raminit_amdmct(sysinfo);
post_code(0x41);
-// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 97c03b5..df571a0 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -238,7 +238,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
raminit_amdmct(sysinfo);
post_code(0x41);
- printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
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