<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30383">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK<br><br>This puts the cache as ram in the bootblock.<br>Before setting up cache as ram the microcode updates are applied.<br><br>This removes the possibility for a normal/fallback setup although<br>implementing this should be quite easy.<br><br>Setting up LPC in the bootblock to output console on SuperIOs is not<br>done in this patch.<br><br>Untested<br><br>Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/soc/intel/broadwell/Kconfig<br>M src/soc/intel/broadwell/Makefile.inc<br>M src/soc/intel/broadwell/bootblock/cpu.c<br>M src/soc/intel/broadwell/bootblock/pch.c<br>M src/soc/intel/broadwell/bootblock/systemagent.c<br>D src/soc/intel/broadwell/bootblock/timestamp.inc<br>M src/soc/intel/broadwell/romstage/Makefile.inc<br>M src/soc/intel/broadwell/romstage/romstage.c<br>8 files changed, 36 insertions(+), 105 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig</span><br><span>index e6cbd95..8f77930 100644</span><br><span>--- a/src/soc/intel/broadwell/Kconfig</span><br><span>+++ b/src/soc/intel/broadwell/Kconfig</span><br><span>@@ -42,6 +42,8 @@</span><br><span> select INTEL_GMA_ACPI</span><br><span> select POSTCAR_STAGE</span><br><span> select POSTCAR_CONSOLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select C_ENVIRONMENT_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOOTBLOCK_CONSOLE</span><br><span> </span><br><span> config PCIEXP_ASPM</span><br><span> bool</span><br><span>@@ -66,18 +68,6 @@</span><br><span> config VBOOT</span><br><span> select VBOOT_STARTS_IN_ROMSTAGE</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config BOOTBLOCK_CPU_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "soc/intel/broadwell/bootblock/cpu.c"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOOTBLOCK_NORTHBRIDGE_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "soc/intel/broadwell/bootblock/systemagent.c"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOOTBLOCK_SOUTHBRIDGE_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "soc/intel/broadwell/bootblock/pch.c"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config MMCONF_BASE_ADDRESS</span><br><span> hex</span><br><span> default 0xf0000000</span><br><span>@@ -120,6 +110,13 @@</span><br><span> help</span><br><span> The amount of cache-as-ram region required by the reference code.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ The amount of anticipated stack usage in CAR by bootblock and</span><br><span style="color: hsl(120, 100%, 40%);">+ other stages.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config HAVE_MRC</span><br><span> bool "Add a Memory Reference Code binary"</span><br><span> help</span><br><span>diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc</span><br><span>index caf963c..70d8e39 100644</span><br><span>--- a/src/soc/intel/broadwell/Makefile.inc</span><br><span>+++ b/src/soc/intel/broadwell/Makefile.inc</span><br><span>@@ -9,6 +9,13 @@</span><br><span> subdirs-y += ../../../cpu/intel/turbo</span><br><span> subdirs-y += ../../../cpu/intel/common</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/cpu.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/pch.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += bootblock/systemagent.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../../../cpu/intel/car/bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ramstage-y += acpi.c</span><br><span> ramstage-y += adsp.c</span><br><span> ramstage-y += chip.c</span><br><span>diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c</span><br><span>index 7508bc2..52be618 100644</span><br><span>--- a/src/soc/intel/broadwell/bootblock/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/bootblock/cpu.c</span><br><span>@@ -19,48 +19,10 @@</span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <arch/io.h></span><br><span> #include <halt.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/intel/microcode/microcode.c></span><br><span> #include <soc/rcba.h></span><br><span> #include <soc/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int type)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t basem, maskm;</span><br><span style="color: hsl(0, 100%, 40%);">- basem.lo = base | type;</span><br><span style="color: hsl(0, 100%, 40%);">- basem.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_PHYS_BASE(reg), basem);</span><br><span style="color: hsl(0, 100%, 40%);">- maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;</span><br><span style="color: hsl(0, 100%, 40%);">- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_PHYS_MASK(reg), maskm);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_rom_caching(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- disable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- /* Why only top 4MiB ? */</span><br><span style="color: hsl(0, 100%, 40%);">- set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(0, 100%, 40%);">- enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x00000800;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MTRR_DEF_TYPE_MSR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_mdelay(int ms)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 target = ms * 24 * 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t current;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t start = rdmsr(MSR_COUNTER_24_MHZ);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- current = rdmsr(MSR_COUNTER_24_MHZ);</span><br><span style="color: hsl(0, 100%, 40%);">- } while ((current.lo - start.lo) < target);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span> </span><br><span> static void set_flex_ratio_to_tdp_nominal(void)</span><br><span> {</span><br><span>@@ -103,7 +65,7 @@</span><br><span> RCBA32_OR(SOFT_RESET_CTRL, 1);</span><br><span> </span><br><span> /* Delay before reset to avoid potential TPM lockout */</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_mdelay(30);</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(30);</span><br><span> </span><br><span> /* Issue warm reset, will be "CPU only" due to soft reset data */</span><br><span> outb(0x0, 0xcf9);</span><br><span>@@ -126,11 +88,9 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_cpu_init(void)</span><br><span> {</span><br><span> /* Set flex ratio and reset if needed */</span><br><span> set_flex_ratio_to_tdp_nominal();</span><br><span> check_for_clean_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_rom_caching();</span><br><span style="color: hsl(0, 100%, 40%);">- intel_update_microcode_from_cbfs();</span><br><span> }</span><br><span>diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>index 2643801..9cd199f 100644</span><br><span>--- a/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/broadwell/bootblock/pch.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/rcba.h></span><br><span> #include <soc/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span> </span><br><span> /*</span><br><span> * Enable Prefetching and Caching.</span><br><span>@@ -66,7 +67,7 @@</span><br><span> SPIBAR8(SPIBAR_SSFC + 2) = ssfc;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_southbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_southbridge_init(void)</span><br><span> {</span><br><span> map_rcba();</span><br><span> enable_spi_prefetch();</span><br><span>diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c</span><br><span>index 1a09f8e..61fc8c2 100644</span><br><span>--- a/src/soc/intel/broadwell/bootblock/systemagent.c</span><br><span>+++ b/src/soc/intel/broadwell/bootblock/systemagent.c</span><br><span>@@ -16,8 +16,9 @@</span><br><span> #include <arch/io.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/car/bootblock.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void bootblock_northbridge_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_early_northbridge_init(void)</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/bootblock/timestamp.inc b/src/soc/intel/broadwell/bootblock/timestamp.inc</span><br><span>deleted file mode 100644</span><br><span>index 3115c22..0000000</span><br><span>--- a/src/soc/intel/broadwell/bootblock/timestamp.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,33 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Store the initial timestamp for booting in mmx registers. This works</span><br><span style="color: hsl(0, 100%, 40%);">- * because the bootblock isn't being compiled with MMX support so mm0 and</span><br><span style="color: hsl(0, 100%, 40%);">- * mm1 will be preserved into romstage.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .code32</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.global stash_timestamp</span><br><span style="color: hsl(0, 100%, 40%);">-stash_timestamp:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the BIST value */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- finit</span><br><span style="color: hsl(0, 100%, 40%);">- rdtsc</span><br><span style="color: hsl(0, 100%, 40%);">- movd %eax, %mm0</span><br><span style="color: hsl(0, 100%, 40%);">- movd %edx, %mm1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore the BIST value to %eax */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebp, %eax</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc</span><br><span>index 2d562d9..60c8446 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/Makefile.inc</span><br><span>+++ b/src/soc/intel/broadwell/romstage/Makefile.inc</span><br><span>@@ -1,5 +1,3 @@</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> romstage-y += cpu.c</span><br><span> romstage-y += pch.c</span><br><span> romstage-y += power_state.c</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>index afc8216..8d75f50 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>@@ -63,19 +63,24 @@</span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Entry from cache-as-ram.inc. */</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void *romstage_main(unsigned long bist,</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t tsc_low, uint32_t tsc_hi)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int get_bist_result(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int result;</span><br><span style="color: hsl(120, 100%, 40%);">+ asm ("movd %%mm0, %0;"</span><br><span style="color: hsl(120, 100%, 40%);">+ : "=r" (result));</span><br><span style="color: hsl(120, 100%, 40%);">+ return result;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span> struct romstage_params rp = {</span><br><span style="color: hsl(0, 100%, 40%);">- .bist = bist,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bist = get_bist_result(),</span><br><span> .pei_data = NULL,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30);</span><br><span style="color: hsl(120, 100%, 40%);">+ console_init();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save initial timestamp from bootblock. */</span><br><span style="color: hsl(0, 100%, 40%);">- timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30);</span><br><span> </span><br><span> /* Save romstage begin */</span><br><span> timestamp_add_now(TS_START_ROMSTAGE);</span><br><span>@@ -90,9 +95,6 @@</span><br><span> on IT8772 */</span><br><span> mainboard_pre_console_init();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Start console drivers */</span><br><span style="color: hsl(0, 100%, 40%);">- console_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Get power state */</span><br><span> rp.power_state = fill_power_state();</span><br><span> </span><br><span>@@ -106,8 +108,6 @@</span><br><span> mainboard_romstage_entry(&rp);</span><br><span> </span><br><span> platform_enter_postcar();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span> }</span><br><span> </span><br><span> /* Entry from the mainboard. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30383">change 30383</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30383"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 </div>
<div style="display:none"> Gerrit-Change-Number: 30383 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>