<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30384">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/broadwell: Add an option for where verstage starts<br><br>Previously broadwell used a romcc bootblock and starting verstage in<br>romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also<br>possible to have a separate verstage.<br><br>This selects using a separate verstage by default but still keeps the<br>option around to use verstage in romstage.<br><br>Also make sure mrc.bin is only added to the COREBOOT fmap region as it<br>requires to be run at a specific offset. This means that coreboot will<br>have to jump from a RW region to the RO region for that binary and<br>back to that RW region after that binary is done initializing the<br>memory.<br><br>Change-Id: I900233cadb3c76da329fb98f93917570e633365f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/soc/intel/broadwell/Kconfig<br>M src/soc/intel/broadwell/romstage/raminit.c<br>2 files changed, 30 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig</span><br><span>index 8f77930..44254b4 100644</span><br><span>--- a/src/soc/intel/broadwell/Kconfig</span><br><span>+++ b/src/soc/intel/broadwell/Kconfig</span><br><span>@@ -65,8 +65,24 @@</span><br><span> bool</span><br><span> default y</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BROADWELL_VBOOT_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Start verstage in bootblock"</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Broadwell can either start verstage in a separate stage</span><br><span style="color: hsl(120, 100%, 40%);">+ right after the bootblock has run or it can start it</span><br><span style="color: hsl(120, 100%, 40%);">+ after romstage for compatibility reasons.</span><br><span style="color: hsl(120, 100%, 40%);">+ Broadwell however uses a mrc.bin to initialse memory which</span><br><span style="color: hsl(120, 100%, 40%);">+ needs to be located at a fixed offset. Therefore even with</span><br><span style="color: hsl(120, 100%, 40%);">+ a separate verstage starting after the bootblock that same</span><br><span style="color: hsl(120, 100%, 40%);">+ binary is used meaning a jump is made from RW to the RO region</span><br><span style="color: hsl(120, 100%, 40%);">+ and back to the RW region after the binary is done.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config VBOOT</span><br><span style="color: hsl(0, 100%, 40%);">- select VBOOT_STARTS_IN_ROMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK</span><br><span> </span><br><span> config MMCONF_BASE_ADDRESS</span><br><span> hex</span><br><span>@@ -138,6 +154,13 @@</span><br><span> hex</span><br><span> default 0xfffa0000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+# The UEFI System Agent binary needs to be at a fixed offset in the flash</span><br><span style="color: hsl(120, 100%, 40%);">+# and can therefore only reside in the COREBOOT fmap region</span><br><span style="color: hsl(120, 100%, 40%);">+config RO_REGION_ONLY</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ default "mrc.bin"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # HAVE_MRC</span><br><span> </span><br><span> config PRE_GRAPHICS_DELAY</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c</span><br><span>index c4a3b2c..ba9dac1 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/raminit.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/raminit.c</span><br><span>@@ -47,6 +47,8 @@</span><br><span> struct memory_info *mem_info;</span><br><span> pei_wrapper_entry_t entry;</span><br><span> int ret;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cbfsf f;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t type = CBFS_TYPE_MRC;</span><br><span> </span><br><span> broadwell_fill_pei_data(pei_data);</span><br><span> </span><br><span>@@ -79,7 +81,10 @@</span><br><span> }</span><br><span> </span><br><span> /* Determine if mrc.bin is in the cbfs. */</span><br><span style="color: hsl(0, 100%, 40%);">- entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ die("mrc.bin not found!");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't care about leaking the mapping */</span><br><span style="color: hsl(120, 100%, 40%);">+ entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data);</span><br><span> if (entry == NULL) {</span><br><span> printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");</span><br><span> return;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30384">change 30384</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30384"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I900233cadb3c76da329fb98f93917570e633365f </div>
<div style="display:none"> Gerrit-Change-Number: 30384 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>