<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30377">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">x86/smm/smmhandler.S: Use tabs instead of white spaces<br><br>Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/x86/smm/smmhandler.S<br>1 file changed, 26 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30377/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S</span><br><span>index 0989e89..3145ef0 100644</span><br><span>--- a/src/cpu/x86/smm/smmhandler.S</span><br><span>+++ b/src/cpu/x86/smm/smmhandler.S</span><br><span>@@ -107,13 +107,13 @@</span><br><span> ud2</span><br><span> untampered_lapic:</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">- movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx</span><br><span style="color: hsl(120, 100%, 40%);">+ movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx</span><br><span> lgdtl %cs:(%bx)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- orl $0x60000001, %eax /* CD, NW, PE = 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $0x60000001, %eax /* CD, NW, PE = 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span> </span><br><span> /* Enable protected mode */</span><br><span> ljmpl $0x08, $1f</span><br><span>@@ -124,31 +124,31 @@</span><br><span> wbinvd</span><br><span> </span><br><span> /* Use flat data segment */</span><br><span style="color: hsl(0, 100%, 40%);">- movw $0x10, %ax</span><br><span style="color: hsl(0, 100%, 40%);">- movw %ax, %ds</span><br><span style="color: hsl(0, 100%, 40%);">- movw %ax, %es</span><br><span style="color: hsl(0, 100%, 40%);">- movw %ax, %ss</span><br><span style="color: hsl(0, 100%, 40%);">- movw %ax, %fs</span><br><span style="color: hsl(0, 100%, 40%);">- movw %ax, %gs</span><br><span style="color: hsl(120, 100%, 40%);">+ movw $0x10, %ax</span><br><span style="color: hsl(120, 100%, 40%);">+ movw %ax, %ds</span><br><span style="color: hsl(120, 100%, 40%);">+ movw %ax, %es</span><br><span style="color: hsl(120, 100%, 40%);">+ movw %ax, %ss</span><br><span style="color: hsl(120, 100%, 40%);">+ movw %ax, %fs</span><br><span style="color: hsl(120, 100%, 40%);">+ movw %ax, %gs</span><br><span> </span><br><span> /* Get this CPU's LAPIC ID */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl (%esi), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- shr $24, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ movl (%esi), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ shr $24, %ecx</span><br><span> </span><br><span> /* This is an ugly hack, and we should find a way to read the CPU index</span><br><span> * without relying on the LAPIC ID.</span><br><span> */</span><br><span> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)</span><br><span> /* LAPIC IDs start from 0x10; map that to the proper core index */</span><br><span style="color: hsl(0, 100%, 40%);">- subl $0x10, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ subl $0x10, %ecx</span><br><span> #endif</span><br><span> </span><br><span> /* calculate stack offset by multiplying the APIC ID</span><br><span> * by 1024 (0x400), and save that offset in ebp.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- shl $10, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ecx, %ebp</span><br><span style="color: hsl(120, 100%, 40%);">+ shl $10, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %ecx, %ebp</span><br><span> </span><br><span> /* We put the stack for each core right above</span><br><span> * its SMM entry point. Core 0 starts at 0xa8000,</span><br><span>@@ -171,13 +171,13 @@</span><br><span> movl %ebx, %esp</span><br><span> </span><br><span> /* Get SMM revision */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0xa8000 + 0x7efc, %ebx /* core 0 address */</span><br><span style="color: hsl(0, 100%, 40%);">- subl %ebp, %ebx /* subtract core X offset */</span><br><span style="color: hsl(0, 100%, 40%);">- movl (%ebx), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */</span><br><span style="color: hsl(120, 100%, 40%);">+ subl %ebp, %ebx /* subtract core X offset */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl (%ebx), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ pushl %eax</span><br><span> </span><br><span> /* Call 32bit C handler */</span><br><span style="color: hsl(0, 100%, 40%);">- call smi_handler</span><br><span style="color: hsl(120, 100%, 40%);">+ call smi_handler</span><br><span> </span><br><span> /* To return, just do rsm. It will "clean up" protected mode */</span><br><span> rsm</span><br><span>@@ -227,14 +227,14 @@</span><br><span> .code16</span><br><span> jumptable:</span><br><span> /* core 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span> .align 1024, 0x00</span><br><span> /* core 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span> .align 1024, 0x00</span><br><span> /* core 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span> .align 1024, 0x00</span><br><span> /* core 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span style="color: hsl(120, 100%, 40%);">+ ljmp $0xa000, $SMM_HANDLER_OFFSET</span><br><span> .align 1024, 0x00</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30377">change 30377</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce </div>
<div style="display:none"> Gerrit-Change-Number: 30377 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>