<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30354">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mainboard/pcengines/apu1: Enable LPC TPM<br><br>PC Engines apu1 has a 20 pin LPC header that allows connection of<br>external TPM module.<br><br>Add necessary Kconfig option and devicetree entry for TPM.<br><br>Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/mainboard/pcengines/apu1/Kconfig<br>M src/mainboard/pcengines/apu1/devicetree.cb<br>2 files changed, 32 insertions(+), 28 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30354/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig</span><br><span>index 9d42159..07aaa8c 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/Kconfig</span><br><span>+++ b/src/mainboard/pcengines/apu1/Kconfig</span><br><span>@@ -31,6 +31,7 @@</span><br><span> select BOARD_ROMSIZE_KB_2048</span><br><span> select GENERIC_SPD_BIN</span><br><span> select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span> </span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span>diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb</span><br><span>index 72e89c0..acdabd1 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/devicetree.cb</span><br><span>+++ b/src/mainboard/pcengines/apu1/devicetree.cb</span><br><span>@@ -43,35 +43,38 @@</span><br><span> device pci 14.1 off end # IDE 0x439c</span><br><span> device pci 14.2 off end # HDA 0x4383</span><br><span> device pci 14.3 on # LPC 0x439d</span><br><span style="color: hsl(0, 100%, 40%);">- chip superio/nuvoton/nct5104d</span><br><span style="color: hsl(0, 100%, 40%);">- register "irq_trigger_type" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.0 off end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.2 on</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nuvoton/nct5104d</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq_trigger_type" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.10 off</span><br><span style="color: hsl(120, 100%, 40%);">+ # UART C is conditionally turned on</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3e8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.11 off</span><br><span style="color: hsl(120, 100%, 40%);">+ # UART D is conditionally turned on</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2e8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f off end</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPIO0 and GPIO1 are conditionally turned on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.007 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.607 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.e off end</span><br><span> end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.3 on</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x2f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 3</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.10 off</span><br><span style="color: hsl(0, 100%, 40%);">- # UART C is conditionally turned on</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3e8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 4</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.11 off</span><br><span style="color: hsl(0, 100%, 40%);">- # UART D is conditionally turned on</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x2e8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 3</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.8 off end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.f off end</span><br><span style="color: hsl(0, 100%, 40%);">- # GPIO0 and GPIO1 are conditionally turned on</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.007 off end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.107 off end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.607 off end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.e off end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC TPM</span><br><span> end #LPC</span><br><span> device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1</span><br><span> device pci 14.5 off end # OHCI FS/LS USB</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30354">change 30354</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd </div>
<div style="display:none"> Gerrit-Change-Number: 30354 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>