<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30325">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
HAOUAS Elyes: Looks good to me, approved
Angel Pons: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/pcengines/alixxx: Drop boards<br><br>These boards are still using LATE_CBMEM which was agreed upon to<br>be removed after release 4.7. It is now more than 1 year later<br>and they still linger around.<br><br>The work and review to bring those boards up to date can happen on the 4.9<br>branch and then squashed and merged back into mainline when done.<br><br>Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/c/30325<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr><br>Reviewed-by: Angel Pons <th3fanbus@gmail.com><br>Reviewed-by: Nico Huber <nico.h@gmx.de><br>---<br>D src/mainboard/pcengines/alix1c/Kconfig<br>D src/mainboard/pcengines/alix1c/Kconfig.name<br>D src/mainboard/pcengines/alix1c/board_info.txt<br>D src/mainboard/pcengines/alix1c/cmos.default<br>D src/mainboard/pcengines/alix1c/cmos.layout<br>D src/mainboard/pcengines/alix1c/devicetree.cb<br>D src/mainboard/pcengines/alix1c/irq_tables.c<br>D src/mainboard/pcengines/alix1c/romstage.c<br>D src/mainboard/pcengines/alix2c/Kconfig<br>D src/mainboard/pcengines/alix2c/Kconfig.name<br>D src/mainboard/pcengines/alix2c/board_info.txt<br>D src/mainboard/pcengines/alix2d/Kconfig<br>D src/mainboard/pcengines/alix2d/Kconfig.name<br>D src/mainboard/pcengines/alix2d/board_info.txt<br>D src/mainboard/pcengines/alix2d/cmos.layout<br>D src/mainboard/pcengines/alix2d/devicetree.cb<br>D src/mainboard/pcengines/alix2d/irq_tables.c<br>D src/mainboard/pcengines/alix2d/romstage.c<br>D src/mainboard/pcengines/alix6/Kconfig<br>D src/mainboard/pcengines/alix6/Kconfig.name<br>D src/mainboard/pcengines/alix6/board_info.txt<br>21 files changed, 0 insertions(+), 843 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 556a323..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_PCENGINES_ALIX1C</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool y</span><br><span style="color: hsl(0, 100%, 40%);">- select CPU_AMD_GEODE_LX</span><br><span style="color: hsl(0, 100%, 40%);">- select NORTHBRIDGE_AMD_LX</span><br><span style="color: hsl(0, 100%, 40%);">- select SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">- select SUPERIO_WINBOND_W83627HF</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_PIRQ_TABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select PIRQ_ROUTE</span><br><span style="color: hsl(0, 100%, 40%);">- select UDELAY_TSC</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_512</span><br><span style="color: hsl(0, 100%, 40%);">- select POWER_BUTTON_DEFAULT_DISABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_OPTION_TABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(0, 100%, 40%);">- select NO_EARLY_SMBUS</span><br><span style="color: hsl(0, 100%, 40%);">- select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS</span><br><span style="color: hsl(0, 100%, 40%);">- select MISSING_BOARD_RESET</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default pcengines/alix1c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ALIX.1C"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IRQ_SLOT_COUNT</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 5</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif # BOARD_PCENGINES_ALIX1C</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/Kconfig.name b/src/mainboard/pcengines/alix1c/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index 9b2a7ef..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,2 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_PCENGINES_ALIX1C</span><br><span style="color: hsl(0, 100%, 40%);">- bool "ALIX.1C"</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/board_info.txt b/src/mainboard/pcengines/alix1c/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index f31e77c..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,9 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: alix1c</span><br><span style="color: hsl(0, 100%, 40%);">-Board URL: http://pcengines.ch/alix1c.htm</span><br><span style="color: hsl(0, 100%, 40%);">-Category: half</span><br><span style="color: hsl(0, 100%, 40%);">-ROM package: PLCC-32</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: LPC</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span style="color: hsl(0, 100%, 40%);">-Vendor cooperation score: 4</span><br><span style="color: hsl(0, 100%, 40%);">-Vendor cooperation page: PC Engines ALIX.1C Vendor Cooperation Score</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default</span><br><span>deleted file mode 100644</span><br><span>index da50263..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/cmos.default</span><br><span>+++ /dev/null</span><br><span>@@ -1,4 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-boot_option=Fallback</span><br><span style="color: hsl(0, 100%, 40%);">-ECC_memory=Disable</span><br><span style="color: hsl(0, 100%, 40%);">-power_on_after_fail=Disable</span><br><span style="color: hsl(0, 100%, 40%);">-debug_level=Debug</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/cmos.layout b/src/mainboard/pcengines/alix1c/cmos.layout</span><br><span>deleted file mode 100644</span><br><span>index b238a37..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/cmos.layout</span><br><span>+++ /dev/null</span><br><span>@@ -1,28 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-entries</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-0 384 r 0 reserved_memory</span><br><span style="color: hsl(0, 100%, 40%);">-384 1 e 4 boot_option</span><br><span style="color: hsl(0, 100%, 40%);">-388 4 h 0 reboot_counter</span><br><span style="color: hsl(0, 100%, 40%);">-#392 3 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-400 1 e 1 power_on_after_fail</span><br><span style="color: hsl(0, 100%, 40%);">-412 4 e 6 debug_level</span><br><span style="color: hsl(0, 100%, 40%);">-456 1 e 1 ECC_memory</span><br><span style="color: hsl(0, 100%, 40%);">-1008 16 h 0 check_sum</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enumerations</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ID value text</span><br><span style="color: hsl(0, 100%, 40%);">-1 0 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-1 1 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 0 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 1 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-4 0 Fallback</span><br><span style="color: hsl(0, 100%, 40%);">-4 1 Normal</span><br><span style="color: hsl(0, 100%, 40%);">-6 5 Notice</span><br><span style="color: hsl(0, 100%, 40%);">-6 6 Info</span><br><span style="color: hsl(0, 100%, 40%);">-6 7 Debug</span><br><span style="color: hsl(0, 100%, 40%);">-6 8 Spew</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-checksums</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-checksum 392 1007 1008</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb</span><br><span>deleted file mode 100644</span><br><span>index 5b4e603..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/devicetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,84 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-chip northbridge/amd/lx</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.1 on end</span><br><span style="color: hsl(0, 100%, 40%);">- chip southbridge/amd/cs5536</span><br><span style="color: hsl(0, 100%, 40%);">- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK</span><br><span style="color: hsl(0, 100%, 40%);">- # SIRQ Mode = Active(Quiet) mode. Save power....</span><br><span style="color: hsl(0, 100%, 40%);">- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK</span><br><span style="color: hsl(0, 100%, 40%);">- # How to get these? Boot linux and do this:</span><br><span style="color: hsl(0, 100%, 40%);">- # rdmsr 0x51400025</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_enable" = "0x0000105a"</span><br><span style="color: hsl(0, 100%, 40%);">- # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_polarity" = "0x0000EFA5"</span><br><span style="color: hsl(0, 100%, 40%);">- # mode is high 10 bits (determined from code)</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_mode" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- # Don't yet know how to find this.</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_gpio_int_route" = "0x0D0C0700"</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_USBP4_device" = "0" #0: host, 1:device</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_enable" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_address" = "0x3F8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_irq" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_enable" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_address" = "0x2F8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_irq" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "unwanted_vpci[0]" = "0" # End of list has a zero</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.0 on # ISA Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- chip superio/winbond/w83627hf</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.0 off # Floppy</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f0</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 6</span><br><span style="color: hsl(0, 100%, 40%);">- drq 0x74 = 2</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.1 on # Parallel Port</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x378</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 7</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.2 on # Com1</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x3f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 4</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.3 on # Com2</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x2f8</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 3</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.5 on # Keyboard</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x60</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x62 = 0x64</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 1</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x72 = 12</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.6 off # CIR</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x100</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.7 off # GAME_MIDI_GIPO1</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x220</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x62 = 0x300</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 9</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.8 on end # GPIO2</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.9 on end # GPIO3</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.a on end # ACPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pnp 2e.b on # HW Monitor</span><br><span style="color: hsl(0, 100%, 40%);">- io 0x60 = 0x290</span><br><span style="color: hsl(0, 100%, 40%);">- irq 0x70 = 5</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.1 on end # Flash controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.2 on end # IDE controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.3 on end # Audio</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.4 on end # OHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.5 on end # EHCI</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # APIC cluster is late CPU init.</span><br><span style="color: hsl(0, 100%, 40%);">- device cpu_cluster 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip cpu/amd/geode_lx</span><br><span style="color: hsl(0, 100%, 40%);">- device lapic 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-end</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c</span><br><span>deleted file mode 100644</span><br><span>index 0296244..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/irq_tables.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,103 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">-* This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-* it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">-* published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-* but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-* GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-*/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/pirq_routing.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Platform IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQA 11</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQB 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQC 11</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQD 9</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Map */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Link */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * ALIX1.C interrupt wiring.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Devices are:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The only devices that interrupt are:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * What Device IRQ PIN PIN WIRED TO</span><br><span style="color: hsl(0, 100%, 40%);">- * -------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">- * AES 00:01.2 0a 01 A A</span><br><span style="color: hsl(0, 100%, 40%);">- * 3VPCI 00:0c.0 0a 01 A A</span><br><span style="color: hsl(0, 100%, 40%);">- * eth0 00:0d.0 0b 01 A B</span><br><span style="color: hsl(0, 100%, 40%);">- * mpci 00:0e.0 0a 01 A A</span><br><span style="color: hsl(0, 100%, 40%);">- * usb 00:0f.3 0b 02 B B</span><br><span style="color: hsl(0, 100%, 40%);">- * usb 00:0f.4 0b 04 D D</span><br><span style="color: hsl(0, 100%, 40%);">- * usb 00:0f.5 0b 04 D D</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct irq_routing_table intel_irq_routing_table = {</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQ_SIGNATURE,</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQ_VERSION,</span><br><span style="color: hsl(0, 100%, 40%);">- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* Where the interrupt router lies (bus) */</span><br><span style="color: hsl(0, 100%, 40%);">- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* IRQs devoted exclusively to PCI usage */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x100B, /* Vendor */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x002B, /* Device */</span><br><span style="color: hsl(0, 100%, 40%);">- 0, /* Miniport data */</span><br><span style="color: hsl(0, 100%, 40%);">- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* Checksum */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PCI (slot 1) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* On-board ethernet */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mini PCI (slot 2) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long write_pirq_routing_table(unsigned long addr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return copy_pirq_routing_table(addr, &intel_irq_routing_table);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>deleted file mode 100644</span><br><span>index ba2541a..0000000</span><br><span>--- a/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,148 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spd.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pnp_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/bist.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/car.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/raminit.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/northbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/amd/cs5536/cs5536.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <superio/winbond/common/winbond.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <superio/winbond/w83627hf/w83627hf.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The part is a Hynix hy5du121622ctp-d43.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * HY 5D U 12 16 2 2 C <blank> T <blank> P D43</span><br><span style="color: hsl(0, 100%, 40%);">- * Hynix</span><br><span style="color: hsl(0, 100%, 40%);">- * DDR SDRAM (5D)</span><br><span style="color: hsl(0, 100%, 40%);">- * VDD 2.5 VDDQ 2.5 (U)</span><br><span style="color: hsl(0, 100%, 40%);">- * 512M 8K REFRESH (12)</span><br><span style="color: hsl(0, 100%, 40%);">- * x16 (16)</span><br><span style="color: hsl(0, 100%, 40%);">- * 4banks (2)</span><br><span style="color: hsl(0, 100%, 40%);">- * SSTL_2 (2)</span><br><span style="color: hsl(0, 100%, 40%);">- * 4th GEN die (C)</span><br><span style="color: hsl(0, 100%, 40%);">- * Normal Power Consumption (<blank>)</span><br><span style="color: hsl(0, 100%, 40%);">- * TSOP (T)</span><br><span style="color: hsl(0, 100%, 40%);">- * Single Die (<blank>)</span><br><span style="color: hsl(0, 100%, 40%);">- * Lead Free (P)</span><br><span style="color: hsl(0, 100%, 40%);">- * DDR400 3-3-3 (D43)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPD array */</span><br><span style="color: hsl(0, 100%, 40%);">-static const u8 spdbytes[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_BANK_DENSITY] = 0x40,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MEMORY_TYPE] = 7,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_BANKS_PER_SDRAM] = 4,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_PRIMARY_SDRAM_WIDTH] = 8,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_COLUMNS] = 0xa,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_ROWS] = 3,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_REFRESH] = 0x3a,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_SDRAM_CYCLE_TIME_2ND] = 60,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_SDRAM_CYCLE_TIME_3RD] = 75,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRAS] = 40,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRCD] = 15,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRFC] = 70,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRP] = 15,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRRD] = 10,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_read_byte(unsigned int device, unsigned int address)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (device != DIMM0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " returns 0xff\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return 0xff;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " addr %02x returns %02x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- address, spdbytes[address]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return spdbytes[address];</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void asmlinkage mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static const struct mem_controller memctrl[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {.channel0 = {DIMM0}},</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- SystemPreInit();</span><br><span style="color: hsl(0, 100%, 40%);">- lx_msr_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_early_setup();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NOTE: Must do this AFTER cs5536_early_setup()!</span><br><span style="color: hsl(0, 100%, 40%);">- * It is counting on some early MSR setup for the CS5536.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_disable_internal_uart();</span><br><span style="color: hsl(0, 100%, 40%);">- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(0, 100%, 40%);">- console_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Halt if there was a built in self test failure */</span><br><span style="color: hsl(0, 100%, 40%);">- report_bist_failure(bist);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- lx_pll_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sdram_initialize(1, memctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Switch from Cache as RAM to real RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * There are two ways we could think about this.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. If we are using the romstage.inc ROMCC way, the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * going to be re-setup in the code following this code. Just</span><br><span style="color: hsl(0, 100%, 40%);">- * wbinvd the stack to clear the cache tags. We don't care</span><br><span style="color: hsl(0, 100%, 40%);">- * where the stack used to be.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 2. This file is built as a normal .c -> .o and linked in</span><br><span style="color: hsl(0, 100%, 40%);">- * etc. The stack might be used to return etc. That means we</span><br><span style="color: hsl(0, 100%, 40%);">- * care about what is in the stack. If we are smart we set</span><br><span style="color: hsl(0, 100%, 40%);">- * the CAR stack to the same location as the rest of</span><br><span style="color: hsl(0, 100%, 40%);">- * coreboot. If that is the case we can just do a wbinvd.</span><br><span style="color: hsl(0, 100%, 40%);">- * The stack will be written into real RAM that is now setup</span><br><span style="color: hsl(0, 100%, 40%);">- * and we continue like nothing happened. If the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * located somewhere other than where LB would like it, you</span><br><span style="color: hsl(0, 100%, 40%);">- * need to write some code to do a copy from cache to RAM</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * We use method 1 on Norwich and on this board too.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x02);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "POST 02\n");</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__("wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Past wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We are finding the return does not work on this board. Explicitly</span><br><span style="color: hsl(0, 100%, 40%);">- * call the label that is after the call to us. This is gross, but</span><br><span style="color: hsl(0, 100%, 40%);">- * sometimes at this level it is the only way out.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- done_cache_as_ram_main();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/pcengines/alix2c/Kconfig b/src/mainboard/pcengines/alix2c/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 8bed484..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2c/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,9 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_PCENGINES_ALIX2C</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# Dummy for abuild</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ALIX.2C"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/mainboard/pcengines/alix2c/Kconfig.name b/src/mainboard/pcengines/alix2c/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index 7583019..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2c/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,2 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_PCENGINES_ALIX2C</span><br><span style="color: hsl(0, 100%, 40%);">- bool "ALIX.2C2 or 2C3"</span><br><span>diff --git a/src/mainboard/pcengines/alix2c/board_info.txt b/src/mainboard/pcengines/alix2c/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index 099a3ca..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2c/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,7 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: alix2c</span><br><span style="color: hsl(0, 100%, 40%);">-Board URL: http://pcengines.ch/alix2c3.htm</span><br><span style="color: hsl(0, 100%, 40%);">-Category: half</span><br><span style="color: hsl(0, 100%, 40%);">-ROM package: TSOP-32</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: LPC</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index aa8e85c..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,33 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool y</span><br><span style="color: hsl(0, 100%, 40%);">- select CPU_AMD_GEODE_LX</span><br><span style="color: hsl(0, 100%, 40%);">- select NORTHBRIDGE_AMD_LX</span><br><span style="color: hsl(0, 100%, 40%);">- select SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">- select HAVE_PIRQ_TABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select PIRQ_ROUTE</span><br><span style="color: hsl(0, 100%, 40%);">- select UDELAY_TSC</span><br><span style="color: hsl(0, 100%, 40%);">- select BOARD_ROMSIZE_KB_512</span><br><span style="color: hsl(0, 100%, 40%);">- select POWER_BUTTON_FORCE_DISABLE</span><br><span style="color: hsl(0, 100%, 40%);">- select NO_EARLY_SMBUS</span><br><span style="color: hsl(0, 100%, 40%);">- select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS</span><br><span style="color: hsl(0, 100%, 40%);">- select MISSING_BOARD_RESET</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_DIR</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default pcengines/alix2d</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_PCENGINES_ALIX2D</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ALIX.2D"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config IRQ_SLOT_COUNT</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 7</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif # BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/Kconfig.name b/src/mainboard/pcengines/alix2d/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index 142256e..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,2 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_PCENGINES_ALIX2D</span><br><span style="color: hsl(0, 100%, 40%);">- bool "ALIX.2D2 or 2D3"</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/board_info.txt b/src/mainboard/pcengines/alix2d/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index f9efc64..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,7 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: alix2d</span><br><span style="color: hsl(0, 100%, 40%);">-Board URL: http://pcengines.ch/alix2d0.htm</span><br><span style="color: hsl(0, 100%, 40%);">-Category: half</span><br><span style="color: hsl(0, 100%, 40%);">-ROM package: TSOP-32</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: LPC</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/cmos.layout b/src/mainboard/pcengines/alix2d/cmos.layout</span><br><span>deleted file mode 100644</span><br><span>index b238a37..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/cmos.layout</span><br><span>+++ /dev/null</span><br><span>@@ -1,28 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-entries</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-0 384 r 0 reserved_memory</span><br><span style="color: hsl(0, 100%, 40%);">-384 1 e 4 boot_option</span><br><span style="color: hsl(0, 100%, 40%);">-388 4 h 0 reboot_counter</span><br><span style="color: hsl(0, 100%, 40%);">-#392 3 r 0 unused</span><br><span style="color: hsl(0, 100%, 40%);">-400 1 e 1 power_on_after_fail</span><br><span style="color: hsl(0, 100%, 40%);">-412 4 e 6 debug_level</span><br><span style="color: hsl(0, 100%, 40%);">-456 1 e 1 ECC_memory</span><br><span style="color: hsl(0, 100%, 40%);">-1008 16 h 0 check_sum</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-enumerations</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ID value text</span><br><span style="color: hsl(0, 100%, 40%);">-1 0 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-1 1 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 0 Enable</span><br><span style="color: hsl(0, 100%, 40%);">-2 1 Disable</span><br><span style="color: hsl(0, 100%, 40%);">-4 0 Fallback</span><br><span style="color: hsl(0, 100%, 40%);">-4 1 Normal</span><br><span style="color: hsl(0, 100%, 40%);">-6 5 Notice</span><br><span style="color: hsl(0, 100%, 40%);">-6 6 Info</span><br><span style="color: hsl(0, 100%, 40%);">-6 7 Debug</span><br><span style="color: hsl(0, 100%, 40%);">-6 8 Spew</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-checksums</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-checksum 392 1007 1008</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb</span><br><span>deleted file mode 100644</span><br><span>index e684a8f..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/devicetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,44 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-chip northbridge/amd/lx</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1.1 on end</span><br><span style="color: hsl(0, 100%, 40%);">- chip southbridge/amd/cs5536</span><br><span style="color: hsl(0, 100%, 40%);">- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK</span><br><span style="color: hsl(0, 100%, 40%);">- # SIRQ Mode = Active(Quiet) mode. Save power....</span><br><span style="color: hsl(0, 100%, 40%);">- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK</span><br><span style="color: hsl(0, 100%, 40%);">- # How to get these? Boot linux and do this:</span><br><span style="color: hsl(0, 100%, 40%);">- # rdmsr 0x51400025</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_enable" = "0x00001002"</span><br><span style="color: hsl(0, 100%, 40%);">- # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_polarity" = "0x0000EFFD"</span><br><span style="color: hsl(0, 100%, 40%);">- # mode is high 10 bits (determined from code)</span><br><span style="color: hsl(0, 100%, 40%);">- register "lpc_serirq_mode" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- # Don't yet know how to find this.</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_gpio_int_route" = "0x0D0C0700"</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_USBP4_device" = "0" #0: host, 1:device</span><br><span style="color: hsl(0, 100%, 40%);">- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_enable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_address" = "0x3F8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com1_irq" = "4"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_enable" = "1" # Wired on Alix.2D13 only</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_address" = "0x2F8"</span><br><span style="color: hsl(0, 100%, 40%);">- register "com2_irq" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">- register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired)</span><br><span style="color: hsl(0, 100%, 40%);">- register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired)</span><br><span style="color: hsl(0, 100%, 40%);">- register "unwanted_vpci[2]" = "0" # End of list has a zero</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.0 on end # ISA Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.1 on end # Flash controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.2 on end # IDE controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.4 on end # OHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci f.5 on end # EHCI</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # APIC cluster is late CPU init.</span><br><span style="color: hsl(0, 100%, 40%);">- device cpu_cluster 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- chip cpu/amd/geode_lx</span><br><span style="color: hsl(0, 100%, 40%);">- device lapic 0 on end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-end</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/irq_tables.c b/src/mainboard/pcengines/alix2d/irq_tables.c</span><br><span>deleted file mode 100644</span><br><span>index 5b3ae20..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/irq_tables.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,112 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">-* This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-* it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">-* published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-* This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-* but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-* GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-*/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/pirq_routing.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/amd/cs5536/cs5536.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Platform IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQA 11</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQB 10</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQC 11</span><br><span style="color: hsl(0, 100%, 40%);">-#define PIRQD 9</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Map */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Link */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */</span><br><span style="color: hsl(0, 100%, 40%);">-#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * ALIX.2D3 interrupt wiring.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Devices are:</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)</span><br><span style="color: hsl(0, 100%, 40%);">- * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- * The only devices that interrupt are:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * What Device IRQ PIN PIN WIRED TO</span><br><span style="color: hsl(0, 100%, 40%);">- * -------------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">- * AES 00:01.2 0a 01 A A</span><br><span style="color: hsl(0, 100%, 40%);">- * eth0 00:09.0 0b 01 A B</span><br><span style="color: hsl(0, 100%, 40%);">- * eth1 00:0a.0 0b 01 A C</span><br><span style="color: hsl(0, 100%, 40%);">- * eth2 00:0b.0 0b 01 A D</span><br><span style="color: hsl(0, 100%, 40%);">- * mpci 00:0c.0 0a 01 A A</span><br><span style="color: hsl(0, 100%, 40%);">- * mpci 00:0c.0 0b 02 B B</span><br><span style="color: hsl(0, 100%, 40%);">- * usb 00:0f.4 0b 04 D D</span><br><span style="color: hsl(0, 100%, 40%);">- * usb 00:0f.5 0b 04 D D</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * The only swizzled interrupts are the ethernet controllers, where INTA is wired to</span><br><span style="color: hsl(0, 100%, 40%);">- * interrupt controller lines B, C and D.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct irq_routing_table intel_irq_routing_table = {</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQ_SIGNATURE,</span><br><span style="color: hsl(0, 100%, 40%);">- PIRQ_VERSION,</span><br><span style="color: hsl(0, 100%, 40%);">- 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* Where the interrupt router lies (bus) */</span><br><span style="color: hsl(0, 100%, 40%);">- (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* IRQs devoted exclusively to PCI usage */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x100B, /* Vendor */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x002B, /* Device */</span><br><span style="color: hsl(0, 100%, 40%);">- 0, /* Miniport data */</span><br><span style="color: hsl(0, 100%, 40%);">- {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, /* Checksum */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* On-board ethernet (Left) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* On-board ethernet (Middle, ALIX.2D3 only) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* On-board ethernet (Right) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mini PCI (slot 1) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Mini PCI (slot 2, ALIX.2D2 only) */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */</span><br><span style="color: hsl(0, 100%, 40%);">- {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long write_pirq_routing_table(unsigned long addr)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return copy_pirq_routing_table(addr, &intel_irq_routing_table);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>deleted file mode 100644</span><br><span>index 9d3e965..0000000</span><br><span>--- a/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,171 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spd.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pnp_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/bist.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/car.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/amd/cs5536/cs5536.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/raminit.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/northbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The part is a Hynix hy5du121622ctp-d43.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * HY 5D U 12 16 2 2 C <blank> T <blank> P D43</span><br><span style="color: hsl(0, 100%, 40%);">- * Hynix</span><br><span style="color: hsl(0, 100%, 40%);">- * DDR SDRAM (5D)</span><br><span style="color: hsl(0, 100%, 40%);">- * VDD 2.5 VDDQ 2.5 (U)</span><br><span style="color: hsl(0, 100%, 40%);">- * 512M 8K REFRESH (12)</span><br><span style="color: hsl(0, 100%, 40%);">- * x16 (16)</span><br><span style="color: hsl(0, 100%, 40%);">- * 4banks (2)</span><br><span style="color: hsl(0, 100%, 40%);">- * SSTL_2 (2)</span><br><span style="color: hsl(0, 100%, 40%);">- * 4th GEN die (C)</span><br><span style="color: hsl(0, 100%, 40%);">- * Normal Power Consumption (<blank>)</span><br><span style="color: hsl(0, 100%, 40%);">- * TSOP (T)</span><br><span style="color: hsl(0, 100%, 40%);">- * Single Die (<blank>)</span><br><span style="color: hsl(0, 100%, 40%);">- * Lead Free (P)</span><br><span style="color: hsl(0, 100%, 40%);">- * DDR400 3-3-3 (D43)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SPD array */</span><br><span style="color: hsl(0, 100%, 40%);">-static const u8 spdbytes[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_BANK_DENSITY] = 0x40,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MEMORY_TYPE] = 7,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_BANKS_PER_SDRAM] = 4,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_PRIMARY_SDRAM_WIDTH] = 8,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_COLUMNS] = 0xa,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_NUM_ROWS] = 3,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_REFRESH] = 0x3a,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_SDRAM_CYCLE_TIME_2ND] = 60,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_SDRAM_CYCLE_TIME_3RD] = 75,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRAS] = 40,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRCD] = 15,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRFC] = 70,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRP] = 15,</span><br><span style="color: hsl(0, 100%, 40%);">- [SPD_tRRD] = 10,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_read_byte(unsigned int device, unsigned int address)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (device != DIMM0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " returns 0xff\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return 0xff;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " addr %02x returns %02x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- address, spdbytes[address]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return spdbytes[address];</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Early mainboard specific GPIO setup. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void mb_gpio_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable LEDs GPIO outputs to light up the leds</span><br><span style="color: hsl(0, 100%, 40%);">- * This is how the original tinyBIOS sets them after boot.</span><br><span style="color: hsl(0, 100%, 40%);">- * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it</span><br><span style="color: hsl(0, 100%, 40%);">- * may be used here, but not after PCI Init.</span><br><span style="color: hsl(0, 100%, 40%);">- * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the</span><br><span style="color: hsl(0, 100%, 40%);">- * leds-alix2.c driver. coreboot dynamically assigns this space,</span><br><span style="color: hsl(0, 100%, 40%);">- * so the driver does not work anymore.</span><br><span style="color: hsl(0, 100%, 40%);">- * Good workaround: use the newer driver</span><br><span style="color: hsl(0, 100%, 40%);">- * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100</span><br><span style="color: hsl(0, 100%, 40%);">- * This resets the GPIO I/O space to 0x6100.</span><br><span style="color: hsl(0, 100%, 40%);">- * This may break other things, though.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void asmlinkage mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static const struct mem_controller memctrl[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {.channel0 = {DIMM0}},</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- SystemPreInit();</span><br><span style="color: hsl(0, 100%, 40%);">- lx_msr_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_early_setup();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* NOTE: Must do this AFTER cs5536_early_setup()!</span><br><span style="color: hsl(0, 100%, 40%);">- * It is counting on some early MSR setup for the CS5536.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_onchipuart(1);</span><br><span style="color: hsl(0, 100%, 40%);">- mb_gpio_init();</span><br><span style="color: hsl(0, 100%, 40%);">- console_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Halt if there was a built in self test failure */</span><br><span style="color: hsl(0, 100%, 40%);">- report_bist_failure(bist);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- lx_pll_reset();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sdram_initialize(1, memctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Switch from Cache as RAM to real RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * There are two ways we could think about this.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. If we are using the romstage.inc ROMCC way, the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * going to be re-setup in the code following this code. Just</span><br><span style="color: hsl(0, 100%, 40%);">- * wbinvd the stack to clear the cache tags. We don't care</span><br><span style="color: hsl(0, 100%, 40%);">- * where the stack used to be.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 2. This file is built as a normal .c -> .o and linked in</span><br><span style="color: hsl(0, 100%, 40%);">- * etc. The stack might be used to return etc. That means we</span><br><span style="color: hsl(0, 100%, 40%);">- * care about what is in the stack. If we are smart we set</span><br><span style="color: hsl(0, 100%, 40%);">- * the CAR stack to the same location as the rest of</span><br><span style="color: hsl(0, 100%, 40%);">- * coreboot. If that is the case we can just do a wbinvd.</span><br><span style="color: hsl(0, 100%, 40%);">- * The stack will be written into real RAM that is now setup</span><br><span style="color: hsl(0, 100%, 40%);">- * and we continue like nothing happened. If the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * located somewhere other than where LB would like it, you</span><br><span style="color: hsl(0, 100%, 40%);">- * need to write some code to do a copy from cache to RAM</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * We use method 1 on Norwich and on this board too.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x02);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "POST 02\n");</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__("wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Past wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We are finding the return does not work on this board. Explicitly</span><br><span style="color: hsl(0, 100%, 40%);">- * call the label that is after the call to us. This is gross, but</span><br><span style="color: hsl(0, 100%, 40%);">- * sometimes at this level it is the only way out.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- done_cache_as_ram_main();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/pcengines/alix6/Kconfig b/src/mainboard/pcengines/alix6/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 41b9cf4..0000000</span><br><span>--- a/src/mainboard/pcengines/alix6/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,9 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_PCENGINES_ALIX6</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# Dummy for abuild</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ALIX.6"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/mainboard/pcengines/alix6/Kconfig.name b/src/mainboard/pcengines/alix6/Kconfig.name</span><br><span>deleted file mode 100644</span><br><span>index c1e77e3..0000000</span><br><span>--- a/src/mainboard/pcengines/alix6/Kconfig.name</span><br><span>+++ /dev/null</span><br><span>@@ -1,2 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config BOARD_PCENGINES_ALIX6</span><br><span style="color: hsl(0, 100%, 40%);">- bool "ALIX.6"</span><br><span>diff --git a/src/mainboard/pcengines/alix6/board_info.txt b/src/mainboard/pcengines/alix6/board_info.txt</span><br><span>deleted file mode 100644</span><br><span>index 6aae4dd..0000000</span><br><span>--- a/src/mainboard/pcengines/alix6/board_info.txt</span><br><span>+++ /dev/null</span><br><span>@@ -1,7 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-Board name: alix6f</span><br><span style="color: hsl(0, 100%, 40%);">-Board URL: http://pcengines.ch/alix6f2.htm</span><br><span style="color: hsl(0, 100%, 40%);">-Category: half</span><br><span style="color: hsl(0, 100%, 40%);">-ROM package: TSOP-32</span><br><span style="color: hsl(0, 100%, 40%);">-ROM protocol: LPC</span><br><span style="color: hsl(0, 100%, 40%);">-ROM socketed: n</span><br><span style="color: hsl(0, 100%, 40%);">-Flashrom support: y</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30325">change 30325</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30325"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b </div>
<div style="display:none"> Gerrit-Change-Number: 30325 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Piotr Król <piotr.krol@3mdeb.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>