<p>Tristan Corrick has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30357">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard: Add Supermicro X10SLM+-F<br><br>This board runs well with coreboot. The documentation part of this<br>commit lists what works and what doesn't.<br><br>Tested with GRUB 2.02 as a payload, loading SeaBIOS which then boots<br>FreeBSD 11.2. It has also been tested with GRUB directly booting Debian<br>GNU/Linux 9.6 (kernel 4.9).<br><br>Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502<br>Signed-off-by: Tristan Corrick <tristan@corrick.kiwi><br>---<br>M Documentation/mainboard/index.md<br>A Documentation/mainboard/supermicro/x10slm-f.md<br>M MAINTAINERS<br>A src/mainboard/supermicro/x10slm-f/Kconfig<br>A src/mainboard/supermicro/x10slm-f/Kconfig.name<br>A src/mainboard/supermicro/x10slm-f/acpi/ec.asl<br>A src/mainboard/supermicro/x10slm-f/acpi/platform.asl<br>A src/mainboard/supermicro/x10slm-f/acpi/superio.asl<br>A src/mainboard/supermicro/x10slm-f/acpi_tables.c<br>A src/mainboard/supermicro/x10slm-f/board_info.txt<br>A src/mainboard/supermicro/x10slm-f/cmos.default<br>A src/mainboard/supermicro/x10slm-f/cmos.layout<br>A src/mainboard/supermicro/x10slm-f/devicetree.cb<br>A src/mainboard/supermicro/x10slm-f/dsdt.asl<br>A src/mainboard/supermicro/x10slm-f/gpio.h<br>A src/mainboard/supermicro/x10slm-f/hda_verb.c<br>A src/mainboard/supermicro/x10slm-f/mainboard.c<br>A src/mainboard/supermicro/x10slm-f/romstage.c<br>18 files changed, 1,042 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30357/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md</span><br><span>index f97e178..4e2b742 100644</span><br><span>--- a/Documentation/mainboard/index.md</span><br><span>+++ b/Documentation/mainboard/index.md</span><br><span>@@ -66,3 +66,7 @@</span><br><span> ## SiFive</span><br><span> </span><br><span> - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Supermicro</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [X10SLM+-F](supermicro/x10slm-f.md)</span><br><span>diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md</span><br><span>new file mode 100644</span><br><span>index 0000000..8d03429</span><br><span>--- /dev/null</span><br><span>+++ b/Documentation/mainboard/supermicro/x10slm-f.md</span><br><span>@@ -0,0 +1,203 @@</span><br><span style="color: hsl(120, 100%, 40%);">+# Supermicro X10SLM+-F</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section details how to run coreboot on the [Supermicro X10SLM+-F].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Required proprietary blobs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Building coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+If you haven't already, build the coreboot toolchain as described in</span><br><span style="color: hsl(120, 100%, 40%);">+:doc:`../../lessons/lesson1`.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+A fully working image should be possible so long as you have the</span><br><span style="color: hsl(120, 100%, 40%);">+Haswell `mrc.bin` file. You can set the basic config with the following</span><br><span style="color: hsl(120, 100%, 40%);">+commands. However, it is strongly advised to use `make menuconfig`</span><br><span style="color: hsl(120, 100%, 40%);">+afterwards (or instead), so that you can see all of the settings.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+make distclean # Note: this will remove your current config, if it exists.</span><br><span style="color: hsl(120, 100%, 40%);">+touch .config</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable VENDOR_SUPERMICRO</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F</span><br><span style="color: hsl(120, 100%, 40%);">+./util/scripts/config --enable HAVE_MRC</span><br><span style="color: hsl(120, 100%, 40%);">+make olddefconfig</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If you don't plan on using coreboot's serial console to collect logs,</span><br><span style="color: hsl(120, 100%, 40%);">+you might want to disable it at this point (`./util/scripts/config</span><br><span style="color: hsl(120, 100%, 40%);">+--disable CONSOLE_SERIAL`). It should reduce the boot time by several</span><br><span style="color: hsl(120, 100%, 40%);">+seconds. However, a more flexible method is to change the console log</span><br><span style="color: hsl(120, 100%, 40%);">+level from within an OS using `util/nvramtool`, or with the `nvramcui`</span><br><span style="color: hsl(120, 100%, 40%);">+payload.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Now, run `make` to build the coreboot image.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Flashing coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+In addition to the information here, please see the</span><br><span style="color: hsl(120, 100%, 40%);">+:doc:`../../flash_tutorial/index`.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Under the vendor firmware, the BIOS region of the flash chip is</span><br><span style="color: hsl(120, 100%, 40%);">+write-protected. Additionally, the vendor flashing tool does not work</span><br><span style="color: hsl(120, 100%, 40%);">+with a coreboot image. So, [external programming](#external-programming)</span><br><span style="color: hsl(120, 100%, 40%);">+needs to be used when first installing coreboot. By default, coreboot is</span><br><span style="color: hsl(120, 100%, 40%);">+not configured to write-protect the BIOS region, so internal programming</span><br><span style="color: hsl(120, 100%, 40%);">+can be used thereafter.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom] may be used to flash coreboot internally:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The use of `--noverify-all` is required since the Management Engine</span><br><span style="color: hsl(120, 100%, 40%);">+region is not readable even by the host.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### External programming</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The main firmware flash chip is an SOIC-8 package located near the CMOS</span><br><span style="color: hsl(120, 100%, 40%);">+battery and SATA ports. It should come with a sticker attached that</span><br><span style="color: hsl(120, 100%, 40%);">+states the firmware revision (e.g. "X10SLH 4.424"). The chip model is</span><br><span style="color: hsl(120, 100%, 40%);">+an N25Q128A, and the datasheet can be found [here][N25Q128A].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+As with [internal programming](#internal-programming), [flashrom] works</span><br><span style="color: hsl(120, 100%, 40%);">+reliably:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```bash</span><br><span style="color: hsl(120, 100%, 40%);">+flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+For flashing to work, power to the board should be disconnected (ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+G3), and power should be supplied from the external programmer. There is</span><br><span style="color: hsl(120, 100%, 40%);">+a diode attached to Vcc, so such flashing should not damage the board.</span><br><span style="color: hsl(120, 100%, 40%);">+During testing, a single X10SLM+-F has been flashed dozens of times this</span><br><span style="color: hsl(120, 100%, 40%);">+way without issue.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## BMC (IPMI)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This board has an ASPEED [AST2400], which has BMC functionality. The</span><br><span style="color: hsl(120, 100%, 40%);">+BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].</span><br><span style="color: hsl(120, 100%, 40%);">+This chip is an MX25L25635F, whose datasheet can be found</span><br><span style="color: hsl(120, 100%, 40%);">+[here][MX25L25635F].</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+### Removing the BMC functionality</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The BMC functionality on this board can be removed. If you do not need</span><br><span style="color: hsl(120, 100%, 40%);">+its features, removing the BMC functionality might increase security.</span><br><span style="color: hsl(120, 100%, 40%);">+This topic has not been widely explored, and you should only **undertake</span><br><span style="color: hsl(120, 100%, 40%);">+this process at your own risk.**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+There is a jumper labelled `JPB1` on the board that states the ability</span><br><span style="color: hsl(120, 100%, 40%);">+to disable the BMC. Though, pins 1 and 2 are fixed together, keeping</span><br><span style="color: hsl(120, 100%, 40%);">+the BMC enabled. It might be possible to disable the BMC by cutting the</span><br><span style="color: hsl(120, 100%, 40%);">+connection between pins 1 and 2 (and then connecting pins 2 and 3). This</span><br><span style="color: hsl(120, 100%, 40%);">+has not been tested so far.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Another approach is to erase the entire BMC firmware chip. However, if</span><br><span style="color: hsl(120, 100%, 40%);">+this is done, and the board's power cycled, the voltage changes on some</span><br><span style="color: hsl(120, 100%, 40%);">+pins of the flash chip, **so it will be harder to flash it again!**</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+To remove the firmware, connect an external programmer to the BMC</span><br><span style="color: hsl(120, 100%, 40%);">+firmware chip. Vcc should **not** be connected via the external</span><br><span style="color: hsl(120, 100%, 40%);">+programmer. The system should be turned off, but the power still</span><br><span style="color: hsl(120, 100%, 40%);">+connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle</span><br><span style="color: hsl(120, 100%, 40%);">+the board, and the BMC should no longer be active.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If you erase the BMC firmware while using the **vendor BIOS**, you</span><br><span style="color: hsl(120, 100%, 40%);">+will need to cut the connection between pins 1 and 2 of `JPB1`. The</span><br><span style="color: hsl(120, 100%, 40%);">+system will stall for two minutes each time when booting, but it will</span><br><span style="color: hsl(120, 100%, 40%);">+eventually start. There is no such delay when running coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## ECC DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">+ECC DRAM seems to work, but please see</span><br><span style="color: hsl(120, 100%, 40%);">+:doc:`../../northbridge/intel/haswell/mrc.bin`</span><br><span style="color: hsl(120, 100%, 40%);">+for caveats.</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Known issues</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- The x8 PCIe slots do not work, as the Haswell code is missing support.</span><br><span style="color: hsl(120, 100%, 40%);">+ The code to support it has been written, but it still needs to be</span><br><span style="color: hsl(120, 100%, 40%);">+ reviewed and merged.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- Broadwell CPUs are not supported. They might work with minimal changes</span><br><span style="color: hsl(120, 100%, 40%);">+ to the code, but this has not been tested.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- The PCH thermal sensor doesn't yet have a driver in coreboot, so it</span><br><span style="color: hsl(120, 100%, 40%);">+ can't be used for temperature readings.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- There is no automatic, OS-independent fan control. This is because</span><br><span style="color: hsl(120, 100%, 40%);">+ the super I/O hardware monitor can only obtain valid CPU temperature</span><br><span style="color: hsl(120, 100%, 40%);">+ readings from the PECI agent, but the required driver doesn't exist</span><br><span style="color: hsl(120, 100%, 40%);">+ in coreboot. The `coretemp` driver can still be used for accurate CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ temperature readings from an OS, and hence the OS can do fan control.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Untested</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- TPM</span><br><span style="color: hsl(120, 100%, 40%);">+- PCIe x4 slot (it will almost certainly work)</span><br><span style="color: hsl(120, 100%, 40%);">+- BMC (IPMI) functionality</span><br><span style="color: hsl(120, 100%, 40%);">+- internal serial port</span><br><span style="color: hsl(120, 100%, 40%);">+- chassis intrusion header</span><br><span style="color: hsl(120, 100%, 40%);">+- SATA DOM header</span><br><span style="color: hsl(120, 100%, 40%);">+- standby power header</span><br><span style="color: hsl(120, 100%, 40%);">+- serial GPIO headers</span><br><span style="color: hsl(120, 100%, 40%);">+- power supply SMBus header</span><br><span style="color: hsl(120, 100%, 40%);">+- jumpers not otherwise mentioned</span><br><span style="color: hsl(120, 100%, 40%);">+- LEDs</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Working</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- USB</span><br><span style="color: hsl(120, 100%, 40%);">+- S3 suspend/resume</span><br><span style="color: hsl(120, 100%, 40%);">+- Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+- SATA</span><br><span style="color: hsl(120, 100%, 40%);">+- external serial port</span><br><span style="color: hsl(120, 100%, 40%);">+- VGA graphics</span><br><span style="color: hsl(120, 100%, 40%);">+- disabling VGA graphics using the jumper</span><br><span style="color: hsl(120, 100%, 40%);">+- hiding the AST2400 using the CMOS setting</span><br><span style="color: hsl(120, 100%, 40%);">+- super I/O hardware monitor (see [Known issues](#known-issues))</span><br><span style="color: hsl(120, 100%, 40%);">+- initialisation with Haswell MRC version 1.6.1 build 2</span><br><span style="color: hsl(120, 100%, 40%);">+- flashrom under coreboot</span><br><span style="color: hsl(120, 100%, 40%);">+- Wake-on-LAN</span><br><span style="color: hsl(120, 100%, 40%);">+- front panel header</span><br><span style="color: hsl(120, 100%, 40%);">+- internal buzzer</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Technology</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+```eval_rst</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| CPU | :doc:`../../northbridge/intel/haswell/index` |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| PCH | Intel Lynx Point (C224) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Super I/O | Nuvoton NCT6776 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | Intel SPS (server version of the ME) |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+| Coprocessor | ASPEED AST2400 |</span><br><span style="color: hsl(120, 100%, 40%);">++------------------+--------------------------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+```</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+## Extra links</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+- [Board manual]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376</span><br><span style="color: hsl(120, 100%, 40%);">+[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[flashrom]: https://flashrom.org/Flashrom</span><br><span style="color: hsl(120, 100%, 40%);">+[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf</span><br><span style="color: hsl(120, 100%, 40%);">+[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm</span><br><span>diff --git a/MAINTAINERS b/MAINTAINERS</span><br><span>index f90315e..fdecc25 100644</span><br><span>--- a/MAINTAINERS</span><br><span>+++ b/MAINTAINERS</span><br><span>@@ -378,6 +378,11 @@</span><br><span> F: src/mainboard/siemens/mc_bdx1/</span><br><span> F: src/mainboard/siemens/mc_tcu3/</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+SUPERMICRO X10SLM+-F MAINBOARD</span><br><span style="color: hsl(120, 100%, 40%);">+M: Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+S: Maintained</span><br><span style="color: hsl(120, 100%, 40%);">+F: src/mainboard/supermicro/x10slm-f/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE</span><br><span> M: Timothy Pearson <tpearson@raptorengineeringinc.com></span><br><span> S: Supported</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..6bf0b2a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/Kconfig</span><br><span>@@ -0,0 +1,59 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_SUPERMICRO_X10SLM_PLUS_F</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_HASWELL</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_ASPEED_AST2050 # Supports AST2400 too.</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_HASWELL</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_LYNXPOINT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NCT6776_COM_A</span><br><span style="color: hsl(120, 100%, 40%);">+ select TSC_MONOTONIC_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CBFS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xb00000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "supermicro/x10slm-f"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "X10SLM+-F"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x0803</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x15d9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig.name b/src/mainboard/supermicro/x10slm-f/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..a1965a3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SUPERMICRO_X10SLM_PLUS_F</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "X10SLM+-F"</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/acpi/ec.asl b/src/mainboard/supermicro/x10slm-f/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..adaf51a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/acpi/platform.asl</span><br><span>@@ -0,0 +1,24 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (Package() { 0, 0 })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS, 1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b12aabd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/acpi/superio.asl</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV SIO0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_PNP_BASE 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+#define NCT6776_SHOW_HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef NCT6776_SHOW_KBC</span><br><span style="color: hsl(120, 100%, 40%);">+#undef NCT6776_SHOW_PP</span><br><span style="color: hsl(120, 100%, 40%);">+#undef NCT6776_SHOW_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a43b499</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/board_info.txt b/src/mainboard/supermicro/x10slm-f/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..e558429</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: server</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2013</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..f404714</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/cmos.default</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Debug</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Keep</span><br><span style="color: hsl(120, 100%, 40%);">+hide_ast2400=Disable</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..cce1f18</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout</span><br><span>@@ -0,0 +1,97 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 3 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 4 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 5 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: mainboard</span><br><span style="color: hsl(120, 100%, 40%);">+416 1 e 1 hide_ast2400</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+3 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+3 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+4 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+4 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+4 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+4 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+4 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+4 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+4 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+5 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+5 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+5 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 423 984</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..434fb59</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb</span><br><span>@@ -0,0 +1,133 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/haswell</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/haswell</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x15d9 0x0803 inherit</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on end # PEG 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.1 on end # PEG 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 off end # IGD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # Mini-HD audio</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/lynxpoint</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x8b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x8a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x8b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x8a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x80"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x85"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_ahci" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x3f"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000295" # Super I/O HWM</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # xHCI controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 on end # Management Engine interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 off end # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # EHCI controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 off end # HD audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe root port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # ASPEED PCI-to-PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCIe root port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # PCIe root port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Intel I210 Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x15d9 0x1533</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on # PCIe root port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Intel I210 Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x15d9 0x1533</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCIe root port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCIe root port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCIe root port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCIe root port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # EHCI controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nuvoton/nct6776</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 off end # Parallel</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 on # UART A</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x03f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # UART B</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x02f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 off end # PS/2 KBC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 off end # CIR</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 off end # GPIO8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.107 off end # GPIO9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 off end # WDT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.108 off end # GPIO0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.208 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.308 off end # GPIO base</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.109 off end # GPIO1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.209 off end # GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.309 off end # GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.409 off end # GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.509 off end # GPIO5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.609 off end # GPIO6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.709 off end # GPIO7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.a off end # ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.b on # HWM, LED</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0290</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.d off end # VID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.e off end # CIR wake-up</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f off end # GPIO PP/OD</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.14 off end # SVID</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.16 off end # Deep sleep</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.17 off end # GPIOA</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # SATA controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # PCH thermal sensor</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..3a587b6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock("dsdt.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 0x20181220)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (\_SB.PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/haswell/acpi/haswell.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/lynxpoint/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/gpio.h b/src/mainboard/supermicro/x10slm-f/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..95a09b9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/gpio.h</span><br><span>@@ -0,0 +1,220 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SUPERMICRO_X10SLM_PLUS_F_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERMICRO_X10SLM_PLUS_F_GPIO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SUPERMICRO_X10SLM_PLUS_F_GPIO_H */</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm-f/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0944532</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/hda_verb.c</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8d0e3b0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/mainboard.c</span><br><span>@@ -0,0 +1,58 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <option.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Hiding the AST2400 might be desirable to reduce attack surface.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The PCIe root port that the AST2400 is on is disabled, but the</span><br><span style="color: hsl(120, 100%, 40%);">+ * AST2400 itself likely remains in an enabled state.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The AST2400 is also attached to the LPC. That interface does not get</span><br><span style="color: hsl(120, 100%, 40%);">+ * disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void hide_ast2400(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1c, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Marking this device as disabled means that the southbridge code</span><br><span style="color: hsl(120, 100%, 40%);">+ * will properly disable the root port when it configures it later.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "The AST2400 is now set to be hidden.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 hide = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (get_option(&hide, "hide_ast2400") == CB_SUCCESS && hide)</span><br><span style="color: hsl(120, 100%, 40%);">+ hide_ast2400();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CHIP_NAME("X10SLM+-F")</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3707290</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/supermicro/x10slm-f/romstage.c</span><br><span>@@ -0,0 +1,122 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2010 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/haswell.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/haswell/pei_data.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/nct6776/nct6776.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "gpio.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct rcba_config_instruction rcba_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_RMW_REG_32(FD, ~0UL, PCH_DISABLE_ALWAYS),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA_END_CONFIG,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);</span><br><span style="color: hsl(120, 100%, 40%);">+ const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select HWM/LED functions instead of floppy functions. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power RAM in S3 and let the PCH handle power failure actions. */</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_set_logical_device(ACPI_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_write_config(ACPI_DEV, 0xe4, 0x70);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_romstage_entry(unsigned long bist)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pei_data pei_data = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pei_version = PEI_VERSION,</span><br><span style="color: hsl(120, 100%, 40%);">+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .epbar = DEFAULT_EPBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pciexbar = DEFAULT_PCIEXBAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .smbusbar = SMBUS_IO_BASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbbar = 0x4000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .wdbsize = 0x1000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .hpet_address = HPET_ADDR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcba = (uintptr_t)DEFAULT_RCBA,</span><br><span style="color: hsl(120, 100%, 40%);">+ .pmbase = DEFAULT_PMBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpiobase = DEFAULT_GPIOBASE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .temp_mmio_base = 0xfed08000,</span><br><span style="color: hsl(120, 100%, 40%);">+ .system_type = 1, /* desktop/server */</span><br><span style="color: hsl(120, 100%, 40%);">+ .tseg_size = CONFIG_SMM_TSEG_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },</span><br><span style="color: hsl(120, 100%, 40%);">+ .ec_present = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ddr_refresh_2x = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .max_ddr3_freq = 1600,</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb2_ports = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Length, Enable, OCn#, Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 0, USB_PORT_INTERNAL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0110, 1, 2, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0110, 1, 2, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .usb3_ports = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable, OCn# */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, USB_OC_PIN_SKIP },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct romstage_params romstage_params = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pei_data = &pei_data,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio_map = &mainboard_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rcba_config = rcba_config,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bist = bist,</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ romstage_common(&romstage_params);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30357">change 30357</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30357"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 </div>
<div style="display:none"> Gerrit-Change-Number: 30357 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tristan Corrick <tristan@corrick.kiwi> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>