<p>Duncan Laurie <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30350">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Duncan Laurie: Looks good to me, approved
EricR Lai: Looks good to me, but someone else must approve
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/sarien: Disable pcie interface for wwan<br><br>WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the<br>usgae of Sarien choose to only use USB interface but not over pci<br>express, so totally disable pci express root port 12.<br><br>BUG=b:1246720<br>TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10<br>cyles can still device can be listed under lsusb.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d<br>Reviewed-on: https://review.coreboot.org/c/30350<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Duncan Laurie <dlaurie@chromium.org><br>Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com><br>---<br>M src/mainboard/google/sarien/variants/arcada/devicetree.cb<br>M src/mainboard/google/sarien/variants/sarien/devicetree.cb<br>2 files changed, 2 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>index a8bb342..52840de 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb</span><br><span>@@ -86,11 +86,6 @@</span><br><span> register "PcieClkSrcUsage[1]" = "10"</span><br><span> register "PcieClkSrcClkReq[1]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # PCIe port 12 for M.2 3042</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[3]" = "11"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # PCIe port 13 for M.2 2280 SSD</span><br><span> register "PcieRpEnable[12]" = "1"</span><br><span> register "PcieClkSrcUsage[4]" = "12"</span><br><span>@@ -240,7 +235,7 @@</span><br><span> device pci 1d.0 on end # PCI Express Port 9</span><br><span> device pci 1d.1 on end # PCI Express Port 10</span><br><span> device pci 1d.2 on end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 on end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span> device pci 1d.4 on end # PCI Express Port 13 (x4)</span><br><span> device pci 1e.0 off end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span>diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>index c24cd02..47abadc 100644</span><br><span>--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb</span><br><span>@@ -95,11 +95,6 @@</span><br><span> register "PcieClkSrcUsage[1]" = "9"</span><br><span> register "PcieClkSrcClkReq[1]" = "1"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # PCIe port 12 for M.2 3042</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcUsage[0]" = "11"</span><br><span style="color: hsl(0, 100%, 40%);">- register "PcieClkSrcClkReq[0]" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # PCIe port 13 for M.2 2280 SSD</span><br><span> register "PcieRpEnable[12]" = "1"</span><br><span> register "PcieClkSrcUsage[2]" = "12"</span><br><span>@@ -259,7 +254,7 @@</span><br><span> device pci 1d.0 on end # PCI Express Port 9</span><br><span> device pci 1d.1 on end # PCI Express Port 10</span><br><span> device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 on end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span> device pci 1d.4 on end # PCI Express Port 13 (x4)</span><br><span> device pci 1e.0 off end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30350">change 30350</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30350"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d </div>
<div style="display:none"> Gerrit-Change-Number: 30350 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Chris Zhou <chris_zhou@compal.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: EricR Lai <ericr_lai@compal.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>