<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30326">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/amd/geode_lx: Drop support<br><br>These chips are still using LATE_CBMEM which was agreed upon to<br>be removed after release 4.7. It is now more than 1 year later<br>and they still linger around.<br><br>The work and review to bring this code up to date can happen on the 4.9<br>branch and then squashed and merged back into mainline when done.<br><br>Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>D src/cpu/amd/geode_lx/Kconfig<br>D src/cpu/amd/geode_lx/Makefile.inc<br>D src/cpu/amd/geode_lx/cache_as_ram.inc<br>D src/cpu/amd/geode_lx/cpubug.c<br>D src/cpu/amd/geode_lx/cpureginit.c<br>D src/cpu/amd/geode_lx/geode_lx_init.c<br>D src/cpu/amd/geode_lx/msrinit.c<br>D src/cpu/amd/geode_lx/syspreinit.c<br>D src/northbridge/amd/lx/Kconfig<br>D src/northbridge/amd/lx/Makefile.inc<br>D src/northbridge/amd/lx/generic_sdram.c<br>D src/northbridge/amd/lx/grphinit.c<br>D src/northbridge/amd/lx/northbridge.c<br>D src/northbridge/amd/lx/northbridge.h<br>D src/northbridge/amd/lx/northbridgeinit.c<br>D src/northbridge/amd/lx/pll_reset.c<br>D src/northbridge/amd/lx/raminit.c<br>D src/northbridge/amd/lx/raminit.h<br>D src/southbridge/amd/cs5536/Kconfig<br>D src/southbridge/amd/cs5536/Makefile.inc<br>D src/southbridge/amd/cs5536/chip.h<br>D src/southbridge/amd/cs5536/cs5536.c<br>D src/southbridge/amd/cs5536/cs5536.h<br>D src/southbridge/amd/cs5536/early_setup.c<br>D src/southbridge/amd/cs5536/early_smbus.c<br>D src/southbridge/amd/cs5536/ide.c<br>D src/southbridge/amd/cs5536/pirq.c<br>D src/southbridge/amd/cs5536/smbus.c<br>D src/southbridge/amd/cs5536/smbus.h<br>29 files changed, 0 insertions(+), 4,988 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30326/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 82a5d46..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,56 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config CPU_AMD_GEODE_LX</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_BOOTBLOCK_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_VERSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_ROMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">- select ARCH_RAMSTAGE_X86_32</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if CPU_AMD_GEODE_LX</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config CPU_SPECIFIC_OPTIONS</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool y</span><br><span style="color: hsl(0, 100%, 40%);">- select NO_MMCONF_SUPPORT</span><br><span style="color: hsl(0, 100%, 40%);">- select TSC_MONOTONIC_TIMER</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DCACHE_RAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0xc8000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DCACHE_RAM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x8000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DCACHE_BSP_STACK_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DCACHE_BSP_STACK_SLUSH</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config DCACHE_AP_STACK_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config GEODE_VSA</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- default y</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config GEODE_VSA_FILE</span><br><span style="color: hsl(0, 100%, 40%);">- bool "Add a VSA image"</span><br><span style="color: hsl(0, 100%, 40%);">- default y</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Select this option if you have an AMD Geode LX vsa that you would</span><br><span style="color: hsl(0, 100%, 40%);">- like to add to your ROM.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- You will be able to specify the location and file name of the</span><br><span style="color: hsl(0, 100%, 40%);">- image later.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VSA_FILENAME</span><br><span style="color: hsl(0, 100%, 40%);">- string "AMD Geode LX VSA path and filename"</span><br><span style="color: hsl(0, 100%, 40%);">- depends on GEODE_VSA_FILE</span><br><span style="color: hsl(0, 100%, 40%);">- default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- The path and filename of the file to use as VSA.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif # CPU_AMD_GEODE_LX</span><br><span>diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 99be61e..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,18 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/tsc</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/lapic</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/cache</span><br><span style="color: hsl(0, 100%, 40%);">-subdirs-y += ../../x86/smm</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += cpureginit.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += syspreinit.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += msrinit.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += geode_lx_init.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += cpubug.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa</span><br><span style="color: hsl(0, 100%, 40%);">-vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa</span><br><span style="color: hsl(0, 100%, 40%);">-vsa-type = stage</span><br><span style="color: hsl(0, 100%, 40%);">-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)</span><br><span>diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span>deleted file mode 100644</span><br><span>index 8250d72..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,225 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */</span><br><span style="color: hsl(0, 100%, 40%);">-#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/post_code.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * DCacheSetup</span><br><span style="color: hsl(0, 100%, 40%);">- * Setup data cache for use as RAM for a stack.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-DCacheSetup:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the BIST result */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">- /* set cache properties */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_RCONF_DEFAULT, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* in LX DCDIS is set after POR which disables the cache..., clear this bit */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DM_CONFIG0,%ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* get cache timing params from BIOS config data locations and apply */</span><br><span style="color: hsl(0, 100%, 40%);">- /* fix delay controls for DM and IM arrays */</span><br><span style="color: hsl(0, 100%, 40%);">- /* fix delay controls for DM and IM arrays */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_BC_MSS_ARRAY_CTL0, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x2814D352, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_BC_MSS_ARRAY_CTL1, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x1068334D, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_BC_MSS_ARRAY_CTL2, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x00000106, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x83104104, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $GLCP_FIFOCTL, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x00000005, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable setting */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x01, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get cleaned up. */</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %esi, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %ebp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */</span><br><span style="color: hsl(0, 100%, 40%);">- /* remember, there is NO stack yet... */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Tell cache we want to fill WAY 0 starting at the top */</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DC_INDEX, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $LX_STACK_BASE, %ebp /* init to start address */</span><br><span style="color: hsl(0, 100%, 40%);">- orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $LX_NUM_CACHELINES, %edi</span><br><span style="color: hsl(0, 100%, 40%);">-DCacheSetupFillWay:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */</span><br><span style="color: hsl(0, 100%, 40%);">- /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */</span><br><span style="color: hsl(0, 100%, 40%);">- movw $0x04, %si</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DC_DATA, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-DCacheSetup_quadWordLoop:</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- decw %si</span><br><span style="color: hsl(0, 100%, 40%);">- jnz DCacheSetup_quadWordLoop</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the tag for this line, need to do this for every new cache line to validate it! */</span><br><span style="color: hsl(0, 100%, 40%);">- /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebp, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DC_TAG, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* switch to next line */</span><br><span style="color: hsl(0, 100%, 40%);">- /* lines are in Bits10:4 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DC_INDEX, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- decl %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz DCacheSetupFillWay</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */</span><br><span style="color: hsl(0, 100%, 40%);">- addl $LX_CACHEWAY_SIZE, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- cmpl $LX_STACK_END, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- jge leave_DCacheSetup</span><br><span style="color: hsl(0, 100%, 40%);">- movl $LX_NUM_CACHELINES, %edi</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* switch to next way */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_DC_INDEX, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- addl $0x01, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- jmp DCacheSetupFillWay</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-leave_DCacheSetup:</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %esi, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %ebp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the cache, but ... DO NOT INVALIDATE the tags. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Memory reads and writes will all hit in the cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache updates and memory write-backs will not occur ! */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now point sp to the cached stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* The stack will be fully functional at this location. No system memory is required at all ! */</span><br><span style="color: hsl(0, 100%, 40%);">- /* set up the stack pointer */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $LX_STACK_END, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* test the stack*/</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x0F0F05A5A, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- cmpl %ecx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- je DCacheSetupGood</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0xc5)</span><br><span style="color: hsl(0, 100%, 40%);">-DCacheSetupBad:</span><br><span style="color: hsl(0, 100%, 40%);">- hlt /* issues */</span><br><span style="color: hsl(0, 100%, 40%);">- jmp DCacheSetupBad</span><br><span style="color: hsl(0, 100%, 40%);">-DCacheSetupGood:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Go do early init and memory setup */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore the BIST result */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebx, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x23)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call romstage.c main function */</span><br><span style="color: hsl(0, 100%, 40%);">- call mainboard_romstage_entry</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.global done_cache_as_ram_main</span><br><span style="color: hsl(0, 100%, 40%);">-done_cache_as_ram_main:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We now run over the stack-in-cache,</span><br><span style="color: hsl(0, 100%, 40%);">- * copying it back to itself to invalidate the cache */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- push %edi</span><br><span style="color: hsl(0, 100%, 40%);">- mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx</span><br><span style="color: hsl(0, 100%, 40%);">- push %esi</span><br><span style="color: hsl(0, 100%, 40%);">- mov $(CONFIG_DCACHE_RAM_BASE),%edi</span><br><span style="color: hsl(0, 100%, 40%);">- mov %edi,%esi</span><br><span style="color: hsl(0, 100%, 40%);">- cld</span><br><span style="color: hsl(0, 100%, 40%);">- rep movsl %ds:(%esi),%es:(%edi)</span><br><span style="color: hsl(0, 100%, 40%);">- pop %esi</span><br><span style="color: hsl(0, 100%, 40%);">- pop %edi</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the cache out to RAM */</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd</span><br><span style="color: hsl(0, 100%, 40%);">- /* re-enable the cache */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TODO For suspend/resume low memory needs backup store. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* clear direction flag */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* copy coreboot from it's initial load location to</span><br><span style="color: hsl(0, 100%, 40%);">- * the location it is compiled to run at.</span><br><span style="color: hsl(0, 100%, 40%);">- * Normally this is copying from FLASH ROM to RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- call copy_and_run</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(0, 100%, 40%);">- hlt</span><br><span style="color: hsl(0, 100%, 40%);">- jmp .Lhlt</span><br><span>diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c</span><br><span>deleted file mode 100644</span><br><span>index 7e7d81b..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/cpubug.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,84 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * pcideadlock</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Bugtool #465 and #609</span><br><span style="color: hsl(0, 100%, 40%);">- * PCI cache deadlock</span><br><span style="color: hsl(0, 100%, 40%);">- * There is also fix code in cache and PCI functions.</span><br><span style="color: hsl(0, 100%, 40%);">- * This bug is very is pervasive.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pcideadlock(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * forces serialization of all load misses. Setting this bit prevents the</span><br><span style="color: hsl(0, 100%, 40%);">- * DM pipe from backing up if a read request has to be held up waiting</span><br><span style="color: hsl(0, 100%, 40%);">- * for PCI writes to complete.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_DM_CONFIG0);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_DM_CONFIG0, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* write serialize memory hole to PCI. Need to unWS when something is</span><br><span style="color: hsl(0, 100%, 40%);">- * shadowed regardless of cachablility.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x021212121;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x021212121;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_A0_BF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_C0_DF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_E0_FF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * DisableMemoryReorder</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * PBZ 3659:</span><br><span style="color: hsl(0, 100%, 40%);">- * The MC reordered transactions incorrectly and breaks coherency.</span><br><span style="color: hsl(0, 100%, 40%);">- * Disable reordering and take a potential performance hit.</span><br><span style="color: hsl(0, 100%, 40%);">- * This is safe to do here and not in MC init since there is nothing</span><br><span style="color: hsl(0, 100%, 40%);">- * to maintain coherency with and the cache is not enabled yet.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void disablememoryreadorder(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF8F_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF8F_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* For CPU version C3. Should be the only released version */</span><br><span style="color: hsl(0, 100%, 40%);">-void cpubug(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- pcideadlock();</span><br><span style="color: hsl(0, 100%, 40%);">- disablememoryreadorder();</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Done cpubug fixes\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c</span><br><span>deleted file mode 100644</span><br><span>index a61501e..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/cpureginit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,256 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spd.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/raminit.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/northbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Delay Control Settings table from AMD (MCP 0x4C00000F).</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static const msrinit_t delay_msr_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}},</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}},</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct delay_controls {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 dimms;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 devices;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 slow_hi;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 slow_low;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 fast_hi;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 fast_low;</span><br><span style="color: hsl(0, 100%, 40%);">-} delay_control_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">- { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 },</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM</span><br><span style="color: hsl(0, 100%, 40%);">- * in slot 0, but it should be clear for all 2 DIMM settings and if a</span><br><span style="color: hsl(0, 100%, 40%);">- * single DIMM is in slot 1. Bits 54:52 should always be set to '111'.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Settings for single DIMM and no VTT termination (like DB800 platform)</span><br><span style="color: hsl(0, 100%, 40%);">- * 0xF2F100FF 0x56960004</span><br><span style="color: hsl(0, 100%, 40%);">- * -------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">- * ADDR/CTL have 22 ohm series R</span><br><span style="color: hsl(0, 100%, 40%);">- * DQ/DQM/DQS have 33 ohm series R</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * This is Black Magic DRAM timing juju[1].</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * DRAM delay depends on CPU clock, memory bus clock, memory bus loading,</span><br><span style="color: hsl(0, 100%, 40%);">- * memory bus termination, your middle initial (ha! caught you!), GeodeLink</span><br><span style="color: hsl(0, 100%, 40%);">- * clock rate, and DRAM timing specifications.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * From this the code computes a number which is "known to work". No,</span><br><span style="color: hsl(0, 100%, 40%);">- * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger)</span><br><span style="color: hsl(0, 100%, 40%);">- * is hooked up, then just don't do anything. This code was written by a master</span><br><span style="color: hsl(0, 100%, 40%);">- * of the Dark Arts at AMD and should not be modified in any way.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * [1] (http://www.thefreedictionary.com/juju)</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent).</span><br><span style="color: hsl(0, 100%, 40%);">- * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent).</span><br><span style="color: hsl(0, 100%, 40%);">- * @param terminated The bus is terminated. (mainboard dependent).</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 glspeed;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 spdbyte0, spdbyte1, dimms, i;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- glspeed = GeodeLinkSpeed();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fix delay controls for DM and IM arrays. */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLCP_FIFOCTL);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x00000005;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLCP_FIFOCTL, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable setting. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x00000001;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Debug Delay Control setup check.</span><br><span style="color: hsl(0, 100%, 40%);">- * Leave it alone if it has been setup. FS2 or something is here.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLCP_DELAY_CONTROLS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.lo & ~(DELAY_LOWER_STATUS_MASK))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Delay Controls based on DIMM loading. UGH!</span><br><span style="color: hsl(0, 100%, 40%);">- * Number of devices = module width (SPD 6) / device width (SPD 13)</span><br><span style="color: hsl(0, 100%, 40%);">- * * physical banks (SPD 5)</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Note: We only support a module width of 64.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- dimms = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spdbyte0 != 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- dimms++;</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte0 = (u8)64 / spdbyte0 *</span><br><span style="color: hsl(0, 100%, 40%);">- (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS));</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spdbyte1 != 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- dimms++;</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte1 = (u8)64 / spdbyte1 *</span><br><span style="color: hsl(0, 100%, 40%);">- (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS));</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero GLCP_DELAY_CONTROLS MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = msr.lo = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save some power, disable clock to second DIMM if it is empty. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (spdbyte1 == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= DELAY_UPPER_DISABLE_CLK135;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spdbyte0 += spdbyte1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dimms == 1) && (terminated == DRAM_TERMINATED)) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0xF2F100FF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x56960004;</span><br><span style="color: hsl(0, 100%, 40%);">- } else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dimms == delay_control_table[i].dimms) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (spdbyte0 <= delay_control_table[i].devices)) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (glspeed < 334) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= delay_control_table[i].slow_hi;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= delay_control_table[i].slow_low;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= delay_control_table[i].fast_hi;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= delay_control_table[i].fast_low;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLCP_DELAY_CONTROLS, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Castle 2.0 BTM periodic sync period. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* [40:37] 1 sync record per 256 bytes */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Castle 2.0 BTM periodic sync period.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_PF_CONF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= (0x8 << 5);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * LX performance setting.</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable Quack for fewer re-RAS on the MC</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enable Quack for fewer re-RAS on the MC\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLIU0_ARB;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~ARB_UPPER_DACK_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= ARB_UPPER_QUACK_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLIU1_ARB;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~ARB_UPPER_DACK_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= ARB_UPPER_QUACK_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GLIU port active enable, limit south pole masters</span><br><span style="color: hsl(0, 100%, 40%);">- * (AES and PCI) to one outstanding transaction.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " GLIU port active enable\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLIU1_PORT_ACTIVE;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0x880;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the Delay Control in GLCP */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Set the Delay Control in GLCP\n");</span><br><span style="color: hsl(0, 100%, 40%);">- SetDelayControl(dimm0, dimm1, terminated);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable RSDC */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enable RSDC\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_AC_SMM_CTL;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= SMM_INST_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* FPU imprecise exceptions bit */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "FPU imprecise exceptions bit\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_FPU_MSR_MODE;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= FPU_IE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Power Savers (Do after BIST) */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Suspend on HLT & PAUSE instructions */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enable Suspend on HLT & PAUSE instructions\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_XC_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enable SUSP and allow TSC to run in Suspend\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_BC_CONF_0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= 0x0F0FFFFFF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the debug clock to save power. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* NOTE: leave it enabled for fs2 debug */</span><br><span style="color: hsl(0, 100%, 40%);">- if (debug_clock_disable && 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLCP_DBGCLKCTL;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup throttling delays to proper mode if it is ever enabled. */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Setup throttling delays to proper mode\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLCP_TH_OD;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x00000603C;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Done cpuRegInit\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c</span><br><span>deleted file mode 100644</span><br><span>index e620131..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/geode_lx_init.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,69 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/lapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void vsm_end_post_smi(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__ volatile ("push %ax\n"</span><br><span style="color: hsl(0, 100%, 40%);">- "mov $0x5000, %ax\n"</span><br><span style="color: hsl(0, 100%, 40%);">- ".byte 0x0f, 0x38\n" "pop %ax\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void geode_lx_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "geode_lx_init\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn on caching if we haven't already */</span><br><span style="color: hsl(0, 100%, 40%);">- x86_enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the local CPU APICs */</span><br><span style="color: hsl(0, 100%, 40%);">- //setup_lapic();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // do VSA late init</span><br><span style="color: hsl(0, 100%, 40%);">- vsm_end_post_smi();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Set gate A20 (legacy vsm disables it in late init)</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x02, 0x92);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU geode_lx_init DONE\n");</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations cpu_dev_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .init = geode_lx_init,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_device_id cpu_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {X86_VENDOR_AMD, 0x05A2},</span><br><span style="color: hsl(0, 100%, 40%);">- {0, 0},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct cpu_driver driver __cpu_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &cpu_dev_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .id_table = cpu_table,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c</span><br><span>deleted file mode 100644</span><br><span>index 827bb61..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/msrinit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,60 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2010 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/northbridge.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const msrinit_t msr_table[] =</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.</span><br><span style="color: hsl(0, 100%, 40%);">- * Rom Properties: Write Serialize, WriteProtect.</span><br><span style="color: hsl(0, 100%, 40%);">- * RomBase: 0xFFFC0</span><br><span style="color: hsl(0, 100%, 40%);">- * SysTop to RomBase Properties: Write Back.</span><br><span style="color: hsl(0, 100%, 40%);">- * SysTop: 0x000A0</span><br><span style="color: hsl(0, 100%, 40%);">- * System Memory Properties: (Write Back) */</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.</span><br><span style="color: hsl(0, 100%, 40%);">- * It doesn't really matter in fact how much, however, because the only usage</span><br><span style="color: hsl(0, 100%, 40%);">- * of this extended memory will be to host the ramstage stage at RAMBASE,</span><br><span style="color: hsl(0, 100%, 40%);">- * currently 1Mb.</span><br><span style="color: hsl(0, 100%, 40%);">- * These registers will be set to their correct value by the Northbridge init code.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * WARNING: if ramstage could not be loaded, these registers are probably</span><br><span style="color: hsl(0, 100%, 40%);">- * incorrectly set here. You may comment the following two lines and set RAMBASE</span><br><span style="color: hsl(0, 100%, 40%);">- * to 0x4000 to revert to the previous behavior for LX-boards.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000</span><br><span style="color: hsl(0, 100%, 40%);">- {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void lx_msr_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(msr_table); i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msr_table[i].index, msr_table[i].msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c</span><br><span>deleted file mode 100644</span><br><span>index f30c059..0000000</span><br><span>--- a/src/cpu/amd/geode_lx/syspreinit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * StartTimer1</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry: none</span><br><span style="color: hsl(0, 100%, 40%);">- * Exit: Starts Timer 1 for port 61 use</span><br><span style="color: hsl(0, 100%, 40%);">- * Destroys: Al,</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void StartTimer1(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x56, 0x43);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x12, 0x41);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void SystemPreInit(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* they want a jump ... */</span><br><span style="color: hsl(0, 100%, 40%);">- StartTimer1();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 53a0e05..0000000</span><br><span>--- a/src/northbridge/amd/lx/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-config NORTHBRIDGE_AMD_LX</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select GEODE_VSA</span><br><span style="color: hsl(0, 100%, 40%);">- select LATE_CBMEM_INIT</span><br><span style="color: hsl(0, 100%, 40%);">- select NO_RELOCATABLE_RAMSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if NORTHBRIDGE_AMD_LX</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config VIDEO_MB</span><br><span style="color: hsl(0, 100%, 40%);">- int</span><br><span style="color: hsl(0, 100%, 40%);">- default 8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config PLL_MANUAL_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if PLL_MANUAL_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-# "Core/GLIU Frequency"</span><br><span style="color: hsl(0, 100%, 40%);">-config CORE_GLIU_500_266</span><br><span style="color: hsl(0, 100%, 40%);">- bool # "500MHz / 266MHz"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config CORE_GLIU_500_333</span><br><span style="color: hsl(0, 100%, 40%);">- bool # "500MHz / 333MHz"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config CORE_GLIU_500_400</span><br><span style="color: hsl(0, 100%, 40%);">- bool # "500MHz / 400MHz"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config PLLMSRhi</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x39c if CORE_GLIU_500_266</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x49c if CORE_GLIU_500_333</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x59c if CORE_GLIU_500_400</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config PLLMSRlo</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index e36139f..0000000</span><br><span>--- a/src/northbridge/amd/lx/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,11 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(CONFIG_NORTHBRIDGE_AMD_LX),y)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += northbridge.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += northbridgeinit.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += grphinit.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += raminit.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += generic_sdram.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += pll_reset.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c</span><br><span>deleted file mode 100644</span><br><span>index e0869cd..0000000</span><br><span>--- a/src/northbridge/amd/lx/generic_sdram.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,42 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <northbridge/amd/lx/raminit.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Setup SDRAM */</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_initialize(int controllers, const struct mem_controller *ctrl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the registers we can set once to reasonable values */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < controllers; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Ram1.%02x\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- sdram_set_registers(ctrl + i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now setup those things we can auto detect */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < controllers; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Ram2.%02x\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- sdram_set_spd_registers(ctrl + i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now that everything is setup enable the SDRAM.</span><br><span style="color: hsl(0, 100%, 40%);">- * Some chipsets do the work for us while on others</span><br><span style="color: hsl(0, 100%, 40%);">- * we need to it by hand.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Ram3\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sdram_enable(controllers, ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Ram4\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c</span><br><span>deleted file mode 100644</span><br><span>index 1adb9af..0000000</span><br><span>--- a/src/northbridge/amd/lx/grphinit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,99 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/vr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void geodelx_vga_msr_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void graphics_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct msrinit {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct msrinit geodelx_vga_msr[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the GLIU Memory routing to the hardware</span><br><span style="color: hsl(0, 100%, 40%);">- * PDID1 : Port 4, GLIU0</span><br><span style="color: hsl(0, 100%, 40%);">- * PBASE : 0x000A0</span><br><span style="color: hsl(0, 100%, 40%);">- * PMASK : 0xFFFE0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- {.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the GLIU IO Routing</span><br><span style="color: hsl(0, 100%, 40%);">- * IDID : Port 4, GLIU0</span><br><span style="color: hsl(0, 100%, 40%);">- * IBASE : 0x003c0</span><br><span style="color: hsl(0, 100%, 40%);">- * IMASK : 0xffff0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- {.msrnum = GLIU0_IOD_BM_0, {.lo = 0x3c0ffff0, .hi = 0x80000000}},</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable the GLIU IO Routing</span><br><span style="color: hsl(0, 100%, 40%);">- * IDID : Port 4, GLIU0</span><br><span style="color: hsl(0, 100%, 40%);">- * IBASE : 0x003d0</span><br><span style="color: hsl(0, 100%, 40%);">- * IMASK : 0xffff0</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- {.msrnum = GLIU0_IOD_BM_1, {.lo = 0x3d0ffff0, .hi = 0x80000000}},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void geodelx_vga_msr_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * This function mirrors the Graphics_Init routine in GeodeROM.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void graphics_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t wClassIndex, wData, res;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SoftVG initialization */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Graphics init...\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- geodelx_vga_msr_init();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call SoftVG with the main configuration parameters. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wClassIndex = (VRC_VG << 8) + VG_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)</span><br><span style="color: hsl(0, 100%, 40%);">- * External Monochrome Card Support(12) 0, NO</span><br><span style="color: hsl(0, 100%, 40%);">- * Controller Priority Select(11) 1, Primary</span><br><span style="color: hsl(0, 100%, 40%);">- * Display Select(10:8) 0x0, CRT</span><br><span style="color: hsl(0, 100%, 40%);">- * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,</span><br><span style="color: hsl(0, 100%, 40%);">- * defined in devicetree.cb</span><br><span style="color: hsl(0, 100%, 40%);">- * PLL Reference Clock Bypass(0) 0, Default</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Video RAM has to be given in 2MB chunks</span><br><span style="color: hsl(0, 100%, 40%);">- * the value is read @ 7:1 (value in 7:0 looks like /2)</span><br><span style="color: hsl(0, 100%, 40%);">- * so we can add the real value in megabytes</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |</span><br><span style="color: hsl(0, 100%, 40%);">- VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">- vrWrite(wClassIndex, wData);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- res = vrRead(wClassIndex);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c</span><br><span>deleted file mode 100644</span><br><span>index ffaaa19..0000000</span><br><span>--- a/src/northbridge/amd/lx/northbridge.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,425 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/vr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/amd/cs5536/cs5536.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* here is programming for the various MSRs.*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define IM_QWAIT 0x100000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* these are the 8-bit attributes for controlling RCONF registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_DISABLE (1<<0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRITE_ALLOCATE (1<<1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRITE_PROTECT (1<<2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRITE_THROUGH (1<<3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRITE_COMBINE (1<<4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define WRITE_SERIALIZE (1<<5)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* RAM has none of this stuff */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RAM_PROPERTIES (0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_WS_CD_DEFAULT (0x21212121)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* 1810-1817 give you 8 registers with which to program protection regions */</span><br><span style="color: hsl(0, 100%, 40%);">-/* the are region configuration range registers, or RRCF */</span><br><span style="color: hsl(0, 100%, 40%);">-/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */</span><br><span style="color: hsl(0, 100%, 40%);">-/* so no left-shift needed for top or base */</span><br><span style="color: hsl(0, 100%, 40%);">-#define RRCF_LOW(base,properties) (base|(1<<8)|properties)</span><br><span style="color: hsl(0, 100%, 40%);">-#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* build initializer for P2D MSR */</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}</span><br><span style="color: hsl(0, 100%, 40%);">-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void print_conf(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void graphics_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void do_vsmbios(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct msr_defaults {</span><br><span style="color: hsl(0, 100%, 40%);">- int msr_no;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-} msr_defaults[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1700, {</span><br><span style="color: hsl(0, 100%, 40%);">- .hi = 0,.lo = IM_QWAIT}}, {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1800, {</span><br><span style="color: hsl(0, 100%, 40%);">- .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =</span><br><span style="color: hsl(0, 100%, 40%);">- DMCF_SERIAL_LOAD_MISSES}},</span><br><span style="color: hsl(0, 100%, 40%);">- /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */</span><br><span style="color: hsl(0, 100%, 40%);">- /* for 180a, for now, we assume VSM will configure it */</span><br><span style="color: hsl(0, 100%, 40%);">- /* 180b is left at reset value,a0000-bffff is non-cacheable */</span><br><span style="color: hsl(0, 100%, 40%);">- /* 180c, c0000-dffff is set to write serialize and non-cachable */</span><br><span style="color: hsl(0, 100%, 40%);">- /* oops, 180c will be set by CPU bug handling in cpubug.c */</span><br><span style="color: hsl(0, 100%, 40%);">- //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},</span><br><span style="color: hsl(0, 100%, 40%);">- /* 180d is left at default, e0000-fffff is non-cached */</span><br><span style="color: hsl(0, 100%, 40%);">- /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */</span><br><span style="color: hsl(0, 100%, 40%);">- /* we will not set 0x180f, the DMM,yet */</span><br><span style="color: hsl(0, 100%, 40%);">- //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},</span><br><span style="color: hsl(0, 100%, 40%);">- //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},</span><br><span style="color: hsl(0, 100%, 40%);">- //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},</span><br><span style="color: hsl(0, 100%, 40%);">- //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},</span><br><span style="color: hsl(0, 100%, 40%);">- /* now for GLPCI routing */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GLIU0 */</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),</span><br><span style="color: hsl(0, 100%, 40%);">- /* GLIU1 */</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),</span><br><span style="color: hsl(0, 100%, 40%);">- P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {</span><br><span style="color: hsl(0, 100%, 40%);">- 0}</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Print the platform configuration - do before PCI init or it will not</span><br><span style="color: hsl(0, 100%, 40%);">- * work right.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void print_conf(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long iol;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,</span><br><span style="color: hsl(0, 100%, 40%);">- GLCP_DELAY_CONTROLS, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,</span><br><span style="color: hsl(0, 100%, 40%);">- MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,</span><br><span style="color: hsl(0, 100%, 40%);">- MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU0_GLD_MSR_COH, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,</span><br><span style="color: hsl(0, 100%, 40%);">- MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,</span><br><span style="color: hsl(0, 100%, 40%);">- MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,</span><br><span style="color: hsl(0, 100%, 40%);">- MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,</span><br><span style="color: hsl(0, 100%, 40%);">- GLIU1_GLD_MSR_COH, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,</span><br><span style="color: hsl(0, 100%, 40%);">- CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_IRQM_PRIM, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- CPU ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; cpu_msr_defs[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(cpu_msr_defs[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_msr_defs[i], msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(gliu0_msr_defs[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",</span><br><span style="color: hsl(0, 100%, 40%);">- gliu0_msr_defs[i], msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(gliu1_msr_defs[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",</span><br><span style="color: hsl(0, 100%, 40%);">- gliu1_msr_defs[i], msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- RCONF ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; rconf_msr[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(rconf_msr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- VARIA ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(0x51300010);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(0x51400015);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_YLOW);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_YHIGH);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_ZLOW);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_ZHIGH);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- PCI ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; pci_msr[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(pci_msr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; dma_msr[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(dma_msr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "---------- CS5536 ------------\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; cs5536_msr[i] != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(cs5536_msr[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);</span><br><span style="color: hsl(0, 100%, 40%);">- iol = inl(GPIOL_EVENTS_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);</span><br><span style="color: hsl(0, 100%, 40%);">- iol = inl(GPIOL_INPUT_INVERT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);</span><br><span style="color: hsl(0, 100%, 40%);">- iol = inl(GPIO_MAPPER_X);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,</span><br><span style="color: hsl(0, 100%, 40%);">- iol);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* todo: add a resource record. We don't do this here because this may be called when</span><br><span style="color: hsl(0, 100%, 40%);">- * very little of the platform is actually working.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-int sizeram(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- int sizem = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned short dimm;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* dimm 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm = msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">- /* installed? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dimm & 7) != 7) {</span><br><span style="color: hsl(0, 100%, 40%);">- sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* dimm 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm = msr.hi >> 16;</span><br><span style="color: hsl(0, 100%, 40%);">- /* installed? */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dimm & 7) != 7) {</span><br><span style="color: hsl(0, 100%, 40%);">- sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);</span><br><span style="color: hsl(0, 100%, 40%);">- return sizem;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_shadow(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void northbridge_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- enable_shadow(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void northbridge_set_resources(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t line;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- struct bus *bus;</span><br><span style="color: hsl(0, 100%, 40%);">- for (bus = dev->link_list; bus; bus = bus->next) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (bus->children) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- bus->secondary);</span><br><span style="color: hsl(0, 100%, 40%);">- assign_resources(bus);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set a default latency timer */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set a default secondary latency timer */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* zero the irq settings */</span><br><span style="color: hsl(0, 100%, 40%);">- line = pci_read_config8(dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(0, 100%, 40%);">- if (line) {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set the cache line size, so far 64 bytes is good for everyone */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations northbridge_operations = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = pci_dev_read_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = northbridge_set_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = pci_dev_enable_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .init = northbridge_init,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_pci = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pci_driver northbridge_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &northbridge_operations,</span><br><span style="color: hsl(0, 100%, 40%);">- .vendor = PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- .device = PCI_DEVICE_ID_AMD_LXBRIDGE,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int idx;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 tomk;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *mc_dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mc_dev = dev->link_list->children;</span><br><span style="color: hsl(0, 100%, 40%);">- if (mc_dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- tomk = restore_top_of_low_cacheable() / 1024;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Report the memory regions</span><br><span style="color: hsl(0, 100%, 40%);">- All memory up to systop except 0xa0000-0xbffff */</span><br><span style="color: hsl(0, 100%, 40%);">- idx = 10;</span><br><span style="color: hsl(0, 100%, 40%);">- ram_resource(dev, idx++, 0, 640);</span><br><span style="color: hsl(0, 100%, 40%);">- ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- set_late_cbmem_top(tomk * 1024);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- assign_resources(dev->link_list);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_enable(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // do this here for now -- this chip really breaks our device model</span><br><span style="color: hsl(0, 100%, 40%);">- northbridge_init_early();</span><br><span style="color: hsl(0, 100%, 40%);">- cpubug();</span><br><span style="color: hsl(0, 100%, 40%);">- chipsetinit();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- do_vsmbios(); // do the magic stuff here, so prepare your tambourine;)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- graphics_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations pci_domain_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = pci_domain_read_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = pci_domain_set_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = NULL,</span><br><span style="color: hsl(0, 100%, 40%);">- .scan_bus = pci_domain_scan_bus,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable = pci_domain_enable,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- initialize_cpus(dev->link_list);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations cpu_bus_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = DEVICE_NOOP,</span><br><span style="color: hsl(0, 100%, 40%);">- .init = cpu_bus_init,</span><br><span style="color: hsl(0, 100%, 40%);">- .scan_bus = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",</span><br><span style="color: hsl(0, 100%, 40%);">- __func__, dev->path.type);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the operations if it is a special bus type */</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev->path.type == DEVICE_PATH_DOMAIN)</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops = &pci_domain_ops;</span><br><span style="color: hsl(0, 100%, 40%);">- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)</span><br><span style="color: hsl(0, 100%, 40%);">- dev->ops = &cpu_bus_ops;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct chip_operations northbridge_amd_lx_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- CHIP_NAME("AMD LX Northbridge")</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_dev = enable_dev,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h</span><br><span>deleted file mode 100644</span><br><span>index 51c2c14..0000000</span><br><span>--- a/src/northbridge/amd/lx/northbridge.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,31 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef NORTHBRIDGE_AMD_LX_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define NORTHBRIDGE_AMD_LX_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* northbridge.c */</span><br><span style="color: hsl(0, 100%, 40%);">-int sizeram(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* northbridgeinit.c */</span><br><span style="color: hsl(0, 100%, 40%);">-void northbridge_init_early(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* pll_reset.c */</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned int GeodeLinkSpeed(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void lx_pll_reset(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void lx_msr_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>deleted file mode 100644</span><br><span>index 9655c0e..0000000</span><br><span>--- a/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,754 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct gliutable {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long desc_name;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned short desc_type;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long hi, lo;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct gliutable gliu0table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0}, /* Catch and fix dynamicly. */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =</span><br><span style="color: hsl(0, 100%, 40%);">- GL0_CPU},</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct gliutable gliu1table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =</span><br><span style="color: hsl(0, 100%, 40%);">- GL1_GLIU0},</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */</span><br><span style="color: hsl(0, 100%, 40%);">- {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct msrinit {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct msrinit ClockGatingDefault[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},</span><br><span style="color: hsl(0, 100%, 40%);">- {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},</span><br><span style="color: hsl(0, 100%, 40%);">- {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},</span><br><span style="color: hsl(0, 100%, 40%);">- {VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}},</span><br><span style="color: hsl(0, 100%, 40%);">- {0xffffffff, {0xffffffff, 0xffffffff}},</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SET GeodeLink PRIORITY*/</span><br><span style="color: hsl(0, 100%, 40%);">-/* */</span><br><span style="color: hsl(0, 100%, 40%);">-struct msrinit GeodeLinkPriorityTable[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}},</span><br><span style="color: hsl(0, 100%, 40%);">- {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}},</span><br><span style="color: hsl(0, 100%, 40%);">- {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}},</span><br><span style="color: hsl(0, 100%, 40%);">- {VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}},</span><br><span style="color: hsl(0, 100%, 40%);">- {AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}},</span><br><span style="color: hsl(0, 100%, 40%);">- {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void writeglmsr(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = gl->lo;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = gl->hi;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(gl->desc_name, msr); // MSR - see table above</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void ShadowInit(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(gl->desc_name);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.lo == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- writeglmsr(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void SysmemInit(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- int sizembytes, sizebytes;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Figure out how much RAM is in the machine and allocate all to the</span><br><span style="color: hsl(0, 100%, 40%);">- * system. We will adjust for SMM now and Frame Buffer later.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- sizembytes = sizeram();</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes = sizembytes << 20;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes -= ((SMM_SIZE * 1024) + 1);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo</span><br><span style="color: hsl(0, 100%, 40%);">- The top 8 bits go into 0-7 of msr.hi. */</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes--;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes &= 0xfff00000;</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes |= 0x100; /* start at 1MB */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = sizebytes;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(gl->desc_name, msr); // MSR - see table above</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- gl->desc_name, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void SMMGL0Init(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- int sizebytes = sizeram() << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- long offset;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sizebytes -= (SMM_SIZE * 1024);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* calculate the Two's complement offset */</span><br><span style="color: hsl(0, 100%, 40%);">- offset = sizebytes - SMM_OFFSET;</span><br><span style="color: hsl(0, 100%, 40%);">- offset = (offset >> 12) & 0x000fffff;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = offset << 8 | gl->hi;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= SMM_OFFSET >> 24;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (SMM_OFFSET & 0x00ffffff) << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(gl->desc_name, msr); // MSR - See table above</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- gl->desc_name, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void SMMGL1Init(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s:\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = gl->hi;</span><br><span style="color: hsl(0, 100%, 40%);">- /* I don't think this is needed */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= 0xffffff00;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= (SMM_OFFSET >> 24);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (SMM_OFFSET & 0x00fff000) << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(gl->desc_name, msr); // MSR - See table above</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- gl->desc_name, msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void GLIUInit(struct gliutable *gl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- while (gl->desc_type != GL_END) {</span><br><span style="color: hsl(0, 100%, 40%);">- switch (gl->desc_type) {</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- /* For Unknown types: Write then read MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- writeglmsr(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- case SC_SHADOW: /* Check for a Shadow entry */</span><br><span style="color: hsl(0, 100%, 40%);">- ShadowInit(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- case R_SYSMEM: /* check for a SYSMEM entry */</span><br><span style="color: hsl(0, 100%, 40%);">- SysmemInit(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- case BMO_SMM: /* check for a SMM entry */</span><br><span style="color: hsl(0, 100%, 40%);">- SMMGL0Init(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- case BM_SMM: /* check for a SMM entry */</span><br><span style="color: hsl(0, 100%, 40%);">- SMMGL1Init(gl);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- gl++;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ************************************************************************** */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * GLPCIInit */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Set up GLPCI settings for reads/write into memory */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * R0: 0-640KB, */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * R1: 1MB - Top of System Memory */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * R2: SMM Memory */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * R3: Framebuffer? - not set up yet */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * R4: ?? */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Entry: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Exit: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Modified: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ************************************************************************** */</span><br><span style="color: hsl(0, 100%, 40%);">-static void GLPCIInit(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct gliutable *gl = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- int msrnum, enable_preempt, enable_cpu_override;</span><br><span style="color: hsl(0, 100%, 40%);">- int nic_grants_control, enable_bus_parking;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R0 - GLPCI settings for Conventional Memory space. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; /* 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |=</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_RC_LOWER_WC_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_RC0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R1 - GLPCI settings for SysMem space. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get systop from GLIU0 SYSTOP Descriptor */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gliu0table[i].desc_type == R_SYSMEM) {</span><br><span style="color: hsl(0, 100%, 40%);">- gl = &gliu0table[i];</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gl) {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long pah, pal;</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = gl->desc_name;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- /* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00</span><br><span style="color: hsl(0, 100%, 40%);">- * translates to a base of 0x00100000 and top of 0xffbf0000</span><br><span style="color: hsl(0, 100%, 40%);">- * base of 1M and top of around 256M</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- /* we have to create a page-aligned (4KB page) address for base and top */</span><br><span style="color: hsl(0, 100%, 40%);">- /* So we need a high page aligned address (pah) and low page aligned address (pal)</span><br><span style="color: hsl(0, 100%, 40%);">- * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);</span><br><span style="color: hsl(0, 100%, 40%);">- /* we have the page address. Now make it a page-aligned address */</span><br><span style="color: hsl(0, 100%, 40%);">- pah <<= 12;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pal = msr.lo << 12;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = pah;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = pal;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |=</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_RC_LOWER_WC_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo, msr.hi);</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_RC1;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* R2 - GLPCI settings for SMM space */</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi =</span><br><span style="color: hsl(0, 100%, 40%);">- ((SMM_OFFSET +</span><br><span style="color: hsl(0, 100%, 40%);">- (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi);</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_RC2;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* this is done elsewhere already, but it does no harm to do it more than once */</span><br><span style="color: hsl(0, 100%, 40%);">- /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x021212121; /* cache disabled and write serialized */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x021212121; /* cache disabled and write serialized */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_RCONF_A0_BF;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_RCONF_C0_DF;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_RCONF_E0_FF;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_A0_BF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_C0_DF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_E0_FF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x35353535;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set WSREQ */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = CPU_DM_CONFIG0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT; /* reduce to 1 for safe mode */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* we are ignoring the 5530 case for now, and perhaps forever. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* 553x NB Init */</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Arbiter setup */</span><br><span style="color: hsl(0, 100%, 40%);">- enable_preempt =</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- nic_grants_control =</span><br><span style="color: hsl(0, 100%, 40%);">- (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 <<</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_ARB_UPPER_H2_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_ARB;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= nic_grants_control;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_CTRL;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set GLPCI Latency Timer */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_CTRL;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GLPCI_SPARE */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_SPARE;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0x7;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |=</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ************************************************************************** */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * ClockGatingInit */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Enable Clock Gating. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Entry: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Exit: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * Modified: */</span><br><span style="color: hsl(0, 100%, 40%);">- /* * */</span><br><span style="color: hsl(0, 100%, 40%);">- /* ************************************************************************** */</span><br><span style="color: hsl(0, 100%, 40%);">-static void ClockGatingInit(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct msrinit *gating = ClockGatingDefault;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gating->msrnum != 0xffffffff; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(gating->msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= gating->msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= gating->msr.lo;</span><br><span style="color: hsl(0, 100%, 40%);">- /* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- gating->msrnum, msr.hi, msr.lo); */// GX3</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(gating->msrnum, msr); // MSR - See the table above</span><br><span style="color: hsl(0, 100%, 40%);">- gating += 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void GeodeLinkPriority(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct msrinit *prio = GeodeLinkPriorityTable;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; prio->msrnum != 0xffffffff; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(prio->msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= prio->msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0xfff;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= prio->msr.lo;</span><br><span style="color: hsl(0, 100%, 40%);">- /* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- prio->msrnum, msr.hi, msr.lo); */// GX3</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(prio->msrnum, msr); // MSR - See the table above</span><br><span style="color: hsl(0, 100%, 40%);">- prio += 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Get the GLIU0 shadow register settings</span><br><span style="color: hsl(0, 100%, 40%);">- * If the setShadow function is used then all shadow descriptors</span><br><span style="color: hsl(0, 100%, 40%);">- * will stay sync'ed.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static uint64_t getShadow(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_GLIU0_SHADOW);</span><br><span style="color: hsl(0, 100%, 40%);">- return (((uint64_t) msr.hi) << 32) | msr.lo;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set the cache RConf registers for the memory hole.</span><br><span style="color: hsl(0, 100%, 40%);">- * Keeps all cache shadow descriptors sync'ed.</span><br><span style="color: hsl(0, 100%, 40%);">- * This is part of the PCI lockup solution</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry: EDX:EAX is the shadow settings</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // ok this is whacky bit translation time.</span><br><span style="color: hsl(0, 100%, 40%);">- int bit;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t shadowByte;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr = { 0, 0 };</span><br><span style="color: hsl(0, 100%, 40%);">- shadowByte = (uint8_t) (shadowLo >> 16);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // load up D000 settings in edx.</span><br><span style="color: hsl(0, 100%, 40%);">- for (bit = 7; bit >= 4; bit--) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi <<= 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 1; // cache disable PCI/Shadow memory</span><br><span style="color: hsl(0, 100%, 40%);">- if (shadowByte & (1 << bit))</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x20; // write serialize PCI memory</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // load up C000 settings in eax.</span><br><span style="color: hsl(0, 100%, 40%);">- for (; bit >= 0; bit--) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo <<= 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 1; // cache disable PCI/Shadow memory</span><br><span style="color: hsl(0, 100%, 40%);">- if (shadowByte & (1 << bit))</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x20; // write serialize PCI memory</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_C0_DF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- shadowByte = (uint8_t) (shadowLo >> 24);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // load up F000 settings in edx.</span><br><span style="color: hsl(0, 100%, 40%);">- for (bit = 7; bit >= 4; bit--) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi <<= 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 1; // cache disable PCI/Shadow memory</span><br><span style="color: hsl(0, 100%, 40%);">- if (shadowByte & (1 << bit))</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x20; // write serialize PCI memory</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // load up E000 settings in eax.</span><br><span style="color: hsl(0, 100%, 40%);">- for (; bit >= 0; bit--) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo <<= 8;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 1; // cache disable PCI/Shadow memory</span><br><span style="color: hsl(0, 100%, 40%);">- if (shadowByte & (1 << bit))</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x20; // write serialize PCI memory</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_E0_FF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set the GLPCI registers for the memory hole.</span><br><span style="color: hsl(0, 100%, 40%);">- * Keeps all cache shadow descriptors sync'ed.</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry: EDX:EAX is the shadow settings</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// Set the Enable Register.</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLPCI_REN);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= 0xFFFF00FF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLPCI_REN, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.</span><br><span style="color: hsl(0, 100%, 40%);">- * Keeps all shadow descriptors sync'ed.</span><br><span style="color: hsl(0, 100%, 40%);">- * Entry: EDX:EAX is the shadow settings</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void setShadow(uint64_t shadowSettings)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct gliutable *pTable;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t shadowLo, shadowHi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- shadowLo = (uint32_t) shadowSettings;</span><br><span style="color: hsl(0, 100%, 40%);">- shadowHi = (uint32_t) (shadowSettings >> 32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setShadowRCONF(shadowHi, shadowLo);</span><br><span style="color: hsl(0, 100%, 40%);">- setShadowGLPCI(shadowHi, shadowLo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliutables[i]; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- for (pTable = gliutables[i]; pTable->desc_type != GL_END;</span><br><span style="color: hsl(0, 100%, 40%);">- pTable++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (pTable->desc_type == SC_SHADOW) {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(pTable->desc_name);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (uint32_t) shadowSettings;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |=</span><br><span style="color: hsl(0, 100%, 40%);">- ((uint32_t) (shadowSettings >> 32)) &</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0000FFFF;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(pTable->desc_name, msr); // MSR - See the table above</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void rom_shadow_settings(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t shadowSettings = getShadow();</span><br><span style="color: hsl(0, 100%, 40%);">- shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes</span><br><span style="color: hsl(0, 100%, 40%);">- shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF</span><br><span style="color: hsl(0, 100%, 40%);">- shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF</span><br><span style="color: hsl(0, 100%, 40%);">- setShadow(shadowSettings);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/***************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * L1Init</span><br><span style="color: hsl(0, 100%, 40%);">- * Set up RCONF_DEFAULT and any other RCONF registers needed</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * DEVRC_RCONF_DEFAULT:</span><br><span style="color: hsl(0, 100%, 40%);">- * ROMRC(63:56) = 04h ; write protect ROMBASE</span><br><span style="color: hsl(0, 100%, 40%);">- * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area</span><br><span style="color: hsl(0, 100%, 40%);">- * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.</span><br><span style="color: hsl(0, 100%, 40%);">- * SYSTOP(27:8) = top of system memory</span><br><span style="color: hsl(0, 100%, 40%);">- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-#define SYSMEM_RCONF_WRITETHROUGH 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define DEVRC_RCONF_DEFAULT 0x21ul</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMBASE_RCONF_DEFAULT 0xFFFC0000</span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMRC_RCONF_DEFAULT 0x25</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_L1_cache(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct gliutable *gl = NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t SysMemCacheProp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Locate SYSMEM entry in GLIU0table */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliu0table[i].desc_name != GL_END; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (gliu0table[i].desc_type == R_SYSMEM) {</span><br><span style="color: hsl(0, 100%, 40%);">- gl = &gliu0table[i];</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (gl == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0xCE); /* POST_RCONFInitError */</span><br><span style="color: hsl(0, 100%, 40%);">- while (1) ;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-// sysdescfound:</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(gl->desc_name);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the</span><br><span style="color: hsl(0, 100%, 40%);">- * top 8 bits go into 0-7 of edx.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Set Default SYSMEM region properties</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // NOT writethrough == writeback 8 (or ~8)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Set PCI space cache properties</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = (DEVRC_RCONF_DEFAULT >> 4); // setting is split betwwen hi and lo...</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (DEVRC_RCONF_DEFAULT << 28);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Set the ROMBASE. This is usually FFFC0000h</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |=</span><br><span style="color: hsl(0, 100%, 40%);">- (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Set ROMBASE cache properties.</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // now program RCONF_DEFAULT</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_DEFAULT, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.</span><br><span style="color: hsl(0, 100%, 40%);">- // Set to match system memory cache properties.</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_RCONF_DEFAULT);</span><br><span style="color: hsl(0, 100%, 40%);">- SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_RCONF_BYPASS);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo =</span><br><span style="color: hsl(0, 100%, 40%);">- (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_RCONF_BYPASS, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_L2_cache(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Instruction Memory Configuration register</span><br><span style="color: hsl(0, 100%, 40%);">- * set EBE bit, required when L2 cache is enabled</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_IM_CONFIG);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x400;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_IM_CONFIG, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Data Memory Subsystem Configuration register</span><br><span style="color: hsl(0, 100%, 40%);">- * set EVCTONRPL bit, required when L2 cache is enabled in victim mode</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_DM_CONFIG0);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x4000;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_DM_CONFIG0, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* invalidate L2 cache */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_BC_L2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable L2 cache */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x00;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x0f;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_BC_L2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "L2 cache enabled\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void setup_lx_cache(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- enable_L1_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_L2_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Make sure all INVD instructions are treated as WBINVD. We do this</span><br><span style="color: hsl(0, 100%, 40%);">- // because we've found some programs which require this behavior.</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CPU_DM_CONFIG0);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(CPU_DM_CONFIG0, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- x86_enable_cache();</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t restore_top_of_low_cacheable(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t systop;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_GLIU0_SYSMEM);</span><br><span style="color: hsl(0, 100%, 40%);">- systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);</span><br><span style="color: hsl(0, 100%, 40%);">- systop += 0x1000; /* 4K */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return systop;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/****************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-/* * northbridge_init_early */</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* * Core Logic initialization: Host bridge*/</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void northbridge_init_early(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enter %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; gliutables[i]; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- GLIUInit(gliutables[i]);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now that the descriptor to memory is set up. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* The memory controller needs one read to synch its lines before it can be used. */</span><br><span style="color: hsl(0, 100%, 40%);">- read32(zeroptr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- GeodeLinkPriority();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setup_lx_cache();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- rom_shadow_settings();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- GLPCIInit();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ClockGatingInit();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__ __volatile__("FINIT\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Exit %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c</span><br><span>deleted file mode 100644</span><br><span>index cb332ea..0000000</span><br><span>--- a/src/northbridge/amd/lx/pll_reset.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,82 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void lx_pll_reset(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msrGlcpSysRstpll;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_INIT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Configuring PLL.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- if (CONFIG_PLL_MANUAL_CONFIG) {</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_MANUAL);</span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Hold Count - how long we will sit in reset */</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- /*automatic configuration (straps) */</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_STRAP);</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo &=</span><br><span style="color: hsl(0, 100%, 40%);">- ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo |=</span><br><span style="color: hsl(0, 100%, 40%);">- (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo &=</span><br><span style="color: hsl(0, 100%, 40%);">- ~(RSTPPL_LOWER_COREBYPASS_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- RSTPPL_LOWER_MBBYPASS_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo |=</span><br><span style="color: hsl(0, 100%, 40%);">- RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use SWFLAGS to remember: "we've already been here" */</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* "reset the chip" value */</span><br><span style="color: hsl(0, 100%, 40%);">- msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* You should never get here..... The chip has reset. */</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_RESET_FAIL);</span><br><span style="color: hsl(0, 100%, 40%);">- die("CONFIGURING PLL FAILURE\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PLL configured.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned int GeodeLinkSpeed(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int speed;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLCP_SYS_RSTPLL);</span><br><span style="color: hsl(0, 100%, 40%);">- speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;</span><br><span style="color: hsl(0, 100%, 40%);">- if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++speed;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return (speed);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c</span><br><span>deleted file mode 100644</span><br><span>index 8de85a3..0000000</span><br><span>--- a/src/northbridge/amd/lx/raminit.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,775 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <spd.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stddef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <southbridge/amd/cs5536/cs5536.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "raminit.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "northbridge.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const unsigned char NumColAddr[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void banner(const char *s)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, " * %s\n", s);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void __noreturn hcf(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIE\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* this guarantees we flush the UART fifos (if any) and also</span><br><span style="color: hsl(0, 100%, 40%);">- * ensures that things, in general, keep going so no debug output</span><br><span style="color: hsl(0, 100%, 40%);">- * is lost</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- while (1)</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "%c", 0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void auto_size_dimm(unsigned int dimm)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t dimm_setting;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t dimm_size;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("Check present");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check that we have a dimm */</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("MODBANKS");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Field: Module Banks per DIMM */</span><br><span style="color: hsl(0, 100%, 40%);">- /* EEPROM byte usage: (5) Number of DIMM Banks */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "Number of module banks not compatible\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_BANK_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- banner("FIELDBANKS");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Field: Banks per SDRAM device */</span><br><span style="color: hsl(0, 100%, 40%);">- /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "Number of device banks not compatible\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_BANK_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- banner("SPDNUMROWS");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*; Field: DIMM size</span><br><span style="color: hsl(0, 100%, 40%);">- *; EEPROM byte usage: (3) Number of Row Addresses</span><br><span style="color: hsl(0, 100%, 40%);">- *; (4) Number of Column Addresses</span><br><span style="color: hsl(0, 100%, 40%);">- *; (5) Number of DIMM Banks</span><br><span style="color: hsl(0, 100%, 40%);">- *; (31) Module Bank Density</span><br><span style="color: hsl(0, 100%, 40%);">- *; Size = Module Density * Module Banks</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)</span><br><span style="color: hsl(0, 100%, 40%);">- || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_UNSUPPORTED_DIMM);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- banner("SPDBANKDENSITY");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);</span><br><span style="color: hsl(0, 100%, 40%);">- banner("DIMMSIZE");</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Module Density * Module Banks */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */</span><br><span style="color: hsl(0, 100%, 40%);">- banner("BEFORT CTZ");</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_size = __builtin_ctz(dimm_size);</span><br><span style="color: hsl(0, 100%, 40%);">- banner("TEST DIMM SIZE > 8");</span><br><span style="color: hsl(0, 100%, 40%);">- if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_DENSITY_DIMM);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- banner("PAGESIZE");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*; Field: PAGE size</span><br><span style="color: hsl(0, 100%, 40%);">-*; EEPROM byte usage: (4) Number of Column Addresses</span><br><span style="color: hsl(0, 100%, 40%);">-*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-*; But this really works by magic.</span><br><span style="color: hsl(0, 100%, 40%);">-*;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address</span><br><span style="color: hsl(0, 100%, 40%);">-*;that MC generates, here is how the MC assigns the pa onto the ma pins:</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-*;ma 12 11 10 09 08 07 06 05 04 03 02 01 00</span><br><span style="color: hsl(0, 100%, 40%);">-*;-------------------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)</span><br><span style="color: hsl(0, 100%, 40%);">-*; *AP = autoprecharge bit</span><br><span style="color: hsl(0, 100%, 40%);">-*</span><br><span style="color: hsl(0, 100%, 40%);">-*;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),</span><br><span style="color: hsl(0, 100%, 40%);">-*;so lower 3 address bits are dont_cares.So from the table above,</span><br><span style="color: hsl(0, 100%, 40%);">-*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h),</span><br><span style="color: hsl(0, 100%, 40%);">-*;it adds 3 to get 10, then does 2^10 = 1K. Get it?*/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];</span><br><span style="color: hsl(0, 100%, 40%);">- banner("MAXCOLADDR");</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte > MAX_COL_ADDR) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM page size not compatible\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_SET_PAGE);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- banner(">12address test");</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte -= 7;</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte > 5) { /* if the value is above 6 it means > 12 address lines */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = 7; /* which means > 32k so set to disabled */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("RDMSR CF07");</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- banner("WRMSR CF07");</span><br><span style="color: hsl(0, 100%, 40%);">- if (dimm == DIMM0) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= 0xFFFF0000;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= dimm_setting;</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= 0x0000FFFF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= dimm_setting << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF07_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- banner("ALL DONE");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void checkDDRMax(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte0, spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t speed;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PC133 identifier */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* I don't think you need this check.</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_MEM_FAIL);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- } */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use the slowest DIMM */</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn SPD ns time into MHz. Check what the asm does to this math. */</span><br><span style="color: hsl(0, 100%, 40%);">- speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* current speed > max speed? */</span><br><span style="color: hsl(0, 100%, 40%);">- if (GeodeLinkSpeed() > speed) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PLL_MEM_FAIL);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_refresh_rate(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte0, spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t rate0, rate1;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 &= 0xF;</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 > 5) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- rate0 = REF_RATE[spd_byte0];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 &= 0xF;</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 > 5) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- rate1 = REF_RATE[spd_byte1];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use the faster rate (lowest number) */</span><br><span style="color: hsl(0, 100%, 40%);">- if (rate0 > rate1) {</span><br><span style="color: hsl(0, 100%, 40%);">- rate0 = rate1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)</span><br><span style="color: hsl(0, 100%, 40%);">- << CF07_LOWER_REF_INT_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF07_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static u8 getcasmap(u32 dimm, u16 glspeed)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 dimm_speed;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 spd_byte, casmap, casmap_shift = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /************************** DIMM0 **********************************/</span><br><span style="color: hsl(0, 100%, 40%);">- casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);</span><br><span style="color: hsl(0, 100%, 40%);">- if (casmap != 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* IF -.5 timing is supported, check -.5 timing > GeodeLink */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn SPD ns time into MHz. Check what the asm does to this math. */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));</span><br><span style="color: hsl(0, 100%, 40%);">- if (dimm_speed >= glspeed) {</span><br><span style="color: hsl(0, 100%, 40%);">- casmap_shift = 1; /* -.5 is a shift of 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* IF -1 timing is supported, check -1 timing > GeodeLink */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte != 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Turn SPD ns time into MHz. Check what the asm does to this math. */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));</span><br><span style="color: hsl(0, 100%, 40%);">- if (dimm_speed >= glspeed) {</span><br><span style="color: hsl(0, 100%, 40%);">- casmap_shift = 2; /* -1 is a shift of 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- casmap_shift = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* set the casmap based on the shift to limit possible CAS settings */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = 31 - __builtin_clz((uint32_t) casmap);</span><br><span style="color: hsl(0, 100%, 40%);">- /* just want bits in the lower byte since we have to cast to a 32 */</span><br><span style="color: hsl(0, 100%, 40%);">- casmap &= 0xFF << (spd_byte - casmap_shift);</span><br><span style="color: hsl(0, 100%, 40%);">- } else { /* No DIMM */</span><br><span style="color: hsl(0, 100%, 40%);">- casmap = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return casmap;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void setCAS(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-/*;*****************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">-;*</span><br><span style="color: hsl(0, 100%, 40%);">-;* setCAS</span><br><span style="color: hsl(0, 100%, 40%);">-;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency</span><br><span style="color: hsl(0, 100%, 40%);">-;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5</span><br><span style="color: hsl(0, 100%, 40%);">-;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1</span><br><span style="color: hsl(0, 100%, 40%);">-;*</span><br><span style="color: hsl(0, 100%, 40%);">-;* The CAS setting is based on the information provided in each DIMMs SPD.</span><br><span style="color: hsl(0, 100%, 40%);">-;* The speed at which a DIMM can run is described relative to the slowest</span><br><span style="color: hsl(0, 100%, 40%);">-;* CAS the DIMM supports. Each speed for the relative CAS settings is</span><br><span style="color: hsl(0, 100%, 40%);">-;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink</span><br><span style="color: hsl(0, 100%, 40%);">-;* speed, the CAS setting is removed from the list of good settings for</span><br><span style="color: hsl(0, 100%, 40%);">-;* the DIMM. This is done for both DIMMs and the lists are compared to</span><br><span style="color: hsl(0, 100%, 40%);">-;* find the lowest common CAS latency setting. If there are no CAS settings</span><br><span style="color: hsl(0, 100%, 40%);">-;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.</span><br><span style="color: hsl(0, 100%, 40%);">-;*</span><br><span style="color: hsl(0, 100%, 40%);">-;* Entry:</span><br><span style="color: hsl(0, 100%, 40%);">-;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.</span><br><span style="color: hsl(0, 100%, 40%);">-;* Destroys: We really use everything !</span><br><span style="color: hsl(0, 100%, 40%);">-;*****************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t glspeed;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte, casmap0, casmap1;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- glspeed = GeodeLinkSpeed();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- casmap0 = getcasmap(DIMM0, glspeed);</span><br><span style="color: hsl(0, 100%, 40%);">- casmap1 = getcasmap(DIMM1, glspeed);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /********************* CAS_LAT MAP COMPARE ***************************/</span><br><span style="color: hsl(0, 100%, 40%);">- if (casmap0 == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = CASDDR[__builtin_ctz(casmap1)];</span><br><span style="color: hsl(0, 100%, 40%);">- } else if (casmap1 == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = CASDDR[__builtin_ctz(casmap0)];</span><br><span style="color: hsl(0, 100%, 40%);">- } else if ((casmap0 &= casmap1)) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = CASDDR[__builtin_ctz(casmap0)];</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_DIFF_DIMMS);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF8F_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF8F_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_latencies(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t memspeed, dimm_setting;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte0, spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- memspeed = GeodeLinkSpeed() / 2;</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MC_CF8F setup */</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRAS */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = (spd_byte0 * memspeed) / 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- if (((spd_byte0 * memspeed) % 1000)) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRP */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRCD */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRRD */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- if ((((spd_byte0 >> 2) * memspeed) % 1000)) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRC = tRP + tRAS */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +</span><br><span style="color: hsl(0, 100%, 40%);">- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))</span><br><span style="color: hsl(0, 100%, 40%);">- << CF8F_LOWER_ACT2ACTREF_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF8F_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= 0xF00000FF;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= dimm_setting;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= CF8F_UPPER_REORDER_DIS_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF8F_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MC_CF1017 setup */</span><br><span style="color: hsl(0, 100%, 40%);">- /* tRFC */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 < spd_byte1) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = (spd_byte0 * memspeed) / 1000;</span><br><span style="color: hsl(0, 100%, 40%);">- if (((spd_byte0 * memspeed) % 1000)) {</span><br><span style="color: hsl(0, 100%, 40%);">- ++spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF1017_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= dimm_setting;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF1017_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200MHz mem) other wise it stay default(1) */</span><br><span style="color: hsl(0, 100%, 40%);">- if (memspeed > 198) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF1017_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF1017_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_extended_mode_registers(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte0, spd_byte1;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte0 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte0 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 == 0xFF) {</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte1 &= spd_byte0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 & 1) { /* Drive Strength Control */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_EMR_DRV_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- if (spd_byte1 & 2) { /* FET Control */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_EMR_QFC_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF07_DATA, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#undef TLA_MEMORY_DEBUG</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef TLA_MEMORY_DEBUG</span><br><span style="color: hsl(0, 100%, 40%);">-static void EnableMTest(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLCP_DELAY_CONTROLS);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~(7 << 20); /* clear bits 54:52 */</span><br><span style="color: hsl(0, 100%, 40%);">- if (GeodeLinkSpeed() < 200) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 2 << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLCP_DELAY_CONTROLS, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CFCLK_DBUG);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |=</span><br><span style="color: hsl(0, 100%, 40%);">- CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |</span><br><span style="color: hsl(0, 100%, 40%);">- CFCLK_UPPER_MTST_RBEX_EN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CFCLK_DBUG, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "Enabled MTest for TLA debug\n");</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_set_registers(const struct mem_controller *ctrl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Timing Control */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF1017_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- if (GeodeLinkSpeed() < 334) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Refresh Staggering */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0xF0;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Memory Interleave: Set HOI here otherwise default is LOI */</span><br><span style="color: hsl(0, 100%, 40%);">- /* msrnum = MC_CF8F_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= CF8F_UPPER_HOI_LOI_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr); */</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_set_spd_registers(const struct mem_controller *ctrl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t spd_byte;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("sdram_set_spd_register");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP); // post_70h</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);</span><br><span style="color: hsl(0, 100%, 40%);">- banner("Check DIMM 0");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check DIMM is not Register and not Buffered DIMMs. */</span><br><span style="color: hsl(0, 100%, 40%);">- if ((spd_byte != 0xFF) && (spd_byte & 3)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_UNSUPPORTED_DIMM);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- banner("Check DIMM 1");</span><br><span style="color: hsl(0, 100%, 40%);">- spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((spd_byte != 0xFF) && (spd_byte & 3)) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_UNSUPPORTED_DIMM);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP2); // post_72h</span><br><span style="color: hsl(0, 100%, 40%);">- banner("Check DDR MAX");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check that the memory is not overclocked. */</span><br><span style="color: hsl(0, 100%, 40%);">- checkDDRMax();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Size the DIMMS */</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP3); // post_73h</span><br><span style="color: hsl(0, 100%, 40%);">- banner("AUTOSIZE DIMM 0");</span><br><span style="color: hsl(0, 100%, 40%);">- auto_size_dimm(DIMM0);</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP4); // post_74h</span><br><span style="color: hsl(0, 100%, 40%);">- banner("AUTOSIZE DIMM 1");</span><br><span style="color: hsl(0, 100%, 40%);">- auto_size_dimm(DIMM1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set CAS latency */</span><br><span style="color: hsl(0, 100%, 40%);">- banner("set cas latency");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP5); // post_75h</span><br><span style="color: hsl(0, 100%, 40%);">- setCAS();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set all the other latencies here (tRAS, tRP....) */</span><br><span style="color: hsl(0, 100%, 40%);">- banner("set all latency");</span><br><span style="color: hsl(0, 100%, 40%);">- set_latencies();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Extended Mode Registers */</span><br><span style="color: hsl(0, 100%, 40%);">- banner("set emrs");</span><br><span style="color: hsl(0, 100%, 40%);">- set_extended_mode_registers();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("set ref rate");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Memory Refresh Rate */</span><br><span style="color: hsl(0, 100%, 40%);">- set_refresh_rate();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence</span><br><span style="color: hsl(0, 100%, 40%);">- * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_enable(int controllers, const struct mem_controller *ctrl)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t i, msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*********************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">-;* Turn on MC/DIMM interface per JEDEC</span><br><span style="color: hsl(0, 100%, 40%);">-;* 1) Clock stabilizes > 200us</span><br><span style="color: hsl(0, 100%, 40%);">-;* 2) Assert CKE</span><br><span style="color: hsl(0, 100%, 40%);">-;* 3) Precharge All to put all banks into an idles state</span><br><span style="color: hsl(0, 100%, 40%);">-;* 4) EMRS to enable DLL</span><br><span style="color: hsl(0, 100%, 40%);">-;* 6) MRS w/ memory config & reset DLL set</span><br><span style="color: hsl(0, 100%, 40%);">-;* 7) Wait 200 clocks (2us)</span><br><span style="color: hsl(0, 100%, 40%);">-;* 8) Precharge All and 2 Auto refresh</span><br><span style="color: hsl(0, 100%, 40%);">-;* 9) MRS w/ memory config & reset DLL clear</span><br><span style="color: hsl(0, 100%, 40%);">-;* 8) DDR SDRAM ready for normal operation</span><br><span style="color: hsl(0, 100%, 40%);">-;********************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_ENABLE); // post_76h</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef TLA_MEMORY_DEBUG</span><br><span style="color: hsl(0, 100%, 40%);">- /* Only enable MTest for TLA memory debug */</span><br><span style="color: hsl(0, 100%, 40%);">- EnableMTest();</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* If both Page Size = "Not Installed" we have a problems and should halt. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==</span><br><span style="color: hsl(0, 100%, 40%);">- ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_EMERG, "No memory in the system\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(ERROR_NO_DIMMS);</span><br><span style="color: hsl(0, 100%, 40%);">- hcf();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set CKEs */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Force Precharge All on next command, EMRS */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear Force Precharge All */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MRS Reset DLL - set */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Wait 2 PORT61 ticks. between 15us and 30us */</span><br><span style="color: hsl(0, 100%, 40%);">- /* This would be endless if the timer is stuck. */</span><br><span style="color: hsl(0, 100%, 40%);">- while ((inb(0x61))); /* find the first edge */</span><br><span style="color: hsl(0, 100%, 40%);">- while (!(~inb(0x61)));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Force Precharge All on the next command, auto-refresh */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Manually AUTO refresh #1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_REF_TEST_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CF07_LOWER_REF_TEST_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear Force Precharge All */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Manually AUTO refresh */</span><br><span style="color: hsl(0, 100%, 40%);">- /* The MC should insert the right delay between the refreshes */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_REF_TEST_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CF07_LOWER_REF_TEST_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* MRS Reset DLL - clear */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF07_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= CF07_LOWER_PROG_DRAM_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Allow MC to tristate during idle cycles with MTEST OFF */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CFCLK_DBUG;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MC_CF07_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==</span><br><span style="color: hsl(0, 100%, 40%);">- (7 << CF07_UPPER_D1_PSZ_SHIFT)) {</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLCP_DELAY_CONTROLS;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set PMode0 Sensitivity Counter */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; /* pmode 0 = 0 most aggressive */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x200; /* pmode 1 = 200h */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MC_CF_PMCTR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set PMode1 Up delay enable */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MC_CF1017_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (209 << 8); /* bits[15:8] = 209 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- banner("DRAM controller init done.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_MEM_SETUP_GOOD); //0x7E</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* make sure there is nothing stale in the cache */</span><br><span style="color: hsl(0, 100%, 40%);">- /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The RAM dll needs a write to lock on so generate a few dummy writes */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Note: The descriptor needs to be enabled to point at memory */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < 5; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(zeroptr + i, i);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* SWAPSiF for PBZ 4112 (Errata 34) */</span><br><span style="color: hsl(0, 100%, 40%);">- /* check for failed DLL settings now that we have done a memory write. */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLCP_DELAY_CONTROLS;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((msr.lo & 0x7FF) == 0x104) {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* If you had it you would need to clear out the fail boot count flag */</span><br><span style="color: hsl(0, 100%, 40%);">- /* (depending on where it counts from etc). */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The reset we are about to perform clears the PM_SSC register in the */</span><br><span style="color: hsl(0, 100%, 40%);">- /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */</span><br><span style="color: hsl(0, 100%, 40%);">- /* it would do a normal boot */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reset the system */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = MDD_SOFT_RESET;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 1;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "RAM DLL lock\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h</span><br><span>deleted file mode 100644</span><br><span>index a1c0fcd..0000000</span><br><span>--- a/src/northbridge/amd/lx/raminit.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,37 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef RAMINIT_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define RAMINIT_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIMM_SOCKETS 2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct mem_controller {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t channel0[DIMM_SOCKETS];</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_set_registers(const struct mem_controller *ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_set_spd_registers(const struct mem_controller *ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_enable(int controllers, const struct mem_controller *ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void sdram_initialize(int controllers, const struct mem_controller *ctrl);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* mainboard specific */</span><br><span style="color: hsl(0, 100%, 40%);">-int spd_read_byte(unsigned int device, unsigned int address);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig</span><br><span>deleted file mode 100644</span><br><span>index 6b06c33..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/Kconfig</span><br><span>+++ /dev/null</span><br><span>@@ -1,27 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">-## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">- bool</span><br><span style="color: hsl(0, 100%, 40%);">- select UDELAY_TSC</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-if SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-config NO_EARLY_SMBUS</span><br><span style="color: hsl(0, 100%, 40%);">- def_bool n</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- Skip the CS5536 early SMBUS initialization.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc</span><br><span>deleted file mode 100644</span><br><span>index 4bd88ac..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/Makefile.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,27 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">-## it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">-## published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">-## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">-## GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">-##</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += early_smbus.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += early_setup.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += cs5536.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += ide.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += pirq.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += smbus.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += smbus.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-endif</span><br><span>diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h</span><br><span>deleted file mode 100644</span><br><span>index f5411c0..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/chip.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">-#define _SOUTHBRIDGE_AMD_CS5536</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_UNWANTED_VPCI 8 /* increase if needed */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct southbridge_amd_cs5536_config {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char com1_enable; /* enable COM1 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int com1_address; /* e.g. 0x3F8 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int com1_irq; /* e.g. 4 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char com2_enable; /* enable COM2 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int com2_address; /* e.g. 0x2F8 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int com2_irq; /* e.g. 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _SOUTHBRIDGE_AMD_CS5536 */</span><br><span>diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c</span><br><span>deleted file mode 100644</span><br><span>index 956994d..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/cs5536.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,714 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/ioapic.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/smbus.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdint.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/isa-dma.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <pc80/i8259.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/vr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <stdlib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "cs5536.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "smbus.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct msrinit {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Master Configuration Register for Bus Masters.*/</span><br><span style="color: hsl(0, 100%, 40%);">-static struct msrinit SB_MASTER_CONF_TABLE[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},</span><br><span style="color: hsl(0, 100%, 40%);">- {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},</span><br><span style="color: hsl(0, 100%, 40%);">- {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},</span><br><span style="color: hsl(0, 100%, 40%);">- {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}},</span><br><span style="color: hsl(0, 100%, 40%);">- {0, {0, 0}}</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* 5536 Clock Gating*/</span><br><span style="color: hsl(0, 100%, 40%);">-static struct msrinit CS5536_CLOCK_GATING_TABLE[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* MSR Setting*/</span><br><span style="color: hsl(0, 100%, 40%);">- {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},</span><br><span style="color: hsl(0, 100%, 40%);">- {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */</span><br><span style="color: hsl(0, 100%, 40%);">- {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},</span><br><span style="color: hsl(0, 100%, 40%);">- {0, {0, 0}}</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct acpiinit {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 ioreg;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 regdata;</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct acpiinit acpi_init_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x00, 0x01000000},</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x08, 0},</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x0C, 0},</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x1C, 0},</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},</span><br><span style="color: hsl(0, 100%, 40%);">- {ACPI_IO_BASE + 0x00, 0x0000FFFF},</span><br><span style="color: hsl(0, 100%, 40%);">- {PMS_IO_BASE + PM_SCLK, 0x000000E00},</span><br><span style="color: hsl(0, 100%, 40%);">- {PMS_IO_BASE + PM_SED, 0x000004601},</span><br><span style="color: hsl(0, 100%, 40%);">- {PMS_IO_BASE + PM_SIDD, 0x000008C02},</span><br><span style="color: hsl(0, 100%, 40%);">- {PMS_IO_BASE + PM_WKD, 0x0000000A0},</span><br><span style="color: hsl(0, 100%, 40%);">- {PMS_IO_BASE + PM_WKXD, 0x0000000A0},</span><br><span style="color: hsl(0, 100%, 40%);">- {0, 0}</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct FLASH_DEVICE {</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char fType; /* Flash type: NOR or NAND */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char fInterface; /* Flash interface: I/O or Memory */</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long fMask; /* Flash size/mask */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct FLASH_DEVICE FlashInitTable[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static u32 FlashPort[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_LBAR_FLSH0,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_LBAR_FLSH1,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_LBAR_FLSH2,</span><br><span style="color: hsl(0, 100%, 40%);">- MDD_LBAR_FLSH3</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* * pmChipsetInit*/</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* * Program ACPI LBAR and initialize ACPI registers.*/</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void pmChipsetInit(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u32 val = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 port;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- port = (PMS_IO_BASE + 0x010);</span><br><span style="color: hsl(0, 100%, 40%);">- val = 0x0E00; /* 1ms */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, port);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PM_WKXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make sure bits[3:0]=0000b to clear the */</span><br><span style="color: hsl(0, 100%, 40%);">- /* saved Sx state */</span><br><span style="color: hsl(0, 100%, 40%);">- port = (PMS_IO_BASE + 0x034);</span><br><span style="color: hsl(0, 100%, 40%);">- val = 0x0A0; /* 5ms */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, port);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PM_WKD */</span><br><span style="color: hsl(0, 100%, 40%);">- port = (PMS_IO_BASE + 0x030);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, port);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PM_SED */</span><br><span style="color: hsl(0, 100%, 40%);">- port = (PMS_IO_BASE + 0x014);</span><br><span style="color: hsl(0, 100%, 40%);">- val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, port);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PM_SIDD */</span><br><span style="color: hsl(0, 100%, 40%);">- port = (PMS_IO_BASE + 0x020);</span><br><span style="color: hsl(0, 100%, 40%);">- val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, port);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/***************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * ChipsetFlashSetup</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Flash LBARs need to be setup before VSA init so the PCI BARs have</span><br><span style="color: hsl(0, 100%, 40%);">- * correct size info. Call this routine only if flash needs to be</span><br><span style="color: hsl(0, 100%, 40%);">- * configured (don't call it if you want IDE).</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- **************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void ChipsetFlashSetup(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- int numEnabled = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n");</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < FlashInitTableLen; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Enable CS%d\n", i);</span><br><span style="color: hsl(0, 100%, 40%);">- /* we need to configure the memory/IO mask */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(FlashPort[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0; /* start with the "enabled" bit clear */</span><br><span style="color: hsl(0, 100%, 40%);">- if (FlashInitTable[i].fType == FLASH_TYPE_NAND)</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x00000002;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~0x00000002;</span><br><span style="color: hsl(0, 100%, 40%);">- if (FlashInitTable[i].fInterface == FLASH_IF_MEM)</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= 0x00000004;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= ~0x00000004;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= FlashInitTable[i].fMask;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(FlashPort[i], msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* now write-enable the device */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_NORF_CNTRL);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (1 << i);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi, msr.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_NORF_CNTRL, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* update the number enabled */</span><br><span style="color: hsl(0, 100%, 40%);">- numEnabled++;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* * enable_ide_nand_flash_header */</span><br><span style="color: hsl(0, 100%, 40%);">-/* Run after VSA init to enable the flash PCI device header */</span><br><span style="color: hsl(0, 100%, 40%);">-/* **/</span><br><span style="color: hsl(0, 100%, 40%);">-/* ***************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_ide_nand_flash_header(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Tell VSA to use FLASH PCI header. Not IDE header. */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0x80007A40, 0xCF8);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0xDEADBEEF, 0xCFC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define RTC_CENTURY 0x32</span><br><span style="color: hsl(0, 100%, 40%);">-#define RTC_DOMA 0x3D</span><br><span style="color: hsl(0, 100%, 40%);">-#define RTC_MONA 0x3E</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(struct southbridge_amd_cs5536_config *sb)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->lpc_serirq_enable) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = sb->lpc_serirq_enable;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_IRQM_LPC, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->lpc_serirq_polarity) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = sb->lpc_serirq_polarity << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LPC_SIRQ, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Allow DMA from LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_DMA_MAP);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0x7777;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_DMA_MAP, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the RTC/CMOS century byte at address 32h */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_RTC_CENTURY_OFFSET);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = RTC_CENTURY;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_RTC_CENTURY_OFFSET, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the RTC/CMOS day of month and month alarms */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_RTC_DOMA_IND);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = RTC_DOMA;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_RTC_DOMA_IND, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_RTC_MONA_IND);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = RTC_MONA;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_RTC_MONA_IND, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cmos_init(0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- isa_dma_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Depending on settings in the config struct, enable COM1 or COM2 or both.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * If the enable is NOT set, the UARTs are explicitly disabled, which is</span><br><span style="color: hsl(0, 100%, 40%);">- * required if (e.g.) there is a Super I/O attached that does COM1 or COM2.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * @param sb Southbridge config structure.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void uarts_init(struct southbridge_amd_cs5536_config *sb)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 addr = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 gpio_addr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_addr &= ~1; /* Clear I/O bit */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* This could be extended to support IR modes. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* COM1 */</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->com1_enable) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: enable COM1\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the address. */</span><br><span style="color: hsl(0, 100%, 40%);">- switch (sb->com1_address) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x3F8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 7;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x3E8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x2F8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x2E8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= addr << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the IRQ. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_YHIGH);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= sb->com1_irq << 24;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_IRQM_YHIGH, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO8 - UART1_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Output Enable (0x4) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: OUTAUX1 Select (0x10) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO9 - UART1_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Input Enable (0x20) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: INAUX1 Select (0x34) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: GPIO 8 + 9 Pull Up (0x18) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_8_SET | GPIOL_9_SET,</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_addr + GPIOL_PULLUP_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable COM1.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 1 = device enable</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 4 = allow access to the upper banks</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (1 << 4) | (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reset and disable COM1. */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: disable COM1\n");</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_UART1_CONF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 1; /* Reset */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; /* Disabled */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the IRQ. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0xF << 16);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* COM2 */</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->com2_enable) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: enable COM2\n");</span><br><span style="color: hsl(0, 100%, 40%);">- switch (sb->com2_address) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x3F8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 7;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x3E8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x2F8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 0x2E8:</span><br><span style="color: hsl(0, 100%, 40%);">- addr = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= addr << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the IRQ. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_IRQM_YHIGH);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= sb->com2_irq << 28;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_IRQM_YHIGH, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: set COM2 irq\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO3 - UART2_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Input Enable (0x20) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: INAUX1 Select (0x34) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO4 - UART2_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Output Enable (0x4) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: set output enable\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: OUTAUX1 Select (0x10) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: GPIO 3 + 4 Pull Up (0x18) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET | GPIOL_4_SET,</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_addr + GPIOL_PULLUP_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: set pullup COM2\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable COM2.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 1 = device enable</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 4 = allow access to the upper banks</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (1 << 4) | (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: COM2 enabled\n");</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "uarts_init: disable COM2\n");</span><br><span style="color: hsl(0, 100%, 40%);">- /* Reset and disable COM2. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_UART2_CONF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 1; /* Reset */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; /* Disabled */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the IRQ. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~(0xF << 20);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define HCCPARAMS 0x08</span><br><span style="color: hsl(0, 100%, 40%);">-#define IPREG04 0xA0</span><br><span style="color: hsl(0, 100%, 40%);">- #define USB_HCCPW_SET (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define UOCCAP 0x00</span><br><span style="color: hsl(0, 100%, 40%);">- #define APU_SET (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define UOCMUX 0x04</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMUX_HOST 0x02</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMUX_DEVICE 0x03</span><br><span style="color: hsl(0, 100%, 40%);">- #define PUEN_SET (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define UDCDEVCTL 0x404</span><br><span style="color: hsl(0, 100%, 40%);">- #define UDC_SD_SET (1 << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define UOCCTL 0x0C</span><br><span style="color: hsl(0, 100%, 40%);">- #define PADEN_SET (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- void *bar;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Serial Short Detect Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(USB2_SB_GLD_MSR_CONF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi |= USB2_UPPER_SSDEN_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(USB2_SB_GLD_MSR_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* write to clear diag register */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Make HCCPARAMS writable */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* ; EECP=50h, IST=01h, ASPC=1 */</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + HCCPARAMS, 0x00005012);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Host or Device? */</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_USBP4_device) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Overcurrent configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_USBP4_overcurrent) {</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCCAP, read32(bar + UOCCAP)</span><br><span style="color: hsl(0, 100%, 40%);">- | sb->enable_USBP4_overcurrent);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,</span><br><span style="color: hsl(0, 100%, 40%);">- * then perform the following sequence:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * - set SD bit in DEVCTRL udc register</span><br><span style="color: hsl(0, 100%, 40%);">- * - set PADEN (former OTGPADEN) bit in uoc register</span><br><span style="color: hsl(0, 100%, 40%);">- * - set APU bit in uoc register */</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_USBP4_device) {</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- bar = (void *)pci_read_config32(dev,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UDCDEVCTL,</span><br><span style="color: hsl(0, 100%, 40%);">- read32(bar + UDCDEVCTL) | UDC_SD_SET);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- bar = (void *)pci_read_config32(dev,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable virtual PCI UDC and OTG headers */</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_UDC, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, 0x7C, 0xDEADBEEF);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_OTG, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, 0x7C, 0xDEADBEEF);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/****************************************************************************</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * ChipsetInit</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Called from northbridge init (Pre-VSA).</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- ****************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">-void chipsetinit(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 msrnum;</span><br><span style="color: hsl(0, 100%, 40%);">- struct southbridge_amd_cs5536_config *sb;</span><br><span style="color: hsl(0, 100%, 40%);">- struct msrinit *csi;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, PCI_DEVFN(0xf, 0));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "CS5536 not found.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!sb) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "CS5536 configuration not found.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(P80_CHIPSET_INIT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* we hope NEVER to be in coreboot when S3 resumes</span><br><span style="color: hsl(0, 100%, 40%);">- if (! IsS3Resume()) */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- struct acpiinit *aci = acpi_init_table;</span><br><span style="color: hsl(0, 100%, 40%);">- for (; aci->ioreg; aci++) {</span><br><span style="color: hsl(0, 100%, 40%);">- outl(aci->regdata, aci->ioreg);</span><br><span style="color: hsl(0, 100%, 40%);">- inl(aci->ioreg);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pmChipsetInit();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set hd IRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Allow IO read and writes during a ATA DMA operation. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* This could be done in the HD ROM but do it here for easier debugging. */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = ATA_SB_GLD_MSR_ERR;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0x100;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Post Primary IDE. */</span><br><span style="color: hsl(0, 100%, 40%);">- msrnum = GLPCI_SB_CTRL;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(msrnum);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= GLPCI_CRTL_PPIDE_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(msrnum, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- csi = SB_MASTER_CONF_TABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- for (; csi->msrnum; csi++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = csi->msr.lo;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = csi->msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(csi->msrnum, msr); // MSR - see table above</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Flash BAR size Setup */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "%sDoing ChipsetFlashSetup()\n",</span><br><span style="color: hsl(0, 100%, 40%);">- sb->enable_ide_nand_flash == 1 ? "" : "Not ");</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_ide_nand_flash == 1)</span><br><span style="color: hsl(0, 100%, 40%);">- ChipsetFlashSetup();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set up Hardware Clock Gating */</span><br><span style="color: hsl(0, 100%, 40%);">- /* */</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- csi = CS5536_CLOCK_GATING_TABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- for (; csi->msrnum; csi++) {</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = csi->msr.lo;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = csi->msr.hi;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(csi->msrnum, msr); // MSR - see table above</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct southbridge_amd_cs5536_config *sb =</span><br><span style="color: hsl(0, 100%, 40%);">- (struct southbridge_amd_cs5536_config *)dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * struct device *gpiodev;</span><br><span style="color: hsl(0, 100%, 40%);">- * unsigned short gpiobase = MDD_GPIO;</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "cs5536: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!sb) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "CS5536 configuration not found.\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- setup_i8259();</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_init(sb);</span><br><span style="color: hsl(0, 100%, 40%);">- uarts_init(sb);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_gpio_int_route) {</span><br><span style="color: hsl(0, 100%, 40%);">- vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,</span><br><span style="color: hsl(0, 100%, 40%);">- (sb->enable_gpio_int_route & 0xFFFF));</span><br><span style="color: hsl(0, 100%, 40%);">- vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,</span><br><span style="color: hsl(0, 100%, 40%);">- (sb->enable_gpio_int_route >> 16));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__,</span><br><span style="color: hsl(0, 100%, 40%);">- sb->enable_ide_nand_flash);</span><br><span style="color: hsl(0, 100%, 40%);">- if (sb->enable_ide_nand_flash == 1) {</span><br><span style="color: hsl(0, 100%, 40%);">- enable_ide_nand_flash_header();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- enable_USB_port4(sb);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* disable unwanted virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",</span><br><span style="color: hsl(0, 100%, 40%);">- sb->unwanted_vpci[i]);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0xDEADBEEF, 0xCFC);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_read_resources(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *res;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pci_dev_read_resources(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- res = new_resource(dev, 1);</span><br><span style="color: hsl(0, 100%, 40%);">- res->base = 0x0UL;</span><br><span style="color: hsl(0, 100%, 40%);">- res->size = 0x1000UL;</span><br><span style="color: hsl(0, 100%, 40%);">- res->limit = 0xffffUL;</span><br><span style="color: hsl(0, 100%, 40%);">- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- res = new_resource(dev, 3); /* IOAPIC */</span><br><span style="color: hsl(0, 100%, 40%);">- res->base = IO_APIC_ADDR;</span><br><span style="color: hsl(0, 100%, 40%);">- res->size = 0x00001000;</span><br><span style="color: hsl(0, 100%, 40%);">- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_enable(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "cs5536: %s: dev is %p\n", __func__, dev);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 device;</span><br><span style="color: hsl(0, 100%, 40%);">- struct resource *res;</span><br><span style="color: hsl(0, 100%, 40%);">- struct bus *pbus;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- device = dev->path.i2c.device;</span><br><span style="color: hsl(0, 100%, 40%);">- pbus = get_pbus_smbus(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- res = find_resource(pbus->dev, 0x10);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return do_smbus_read_byte(res->base, device, address);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct smbus_bus_operations lops_smbus_bus = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_byte = lsmbus_read_byte,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void scan_lpc_smbus(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME. Do we have mixed LPC/SMBus device node here. */</span><br><span style="color: hsl(0, 100%, 40%);">- scan_smbus(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations southbridge_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = cs5536_read_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = pci_dev_set_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = pci_dev_enable_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .init = southbridge_init,</span><br><span style="color: hsl(0, 100%, 40%);">- .scan_bus = scan_lpc_smbus,</span><br><span style="color: hsl(0, 100%, 40%);">- .ops_smbus_bus = &lops_smbus_bus,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pci_driver cs5536_pci_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &southbridge_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .vendor = PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- .device = PCI_DEVICE_ID_AMD_CS5536_ISA</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-struct chip_operations southbridge_amd_cs5536_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- CHIP_NAME("AMD Geode CS5536 Southbridge")</span><br><span style="color: hsl(0, 100%, 40%);">- /* This is only called when this device is listed in the</span><br><span style="color: hsl(0, 100%, 40%);">- * static device tree.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_dev = southbridge_enable,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h</span><br><span>deleted file mode 100644</span><br><span>index 06c504a..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/cs5536.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,454 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _CS5536_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define _CS5536_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define Cx5536_ID ( 0x208F1022)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SouthBridge Equates */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMBUS_IO_BASE 0x6000</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_IO_BASE 0x6100</span><br><span style="color: hsl(0, 100%, 40%);">-#define MFGPT_IO_BASE 0x6200</span><br><span style="color: hsl(0, 100%, 40%);">-#define ACPI_IO_BASE 0x9C00</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMS_IO_BASE 0x9D00</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CHIPSET_DEV_NUM 15</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDSEL_BASE 11 /* bit 11 = device 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Cs5536 as follows. */</span><br><span style="color: hsl(0, 100%, 40%);">-/* SB_GLIU */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port0 - GLIU */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port1 - GLPCI */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port2 - USB Controller #2 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port3 - ATA-5 Controller */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port4 - MDD */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port5 - AC97 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port6 - USB Controller #1 */</span><br><span style="color: hsl(0, 100%, 40%);">-/* port7 - GLCP */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GLIU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB1 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* USB2 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* ATA */</span><br><span style="color: hsl(0, 100%, 40%);">-#define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* AC97 */</span><br><span style="color: hsl(0, 100%, 40%);">-#define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GLPCI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLPCI_CRTL_PPIDE_SET (1 << 17)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GLCP */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* MDD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define LBAR_EN (0x01)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IO_MASK (0x1f)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MEM_MASK (0x0FFFFF)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LEG_IO (MSR_SB_MDD + 0x14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_SOFT_IRQ (MSR_SB_MDD + 0x16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_SOFT_RESET (MSR_SB_MDD + 0x17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_NORF_T01 (MSR_SB_MDD + 0x19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_NORF_T23 (MSR_SB_MDD + 0x1A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_AC_DMA (MSR_SB_MDD + 0x1E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_PRIM (MSR_SB_MDD + 0x24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_LPC (MSR_SB_MDD + 0x25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x27)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_MFGPT_NR (MSR_SB_MDD + 0x29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x2A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x2B)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_FLOP_S372 (MSR_SB_MDD + 0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_FLOP_S377 (MSR_SB_MDD + 0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_PIC_S (MSR_SB_MDD + 0x34)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_PIT_S (MSR_SB_MDD + 0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_PIT_CNTRL (MSR_SB_MDD + 0x37)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART1_MOD (MSR_SB_MDD + 0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART1_DON (MSR_SB_MDD + 0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART1_CONF (MSR_SB_MDD + 0x3A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART2_MOD (MSR_SB_MDD + 0x3C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART2_DON (MSR_SB_MDD + 0x3D)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_UART2_CONF (MSR_SB_MDD + 0x3E)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_MAP (MSR_SB_MDD + 0x40)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x41)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x42)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x43)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x44)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x45)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x46)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x47)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x48)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x49)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LPC_EADDR (MSR_SB_MDD + 0x4C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LPC_ESTAT (MSR_SB_MDD + 0x4D)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LPC_SIRQ (MSR_SB_MDD + 0x4E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_LPC_RES (MSR_SB_MDD + 0x4F)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_PML_TMR (MSR_SB_MDD + 0x50)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x54)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x55)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x56)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x57)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* LBUS Device Equates - */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMBus */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_SDA 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS 0x01</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_SLVSTP (0x01 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_SDAST (0x01 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_BER (0x01 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_NEGACK (0x01 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_STASTR (0x01 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_NMATCH (0x01 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_MASTER (0x01 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_STS_XMIT (0x01 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL_STS 0x02</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_TGSCL (0x01 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_TSDA (0x01 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_GCMTCH (0x01 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_MATCH (0x01 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_BB (0x01 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CSTS_BUSY (0x01 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1 0x03</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_STASTRE (0x01 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_NMINTE (0x01 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_GCMEN (0x01 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_ACK (0x01 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_RSVD (0x01 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_INTEN (0x01 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_STOP (0x01 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL1_START (0x01 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_ADD 0x04</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_ADD_SAEN (0x01 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL2 0x05</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL2_ENABLE (0x01 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMB_CTRL3 0x06</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPIO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_0_SET (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_1_SET (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_2_SET (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_3_SET (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_4_SET (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_5_SET (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_6_SET (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_7_SET (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_8_SET (1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_9_SET (1 << 9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_10_SET (1 << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_11_SET (1 << 11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_12_SET (1 << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_13_SET (1 << 13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_14_SET (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_15_SET (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_0_CLEAR (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_1_CLEAR (1 << 17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_2_CLEAR (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_3_CLEAR (1 << 19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_4_CLEAR (1 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_5_CLEAR (1 << 21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_6_CLEAR (1 << 22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_7_CLEAR (1 << 23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_8_CLEAR (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_9_CLEAR (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_10_CLEAR (1 << 26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_11_CLEAR (1 << 27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_12_CLEAR (1 << 28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_13_CLEAR (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_14_CLEAR (1 << 30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_15_CLEAR (1 << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_16_SET (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_17_SET (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_18_SET (1 << 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_19_SET (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_20_SET (1 << 4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_21_SET (1 << 5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_22_SET (1 << 6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_23_SET (1 << 7)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_24_SET (1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_25_SET (1 << 9)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_26_SET (1 << 10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_27_SET (1 << 11)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_28_SET (1 << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_29_SET (1 << 13)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_30_SET (1 << 14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_31_SET (1 << 15)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_16_CLEAR (1 << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_17_CLEAR (1 << 17)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_18_CLEAR (1 << 18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_19_CLEAR (1 << 19)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_20_CLEAR (1 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_21_CLEAR (1 << 21)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_22_CLEAR (1 << 22)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_23_CLEAR (1 << 23)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_24_CLEAR (1 << 24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_25_CLEAR (1 << 25)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_26_CLEAR (1 << 26)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_27_CLEAR (1 << 27)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_28_CLEAR (1 << 28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_29_CLEAR (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_30_CLEAR (1 << 30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_31_CLEAR (1 << 31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPIO LOW Bank Bit Registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUTPUT_VALUE (0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUTPUT_ENABLE (0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUT_OPENDRAIN (0x08)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUTPUT_INVERT_ENABLE (0x0C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUT_AUX1_SELECT (0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_OUT_AUX2_SELECT (0x14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_PULLUP_ENABLE (0x18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_PULLDOWN_ENABLE (0x1C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_INPUT_ENABLE (0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_INPUT_INVERT_ENABLE (0x24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_FILTER_ENABLE (0x28)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_READ_BACK (0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_AUX1_SELECT (0x34)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_EVENTS_ENABLE (0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_LOCK_ENABLE (0x3C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_POSEDGE_ENABLE (0x40)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_NEGEDGE_ENABLE (0x44)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_POSEDGE_STATUS (0x48)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_NEGEDGE_STATUS (0x4C)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* GPIO High Bank Bit Registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUTPUT_VALUE (0x80)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUTPUT_ENABLE (0x84)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUT_OPENDRAIN (0x88)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUTPUT_INVERT_ENABLE (0x8C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUT_AUX1_SELECT (0x90)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_OUT_AUX2_SELECT (0x94)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_PULLUP_ENABLE (0x98)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_PULLDOWN_ENABLE (0x9C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_INPUT_ENABLE (0xA0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_INPUT_INVERT_ENABLE (0xA4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_FILTER_ENABLE (0xA8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_EVENTCOUNT_ENABLE (0xAC)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_READ_BACK (0xB0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_AUX1_SELECT (0xB4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_EVENTS_ENABLE (0xB8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_LOCK_ENABLE (0xBC)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_POSEDGE_ENABLE (0xC0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_NEGEDGE_ENABLE (0xC4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_POSEDGE_STATUS (0xC8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_NEGEDGE_STATUS (0xCC)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Input Conditioning Function Registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_00_FILTER_AMOUNT (0x50)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_00_FILTER_COUNT (0x52)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_00_EVENT_COUNT (0x54)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_00_EVENTCOMPARE_VALUE (0x56)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_01_FILTER_AMOUNT (0x58)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_01_FILTER_COUNT (0x5A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_01_EVENT_COUNT (0x5C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_01_EVENTCOMPARE_VALUE (0x5E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_02_FILTER_AMOUNT (0x60)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_02_FILTER_COUNT (0x62)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_02_EVENT_COUNT (0x64)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_02_EVENTCOMPARE_VALUE (0x66)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_03_FILTER_AMOUNT (0x68)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_03_FILTER_COUNT (0x6A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_03_EVENT_COUNT (0x6C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_03_EVENTCOMPARE_VALUE (0x6E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_04_FILTER_AMOUNT (0x70)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_04_FILTER_COUNT (0x72)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_04_EVENT_COUNT (0x74)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_04_EVENTCOMPARE_VALUE (0x76)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_05_FILTER_AMOUNT (0x78)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_05_FILTER_COUNT (0x7A)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_05_EVENT_COUNT (0x7C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_05_EVENTCOMPARE_VALUE (0x7E)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_06_FILTER_AMOUNT (0xD0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_06_FILTER_COUNT (0xD2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_06_EVENT_COUNT (0xD4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_06_EVENTCOMPARE_VALUE (0xD6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_07_FILTER_AMOUNT (0xD8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_07_FILTER_COUNT (0xDA)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_07_EVENT_COUNT (0xDC)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_07_EVENTCOMPARE_VALUE (0xDE)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* R/W GPIO Interrupt &PME Mapper Registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MAPPER_X (0xE0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MAPPER_Y (0xE4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MAPPER_Z (0xE8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_MAPPER_W (0xEC)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_0 (0xF0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_1 (0xF1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_2 (0xF2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_3 (0xF3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_4 (0xF4)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_5 (0xF5)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_6 (0xF6)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FE_SELECT_7 (0xF7)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Event Counter Decrement Registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOL_IN_EVENT_DECREMENT (0xF8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIOH_IN_EVENT_DECREMENT (0xFC)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* PMC register */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SSD (0x00)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SCXA (0x04)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SCYA (0x08)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SODA (0x0C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SCLK (0x10)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SED (0x14)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SCXD (0x18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SCYD (0x1C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SIDD (0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_WKD (0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_WKXD (0x34)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_RD (0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_WKXA (0x3C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_FSD (0x40)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_TSD (0x44)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_PSD (0x48)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_NWKD (0x4C)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_AWKD (0x50)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_SSC (0x54)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* FLASH device macros */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_TYPE_NONE 0 /* No flash device installed */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_TYPE_NAND 1 /* NAND device */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_TYPE_NOR 2 /* NOR device */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IF_IO 2 /* I/O interface for Flash device */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Flash Memory Mask values */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_DEFAULT 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_4K 0xFFFFF000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_8K 0xFFFFE000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_16K 0xFFFFC000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_128K 0xFFFE0000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_512K 0xFFFC0000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_4M 0xFFC00000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_8M 0xFF800000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_MEM_16M 0xFF000000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Flash IO Mask values */</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_DEFAULT 0x00000000</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_16B 0x0000FFF0</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_32B 0x0000FFE0</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_64B 0x0000FFC0</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_128B 0x0000FF80</span><br><span style="color: hsl(0, 100%, 40%);">-#define FLASH_IO_256B 0x0000FF00</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if !defined(__ASSEMBLER__)</span><br><span style="color: hsl(0, 100%, 40%);">-#if defined(__PRE_RAM__)</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_setup_onchipuart(int uart);</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_disable_internal_uart(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_early_setup(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_enable_smbus(void);</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_read_byte(unsigned int device, unsigned int address);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">-void chipsetinit(void);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _CS5536_H */</span><br><span>diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c</span><br><span>deleted file mode 100644</span><br><span>index a95a0b4..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/early_setup.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,276 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device</span><br><span style="color: hsl(0, 100%, 40%);">- * This file implements the initialization sequence documented in section 4.2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/amd/lxdef.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "cs5536.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * @brief Setup PCI IDSEL for CS5536</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_extmsr(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = msr.lo = 0x00000000;</span><br><span style="color: hsl(0, 100%, 40%);">-#if CS5536_GLINK_PORT_NUM <= 4</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);</span><br><span style="color: hsl(0, 100%, 40%);">-#else</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLPCI_ExtMSR, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_idsel(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* write IDSEL to the write once register at address 0x0000 */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0x1 << (CS5536_DEV_NUM + 10), 0);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_usb_swapsif(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);</span><br><span style="color: hsl(0, 100%, 40%);">- //USB Serial short detect bit.</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.hi & 0x10) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* We need to preserve bits 32,33,35 and not clear any BIST</span><br><span style="color: hsl(0, 100%, 40%);">- * error, but clear the SERSHRT error bit */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi &= 0xFFFFFFFB;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_iobase(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup LBAR for SMBus controller */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x0000f001;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = SMBUS_IO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LBAR_SMB, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup LBAR for GPIO */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x0000f001;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = GPIO_IO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LBAR_GPIO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup LBAR for MFGPT */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x0000f001;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = MFGPT_IO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LBAR_MFGPT, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup LBAR for ACPI */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x0000f001;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = ACPI_IO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LBAR_ACPI, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup LBAR for PM Support */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0x0000f001;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = PMS_IO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LBAR_PMS, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_power_button(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON)</span><br><span style="color: hsl(0, 100%, 40%);">- outl(0x40020000, PMS_IO_BASE + 0x40);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup WORK_AUX/GPIO24, it is the external signal for 5536</span><br><span style="color: hsl(0, 100%, 40%);">- * vsb_work_aux controls all voltage rails except Vstandby & Vmem.</span><br><span style="color: hsl(0, 100%, 40%);">- * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.</span><br><span style="color: hsl(0, 100%, 40%);">- * If WORK_AUX/GPIO24 is not enabled then soft-off will not work.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_gpio(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* setup GPIO pins 14/15 for SDA/SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- val = GPIOL_15_SET | GPIOL_14_SET;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Output Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Output AUX1 */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Input Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Input AUX1 */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_disable_internal_uart(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- /* The UARTs default to enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- * Disable and reset them and configure them later. (SIO init)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_UART1_CONF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 1; // reset</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; // disabled</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_UART2_CONF);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 1; // reset</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = 0; // disabled</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_cis_mode(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup CPU serial SouthBridge interface to mode C. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLPCI_SB_CTRL);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo &= ~0x18;</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x10;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(GLPCI_SB_CTRL, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- * Enable the on-chip UART.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * See page 412 of the AMD Geode CS5536 Companion Device data book.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_onchipuart1(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup early for polling only mode.</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1.</span><br><span style="color: hsl(0, 100%, 40%);">- * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34</span><br><span style="color: hsl(0, 100%, 40%);">- * 2. Enable UART I/O space in MDD.</span><br><span style="color: hsl(0, 100%, 40%);">- * MSR 0x51400014 bit 18:16</span><br><span style="color: hsl(0, 100%, 40%);">- * 3. Enable UART controller.</span><br><span style="color: hsl(0, 100%, 40%);">- * MSR 0x5140003A bit 0, 1</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO8 - UART1_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Output Enable (0x4) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: OUTAUX1 Select (0x10) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO9 - UART1_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Input Enable (0x20) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: INAUX1 Select (0x34) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set address to 0x3F8. */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x7 << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bit 1 = DEVEN (device enable)</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 4 = EN_BANKS (allow access to the upper banks)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (1 << 4) | (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable COM1. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART1_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void cs5536_setup_onchipuart2(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO4 - UART2_TX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Output Enable (0x4) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: OUTAUX1 Select (0x10) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO4 - UART2_RX */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: Input Enable (0x20) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: INAUX1 Select (0x34) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set: GPIO 3 + 3 Pull Up (0x18) */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(GPIOL_3_SET | GPIOL_4_SET,</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* set address to 2F8 */</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MDD_LEG_IO);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo |= 0x5 << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_LEG_IO, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bit 1 = DEVEN (device enable)</span><br><span style="color: hsl(0, 100%, 40%);">- * Bit 4 = EN_BANKS (allow access to the upper banks</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- msr.lo = (1 << 4) | (1 << 1);</span><br><span style="color: hsl(0, 100%, 40%);">- msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable COM2 */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MDD_UART2_CONF, msr);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_setup_onchipuart(int uart)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (uart) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 1:</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_onchipuart1();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 2:</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_onchipuart2();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* note: you can't do prints in here in most cases,</span><br><span style="color: hsl(0, 100%, 40%);">- * and we don't want to hang on serial, so they are</span><br><span style="color: hsl(0, 100%, 40%);">- * commented out</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_early_setup(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_extmsr();</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_cis_mode();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(GLCP_SYS_RSTPLL);</span><br><span style="color: hsl(0, 100%, 40%);">- if (msr.lo & (0x3f << 26)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* PLL is already set and we are reboot from PLL reset */</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "reboot from BIOS reset\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "Setup idsel\n");</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_idsel();</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "Setup iobase\n");</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_usb_swapsif();</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_iobase();</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "Setup gpio\n");</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_gpio();</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "Setup smbus\n");</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_enable_smbus();</span><br><span style="color: hsl(0, 100%, 40%);">- //printk(BIOS_DEBUG, "Setup power button\n");</span><br><span style="color: hsl(0, 100%, 40%);">- cs5536_setup_power_button();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c</span><br><span>deleted file mode 100644</span><br><span>index a1cf50b..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/early_smbus.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,39 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "cs5536.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "smbus.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* initialization for SMBus Controller */</span><br><span style="color: hsl(0, 100%, 40%);">-void cs5536_enable_smbus(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_NO_EARLY_SMBUS))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set SCL freq and enable SMB controller */</span><br><span style="color: hsl(0, 100%, 40%);">- /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */</span><br><span style="color: hsl(0, 100%, 40%);">- outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup SMBus host controller address to 0xEF */</span><br><span style="color: hsl(0, 100%, 40%);">- outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_read_byte(unsigned int device, unsigned int address)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/amd/cs5536/ide.c b/src/southbridge/amd/cs5536/ide.c</span><br><span>deleted file mode 100644</span><br><span>index 53723e6..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/ide.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,57 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ops.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "cs5536.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_CFG 0x40</span><br><span style="color: hsl(0, 100%, 40%);">- #define CHANEN (1L << 1)</span><br><span style="color: hsl(0, 100%, 40%);">- #define PWB (1L << 14)</span><br><span style="color: hsl(0, 100%, 40%);">- #define CABLE (1L << 16)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_DTC 0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_CAST 0x4C</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_ETC 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void ide_init(struct device *dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t ide_cfg;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO and IRQ setup are handled in the main chipset code. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- // Enable the channel and Post Write Buffer</span><br><span style="color: hsl(0, 100%, 40%);">- // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set</span><br><span style="color: hsl(0, 100%, 40%);">- ide_cfg = pci_read_config32(dev, IDE_CFG);</span><br><span style="color: hsl(0, 100%, 40%);">- ide_cfg |= CHANEN | PWB;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, IDE_CFG, ide_cfg);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static struct device_operations ide_ops = {</span><br><span style="color: hsl(0, 100%, 40%);">- .read_resources = pci_dev_read_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .set_resources = pci_dev_set_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable_resources = pci_dev_enable_resources,</span><br><span style="color: hsl(0, 100%, 40%);">- .init = ide_init,</span><br><span style="color: hsl(0, 100%, 40%);">- .enable = 0,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static const struct pci_driver ide_driver __pci_driver = {</span><br><span style="color: hsl(0, 100%, 40%);">- .ops = &ide_ops,</span><br><span style="color: hsl(0, 100%, 40%);">- .vendor = PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE,</span><br><span style="color: hsl(0, 100%, 40%);">-};</span><br><span>diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c</span><br><span>deleted file mode 100644</span><br><span>index 75bb168..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/pirq.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,34 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/pirq_routing.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)</span><br><span style="color: hsl(0, 100%, 40%);">-void pirq_assign_irqs(const unsigned char pIntAtoD[4])</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *pdev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- pdev = dev_find_device(PCI_VENDOR_ID_AMD,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_AMD_CS5536_ISA, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (pdev) {</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12</span><br><span style="color: hsl(0, 100%, 40%);">- | pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0]));</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span>diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c</span><br><span>deleted file mode 100644</span><br><span>index ddbcdf2..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/smbus.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,187 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "cs5536.h"</span><br><span style="color: hsl(0, 100%, 40%);">-#include "smbus.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMBUS_TIMEOUT (1000)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_delay(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* inb(0x80); */</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int smbus_wait(unsigned smbus_io_base)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long loops = SMBUS_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- smbus_delay();</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((val & SMB_STS_SDAST) != 0)</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */</span><br><span style="color: hsl(0, 100%, 40%);">- return SMBUS_ERROR;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } while (--loops);</span><br><span style="color: hsl(0, 100%, 40%);">- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* generate a smbus start condition */</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_start_condition(unsigned smbus_io_base)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* issue a START condition */</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* check for bus conflict */</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((val & SMB_STS_BER) != 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return SMBUS_ERROR;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return smbus_wait(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_check_stop_condition(unsigned smbus_io_base)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val;</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned long loops;</span><br><span style="color: hsl(0, 100%, 40%);">- loops = SMBUS_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">- /* check for SDA status */</span><br><span style="color: hsl(0, 100%, 40%);">- do {</span><br><span style="color: hsl(0, 100%, 40%);">- smbus_delay();</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">- if ((val & SMB_CTRL1_STOP) == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);</span><br><span style="color: hsl(0, 100%, 40%);">- } while (--loops);</span><br><span style="color: hsl(0, 100%, 40%);">- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_stop_condition(unsigned smbus_io_base)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">- return smbus_wait(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static int smbus_ack(unsigned smbus_io_base, int state)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val = inb(smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* if (state) */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">-/* else</span><br><span style="color: hsl(0, 100%, 40%);">- outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);</span><br><span style="color: hsl(0, 100%, 40%);">-*/</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_send_slave_address(unsigned smbus_io_base,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char device)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* send the slave address */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(device, smbus_io_base + SMB_SDA);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* check for bus conflict and NACK */</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */</span><br><span style="color: hsl(0, 100%, 40%);">- return SMBUS_ERROR;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return smbus_wait(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_send_command(unsigned smbus_io_base, unsigned char command)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char val;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* send the command */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(command, smbus_io_base + SMB_SDA);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* check for bus conflict and NACK */</span><br><span style="color: hsl(0, 100%, 40%);">- val = inb(smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))</span><br><span style="color: hsl(0, 100%, 40%);">- return SMBUS_ERROR;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return smbus_wait(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned char smbus_get_result(unsigned smbus_io_base)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return inb(smbus_io_base + SMB_SDA);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned char do_smbus_read_byte(unsigned smbus_io_base,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char device,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char address)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char error = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_check_stop_condition(smbus_io_base))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_start_condition(smbus_io_base))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 2;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_send_slave_address(smbus_io_base, device << 1))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 3;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- smbus_ack(smbus_io_base, 1);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_send_command(smbus_io_base, address))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 4;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_start_condition(smbus_io_base))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 5;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 6;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if ((smbus_stop_condition(smbus_io_base))) {</span><br><span style="color: hsl(0, 100%, 40%);">- error = 7;</span><br><span style="color: hsl(0, 100%, 40%);">- goto err;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return smbus_get_result(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-err:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "SMBUS READ ERROR: %02x device: %02x\n", error, device);</span><br><span style="color: hsl(0, 100%, 40%);">- /* stop, clean up the error, and leave */</span><br><span style="color: hsl(0, 100%, 40%);">- smbus_stop_condition(smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0x0, smbus_io_base + SMB_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- return 0xFF;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h</span><br><span>deleted file mode 100644</span><br><span>index 3d67ace..0000000</span><br><span>--- a/src/southbridge/amd/cs5536/smbus.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,32 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License version 2 as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _CS5536_SMBUS_H</span><br><span style="color: hsl(0, 100%, 40%);">-#define _CS5536_SMBUS_H</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/smbus_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_start_condition(unsigned smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_stop_condition(unsigned smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_check_stop_condition(unsigned smbus_io_base);</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_send_slave_address(unsigned smbus_io_base,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char device);</span><br><span style="color: hsl(0, 100%, 40%);">-int smbus_send_command(unsigned smbus_io_base, unsigned char command);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned char do_smbus_read_byte(unsigned smbus_io_base,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char device,</span><br><span style="color: hsl(0, 100%, 40%);">- unsigned char address);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* _CS5536_SMBUS_H */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30326">change 30326</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30326"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3 </div>
<div style="display:none"> Gerrit-Change-Number: 30326 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>