<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30312">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[RFC] src/mainboard/cmr/cmedrobo: initial commit<br><br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>Change-Id: I40de818d85a15e6515fe6585f9f8c07336f17242<br>---<br>A src/mainboard/cmr/Kconfig<br>A src/mainboard/cmr/Kconfig.name<br>A src/mainboard/cmr/cmedrobo/Kconfig<br>A src/mainboard/cmr/cmedrobo/Kconfig.name<br>A src/mainboard/cmr/cmedrobo/Makefile.inc<br>A src/mainboard/cmr/cmedrobo/acpi/ec.asl<br>A src/mainboard/cmr/cmedrobo/acpi/mainboard.asl<br>A src/mainboard/cmr/cmedrobo/acpi/superio.asl<br>A src/mainboard/cmr/cmedrobo/acpi_tables.c<br>A src/mainboard/cmr/cmedrobo/board_info.txt<br>A src/mainboard/cmr/cmedrobo/cmos.layout<br>A src/mainboard/cmr/cmedrobo/devicetree.cb<br>A src/mainboard/cmr/cmedrobo/dsdt.asl<br>A src/mainboard/cmr/cmedrobo/fadt.c<br>A src/mainboard/cmr/cmedrobo/gpio.c<br>A src/mainboard/cmr/cmedrobo/irq_tables.c<br>A src/mainboard/cmr/cmedrobo/irqroute.c<br>A src/mainboard/cmr/cmedrobo/irqroute.h<br>A src/mainboard/cmr/cmedrobo/mainboard.c<br>A src/mainboard/cmr/cmedrobo/mptable.c<br>A src/mainboard/cmr/cmedrobo/romstage.c<br>21 files changed, 1,300 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/30312/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/cmr/Kconfig b/src/mainboard/cmr/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..3d03f8e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/Kconfig</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if VENDOR_CMR</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+choice</span><br><span style="color: hsl(120, 100%, 40%);">+ prompt "Mainboard model"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/cmr/*/Kconfig.name"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endchoice</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/mainboard/cmr/*/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_VENDOR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "CMR"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # VENDOR_PCENGINES</span><br><span>diff --git a/src/mainboard/cmr/Kconfig.name b/src/mainboard/cmr/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..13e701f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDOR_CMR</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "CMR"</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/Kconfig b/src/mainboard/cmr/cmedrobo/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..a2a55e8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/Kconfig</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_CMR_CMEDROBO</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_FSP_BAYTRAIL</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_MP_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_PIRQ_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select TSC_MONOTONIC_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select IOAPIC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "cmr/cmedrobo"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Minnow Max"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config FSP_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CBFS_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x00600000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config ENABLE_FSP_FAST_BOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on HAVE_FSP_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VIRTUAL_ROM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on ENABLE_FSP_FAST_BOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x800000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config POST_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y if FSP_PACKAGE_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_PIRQ_LINKS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config IRQ_SLOT_COUNT</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_INTEL_MINNOWMAX</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/Kconfig.name b/src/mainboard/cmr/cmedrobo/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..60983f33</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_CMR_CMEDROBO</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "CMR Robo"</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/Makefile.inc b/src/mainboard/cmr/cmedrobo/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..6e0272f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/Makefile.inc</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += irqroute.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/acpi/ec.asl b/src/mainboard/cmr/cmedrobo/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/acpi/mainboard.asl b/src/mainboard/cmr/cmedrobo/acpi/mainboard.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b032ee1</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/acpi/mainboard.asl</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (PWRB)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_HID, EisaId("PNP0C0C"))</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/acpi/superio.asl b/src/mainboard/cmr/cmedrobo/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/acpi/superio.asl</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/acpi_tables.c b/src/mainboard/cmr/cmedrobo/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..33672c5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/acpi_tables.c</span><br><span>@@ -0,0 +1,64 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h> // hexdump</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_init_gnvs(gnvs);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable USB ports in S3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* No TPM Present */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpmp = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->dpte = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_fill_madt(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Local APICs */</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_create_madt_lapics(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IOAPIC */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, IO_APIC_ADDR, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_madt_irq_overrides(current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/board_info.txt b/src/mainboard/cmr/cmedrobo/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..5af79f8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/board_info.txt</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: sbc</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2014</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/cmos.layout b/src/mainboard/cmr/cmedrobo/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..4cb5106</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/cmos.layout</span><br><span>@@ -0,0 +1,108 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+400 1 e 2 hyper_threading</span><br><span style="color: hsl(120, 100%, 40%);">+#401 7 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+411 2 e 8 use_xhci_over_ehci</span><br><span style="color: hsl(120, 100%, 40%);">+#413 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+#1000 24 r 0 amd_reserved</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#save timestamps in pre-ram boot areas</span><br><span style="color: hsl(120, 100%, 40%);">+1720 64 h 0 timestamp_value1</span><br><span style="color: hsl(120, 100%, 40%);">+1784 64 h 0 timestamp_value2</span><br><span style="color: hsl(120, 100%, 40%);">+1848 64 h 0 timestamp_value3</span><br><span style="color: hsl(120, 100%, 40%);">+1912 64 h 0 timestamp_value4</span><br><span style="color: hsl(120, 100%, 40%);">+1976 64 h 0 timestamp_value5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+8 0 EHCI</span><br><span style="color: hsl(120, 100%, 40%);">+8 1 XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+8 2 Default</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 415 984</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/devicetree.cb b/src/mainboard/cmr/cmedrobo/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..264a24d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/devicetree.cb</span><br><span>@@ -0,0 +1,94 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/fsp_baytrail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #### ACPI Register Settings ####</span><br><span style="color: hsl(120, 100%, 40%);">+ register "fadt_pm_profile" = "PM_MOBILE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #### FSP register settings ####</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdSataMode" = "SATA_MODE_AHCI"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdGttSize" = "GTT_SIZE_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DRAMType" = "DRAM_TYPE_DDR3L"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMM0Enable" = "DIMM0_ENABLE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMM1Enable" = "DIMM1_DISABLE"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMDWidth" = "DIMM_DWIDTH_X16"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMSides" = "DIMM_SIDES_1RANK"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtCL" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtRPtRCD" = "11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtWR" = "12"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtWTR" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtRRD" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtRTP" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DIMMtFAW" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # 8086 0F00 - SoC router -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # 8086 0F31 - GFX micro HDMI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 03.0 off end # 8086 0F38 - MIPI -</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 10.0 off end # 8086 0F14 - EMMC Port -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 11.0 off end # 8086 0F15 - SDIO Port -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 off end # 8086 0F37 - OTG controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # 8086 0F50 - MMC Port -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.0 on end # 8086 0F40 - SIO - DMA -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on end # 8086 0F18 - TXE -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on end # 8086 0F04 - HD Audio -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # 8086 0F06 - SIO - DMA -</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 on end # 8086 0F0E - SPI LSEC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/dsdt.asl b/src/mainboard/cmr/cmedrobo/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..2f2c30d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/dsdt.asl</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define INCLUDE_LPE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define INCLUDE_SCC 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define INCLUDE_EHCI 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define INCLUDE_XHCI 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define INCLUDE_LPSS 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02, // DSDT revision: ACPI v2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20110725 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/fsp_baytrail/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // global NVS and variables</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/common/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/fsp_baytrail/acpi/southcluster.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific sleep states */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/mainboard.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/fadt.c b/src/mainboard/cmr/cmedrobo/fadt.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4194bfc</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/fadt.c</span><br><span>@@ -0,0 +1,29 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_header_t *header = &(fadt->header);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_fill_in_fadt(fadt, facs, dsdt);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Platform specific customizations go here */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/gpio.c b/src/mainboard/cmr/cmedrobo/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..3157dbb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/gpio.c</span><br><span>@@ -0,0 +1,240 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqroute.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * For multiplexed functions, look in EDS:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 10.3 Ball Name and Function by Location</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * The pads list is in the BWG_VOL2 Rev1p2:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Note that Pad # is not the same as GPIO#</span><br><span style="color: hsl(120, 100%, 40%);">+ * 37 GPIO Handling:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Table 37-1. SCORE Pads List</span><br><span style="color: hsl(120, 100%, 40%);">+ * Table 37-2. SSUSORE Pads List</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* NCORE GPIOs */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpncore_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[03] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[04] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[05] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[06] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[08] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[09] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[10] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[11] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[13] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[14] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[15] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[16] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[17] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[18] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[19] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[20] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[21] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[22] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[23] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[24] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[25] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_NC[26] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SCORE GPIOs (GPIO_S0_SC_XX) */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpscore_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[008] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[009] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[010] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[011] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[012] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[013] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[014] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[015] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[016] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[017] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[018] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[019] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[020] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[021] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[022] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[023] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[024] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[025] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[026] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[027] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[028] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[029] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[030] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[031] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[032] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD#</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[042] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[043] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[044] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[045] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[046] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[047] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[048] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[049] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[050] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[076] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[077] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[078] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[079] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[082] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[083] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[084] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[085] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[086] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[087] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[096] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[097] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[098] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[099] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[100] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S0_SC[101] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSUS GPIOs (GPIO_S5) */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct soc_gpio_map gpssus_gpio_map[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[04] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT, // GPIO_S5[05] - BOM_OP1</span><br><span style="color: hsl(120, 100%, 40%);">+ // Memory: 0=1GB 1=2GB or 4GB</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT, // GPIO_S5[06] - BOM_OP2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT, // GPIO_S5[07] - BOM_OP3</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[08] - SOC_USB_HOST_EN0</span><br><span style="color: hsl(120, 100%, 40%);">+ // Changed to NC for gpios on ABC</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[09] - SOC_USB_HOST_EN1</span><br><span style="color: hsl(120, 100%, 40%);">+ // Changed to NC for gpios on ABC</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[17] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7)</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[31] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[32] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[33] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[34] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[35] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[36] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[37] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[38] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[39] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[40] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[41] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[42] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_NC, // GPIO_S5[43] - No Connect</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_END</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct soc_gpio_config gpio_config = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .ncore = gpncore_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .score = gpscore_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ssus = gpssus_gpio_map,</span><br><span style="color: hsl(120, 100%, 40%);">+ .core_dirq = &core_dedicated_irq,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sus_dirq = &sus_dedicated_irq,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_gpio_config *mainboard_get_gpios(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return &gpio_config;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/irq_tables.c b/src/mainboard/cmr/cmedrobo/irq_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b4d0e24</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/irq_tables.c</span><br><span>@@ -0,0 +1,87 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013, Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/pirq_routing.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQA 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQB 0x05</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQC 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQD 0x0a</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQE 0x0b</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQF 0x0c</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQG 0x0e</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQH 0x0f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_IRQS 0xDCB0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_HEADER_SIZE 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define IRQ_INFO_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct irq_routing_table intel_irq_routing_table = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_SIGNATURE, /* u32 signature */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_VERSION, /* u16 version */</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_HEADER_SIZE + (IRQ_INFO_SIZE * CONFIG_IRQ_SLOT_COUNT), /* u16 size */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, /* Where the interrupt router lies (bus) */</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* IRQs devoted exclusively to PCI usage */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8086, /* Vendor */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F1C, /* Device */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* miniport */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, /* u8 checksum (filled later) */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // GFX INTA-PIRQA</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x12 << 3)|0x0, {{PIRQC, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SD INTA-PIRQC</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x13 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SATA INTA-PIRQD</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x15 << 3)|0x0, {{PIRQF, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPE INTA-PIRQF</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x18 << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQA, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQC, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQA, INTC-PIRQD, INTD-PIRQC</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x1b << 3)|0x0, {{PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // HDA INTA-PIRQG</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x1c << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQD</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x1d << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // EHCI INTA-PIRQD</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x1e << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQD, INTC-PIRQE, INTD-PIRQF</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x00,(0x1f << 3)|0x0, {{0x00, PCI_IRQS}, {PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPC INTB-PIRQG</span><br><span style="color: hsl(120, 100%, 40%);">+ {0x04,(0x00 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x4, 0x0}, // ETH INTA-PIRQA</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_pirq_routing_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update size */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct irq_routing_table intel_routing_table_copy;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(&intel_routing_table_copy, &intel_irq_routing_table,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(struct irq_routing_table));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update Checksum */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 sum = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *irt = (u8 *)&intel_routing_table_copy;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < intel_routing_table_copy.size; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ sum += irt[i];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ sum = intel_routing_table_copy.checksum - sum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((sum & 0xff) != intel_routing_table_copy.checksum) {</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_routing_table_copy.checksum = sum & 0xff;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return copy_pirq_routing_table(addr, &intel_routing_table_copy);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/irqroute.c b/src/mainboard/cmr/cmedrobo/irqroute.c</span><br><span>new file mode 100644</span><br><span>index 0000000..db8c512</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/irqroute.c</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "irqroute.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+DEFINE_IRQ_ROUTES;</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/irqroute.h b/src/mainboard/cmr/cmedrobo/irqroute.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f4e7c05</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/irqroute.h</span><br><span>@@ -0,0 +1,82 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef IRQROUTE_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define IRQROUTE_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/fsp_baytrail/include/soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR02h GFX INT(A) - PIRQ A</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR10h EMMC INT(ABCD) - PIRQ DEFG</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR11h SDIO INT(A) - PIRQ B</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR12h SD INT(A) - PIRQ C</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR13h SATA INT(A) - PIRQ D</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR14h XHCI INT(A) - PIRQ E</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR15h LP Audio INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR17h MMC INT(A) - PIRQ H</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR18h SIO INT(ABCD) - PIRQ BADC</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Ah TXE INT(A) - PIRQ F</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Bh HD Audio INT(A) - PIRQ G</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Ch PCIe INT(ABCD) - PIRQ EFGD</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Dh EHCI INT(A) - PIRQ D</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Eh SIO INT(ABCD) - PIRQ BDEF</span><br><span style="color: hsl(120, 100%, 40%);">+ *IR1Fh LPC INT(ABCD) - PIRQ EGBC</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCIe bridge routing */</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIDGE1_DEV PCIE_DEV</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI bridge IRQs need to be updated in both tables and need to match */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCIE_BRIDGE_IRQ_ROUTES</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Devices set as A, A, A, A evaluate as 0, and don't get set */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_DEV_PIRQ_ROUTES \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, H, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, D), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, E, G, B, C)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Route each PIRQ[A-H] to a PIC IRQ[0-15]</span><br><span style="color: hsl(120, 100%, 40%);">+ * Reserved: 0, 1, 2, 8, 13</span><br><span style="color: hsl(120, 100%, 40%);">+ * PS2 keyboard: 12</span><br><span style="color: hsl(120, 100%, 40%);">+ * ACPI/SCI: 9</span><br><span style="color: hsl(120, 100%, 40%);">+ * Floppy: 6</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_PIC_ROUTES \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(A, 4), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(B, 5), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(C, 7), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(D, 10), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(E, 11), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(F, 12), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(G, 14), \</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQ_PIC(H, 15)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IRQROUTE_H */</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/mainboard.c b/src/mainboard/cmr/cmedrobo/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0fe1259</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/mainboard.c</span><br><span>@@ -0,0 +1,41 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Sage Electronic Engineering, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * mainboard_enable is executed as first thing after enumerate_buses().</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is the earliest point to add customization.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * mainboard_final is executed as one of the last items before loading the</span><br><span style="color: hsl(120, 100%, 40%);">+ * payload.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is the latest point to add customization.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_final(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .final = mainboard_final,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/mptable.c b/src/mainboard/cmr/cmedrobo/mptable.c</span><br><span>new file mode 100644</span><br><span>index 0000000..394b29b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/mptable.c</span><br><span>@@ -0,0 +1,192 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013-2015 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/fsp_baytrail/include/soc/irq.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_PCI_ENTRIES 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define INT_A 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define INT_B 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define INT_C 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define INT_D 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_A PIRQA_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_B PIRQB_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_C PIRQB_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_D PIRQD_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_E PIRQE_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_F PIRQF_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_G PIRQG_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define PIRQ_H PIRQH_APIC_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_IRQ(dev, intLine) (((dev) << 2) | intLine)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define IO_LOCAL_INT(type, intr, apicid, pin) \</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_lintsrc(mc, (type), \</span><br><span style="color: hsl(120, 100%, 40%);">+ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, \</span><br><span style="color: hsl(120, 100%, 40%);">+ bus_isa, (intr), (apicid), (pin));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_INT(bus, dev, pin, line) \</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_pci_intsrc(mc, mp_INT, (bus), (dev), (pin), ioapic_id, (line))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Find the PIRQ that a device will trigger by looking</span><br><span style="color: hsl(120, 100%, 40%);">+ * it up in the IRQ routing table defined in mainboard/</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * return integer 0 - 7 corresponding to PIRQ[A - H]</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static int get_pirq(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct baytrail_irq_route *ir = &global_baytrail_irq_route;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 devn = PCI_SLOT(dev->path.pci.devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Search the global interrupt routing table that is</span><br><span style="color: hsl(120, 100%, 40%);">+ * defined in mainboard/irqroute.h for the dev we are</span><br><span style="color: hsl(120, 100%, 40%);">+ * interested in. Extract the PIRQ value (0-7) that</span><br><span style="color: hsl(120, 100%, 40%);">+ * we are interested in, where INT PINA is in bits 0-3,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PINB is in bits 4-7, PINC is in bits 8-11, and PIND is</span><br><span style="color: hsl(120, 100%, 40%);">+ * in bits 12-15</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ return (ir->pcidev[devn] >> ((pin - 1) * 4)) & 7;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void *smp_write_config_table(void *v)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "Auto generating MP Table\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ struct mp_config_table *mc;</span><br><span style="color: hsl(120, 100%, 40%);">+ int isa_bus;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i, entry_exists = 0, pirq = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 busn, devn;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 intpin = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int existing_pci_entries[MAX_PCI_ENTRIES];</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < MAX_PCI_ENTRIES; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ existing_pci_entries[i] = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 0: Processor Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,</span><br><span style="color: hsl(120, 100%, 40%);">+ * CPU Signature (Stepping, Model, Family),</span><br><span style="color: hsl(120, 100%, 40%);">+ * Feature Flags</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_processors(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 1: Bus Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bus ID, Bus Type</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_write_buses(mc, NULL, &isa_bus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 2: I/O APICs:</span><br><span style="color: hsl(120, 100%, 40%);">+ * APIC ID, Version, APIC Flags:EN, Address</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 3: I/O Interrupt Table Entries:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Int Type, Int Polarity, Int Level, Source Bus ID,</span><br><span style="color: hsl(120, 100%, 40%);">+ * Source Bus IRQ, Dest APIC ID, Dest PIN#</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Type 3: I/O Interrupt Table Entries for PCI Devices:</span><br><span style="color: hsl(120, 100%, 40%);">+ * This has the same fields as 'Type 3: I/O Interrupt Table Entries'</span><br><span style="color: hsl(120, 100%, 40%);">+ * but the Source Bus IRQ field has a slightly different</span><br><span style="color: hsl(120, 100%, 40%);">+ * definition:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bits 2-6: Originating PCI Device Number (Not its parent bridge device number)</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bit 7: Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ for(dev = all_devices; dev; dev = dev->next) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI || !dev->enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get bus, dev, func info */</span><br><span style="color: hsl(120, 100%, 40%);">+ busn = dev->bus->secondary;</span><br><span style="color: hsl(120, 100%, 40%);">+ devn = PCI_SLOT(dev->path.pci.devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get PCI dev's IRQ info */</span><br><span style="color: hsl(120, 100%, 40%);">+ intpin = pci_read_config8(dev, PCI_INTERRUPT_PIN);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (intpin < 1 || intpin > 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pirq = get_pirq(dev) + PIRQ_A;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pirq >= PIRQ_A) {</span><br><span style="color: hsl(120, 100%, 40%);">+ entry_exists = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < MAX_PCI_ENTRIES; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if(PCI_IRQ(devn, (intpin - 1)) == existing_pci_entries[i]) {</span><br><span style="color: hsl(120, 100%, 40%);">+ entry_exists = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (existing_pci_entries[i] == -1)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (i >= MAX_PCI_ENTRIES) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "Warning: Added the maximum number of PCI entries (%d),"</span><br><span style="color: hsl(120, 100%, 40%);">+ "increase 'MAX_PCI_ENTRIES' to add more\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ MAX_PCI_ENTRIES);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If the entry doesn't already exist, add it */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!entry_exists) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bus, Dev, Fn, PIRQ[A-H] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_INT(busn, devn, intpin - 1, pirq);</span><br><span style="color: hsl(120, 100%, 40%);">+ existing_pci_entries[i] = PCI_IRQ(devn, (intpin - 1));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mptable_lintsrc(mc, isa_bus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* There is no extension information... */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Compute the checksums */</span><br><span style="color: hsl(120, 100%, 40%);">+ return mptable_finalize(mc);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long write_smp_table(unsigned long addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ void *v;</span><br><span style="color: hsl(120, 100%, 40%);">+ v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */</span><br><span style="color: hsl(120, 100%, 40%);">+ return (unsigned long)smp_write_config_table(v);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/cmr/cmedrobo/romstage.c b/src/mainboard/cmr/cmedrobo/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ebc3df5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/cmr/cmedrobo/romstage.c</span><br><span>@@ -0,0 +1,154 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 CMR Surgical Limited</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/fsp1_0/fsp_util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/fsp_baytrail/chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/tsc.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * /brief mainboard call for setup that needs to be done before fsp init</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void early_mainboard_romstage_entry(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *lvscc = (void *)(SPI_BASE_ADDRESS + 0xc4);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 4KiB Erase opcode for N25Q parts. */</span><br><span style="color: hsl(120, 100%, 40%);">+ //reg = 0x20 << 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 64KiB Erase opcode for N25Q parts. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = 0xd8 << 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Write granularity 1 byte. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= 0 << 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 4KiB sector erase size. */</span><br><span style="color: hsl(120, 100%, 40%);">+ //reg |= 0x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /*64KiB sector erase size. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg |= 0x3;</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+ write32(lvscc, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(lvscc + 4, reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Get function disables - most of these will be done automatically</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param fd_mask</span><br><span style="color: hsl(120, 100%, 40%);">+ * @param fd2_mask</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * /brief mainboard call for setup that needs to be done after fsp init</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void late_mainboard_romstage_entry(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set up the default soldered down memory config for 1GB */</span><br><span style="color: hsl(120, 100%, 40%);">+static const MEMORY_DOWN_DATA minnowmax_memory_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1066 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .EnableMemoryDown = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMSpeed = 1, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM0Enable = 1, /* DIMM 0 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM1Enable = 0, /* DIMM 1 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtCL = 11, /* tCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWR = 12, /* tWR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWTR = 6, /* tWTR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRRD = 6, /* tRRD in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRTP = 6, /* tRTP in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtFAW = 20, /* tFAW in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 1333 */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ .EnableMemoryDown = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMSpeed = 2, /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM0Enable = 1, /* DIMM 0 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMM1Enable = 0, /* DIMM 1 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDWidth = 1, /* DRAM device data width: 0=x8, 1=x16, 2=x32*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMSides = 0, /* Ranks Per DIMM: 0=1rank, 1=2rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtCL = 9, /* tCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWR = 10, /* tWR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtWTR = 5, /* tWTR in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRRD = 4, /* tRRD in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtRTP = 5, /* tRTP in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ .DIMMtFAW = 30, /* tFAW in DRAM clk */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 use_xhci = UpdData->PcdEnableXhci;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 gpio5 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ int is_1333_sku;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's</span><br><span style="color: hsl(120, 100%, 40%);">+ * no good way of knowing the SKU'ing so frequency is used as a proxy.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the</span><br><span style="color: hsl(120, 100%, 40%);">+ * E3827 and E3845 are 1750MHz and 1910MHz, respectively.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ is_1333_sku = !!(tsc_freq_mhz() >= 1700);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ is_1333_sku ? 1333 : 1066);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up soldered down memory parameters for 1GB */</span><br><span style="color: hsl(120, 100%, 40%);">+ UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Minnow Max Board</span><br><span style="color: hsl(120, 100%, 40%);">+ * Read SSUS gpio 5 to determine memory type</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 : 1GB SKU uses 2Gb density memory</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 : 2GB SKU uses 4Gb density memory</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * devicetree.cb assumes 1GB SKU board</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio5 = read_ssus_gpio(5);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio5)</span><br><span style="color: hsl(120, 100%, 40%);">+ UpdData->PcdMemoryParameters.DIMMDensity</span><br><span style="color: hsl(120, 100%, 40%);">+ += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio5 ? "2 / 4" : "1");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Update XHCI UPD value if required */</span><br><span style="color: hsl(120, 100%, 40%);">+ get_option(&use_xhci, "use_xhci_over_ehci");</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ UpdData->PcdEnableXhci = use_xhci;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ UpdData->PcdEnableXhci?"Enabled":"Disabled");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30312">change 30312</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30312"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I40de818d85a15e6515fe6585f9f8c07336f17242 </div>
<div style="display:none"> Gerrit-Change-Number: 30312 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>