<p>Patrick Georgi <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30216">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Nick Vaccaro: Looks good to me, but someone else must approve

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Enable CPU flexible ratio<br><br>CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been<br>set to zero.<br><br>BUG=N/A<br>TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is<br>changing.<br><br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82<br>Reviewed-on: https://review.coreboot.org/c/30216<br>Reviewed-by: Nick Vaccaro <nvaccaro@google.com><br>Reviewed-by: Duncan Laurie <dlaurie@chromium.org><br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>---<br>M src/soc/intel/cannonlake/romstage/fsp_params.c<br>1 file changed, 0 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>index 8f6fa2f..3e0f922 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c</span><br><span>@@ -45,8 +45,6 @@</span><br><span>  m_cfg->PcieRpEnableMask = mask;</span><br><span>   m_cfg->PrmrrSize = config->PrmrrSize;</span><br><span>  m_cfg->EnableC6Dram = config->enable_c6dram;</span><br><span style="color: hsl(0, 100%, 40%);">-      /* Disable Cpu Ratio Override temporary. */</span><br><span style="color: hsl(0, 100%, 40%);">-     m_cfg->CpuRatio = 0;</span><br><span>      m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;</span><br><span>   /* Disable Vmx if Vt-d is already disabled */</span><br><span>        if (config->VtdDisable)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30216">change 30216</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30216"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82 </div>
<div style="display:none"> Gerrit-Change-Number: 30216 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Nick Vaccaro <nvaccaro@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>