<p><a href="https://review.coreboot.org/c/coreboot/+/30312">View Change</a></p><p>59 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c">File src/mainboard/cmr/cmedrobo/irq_tables.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@34">Patch Set #1, Line 34:</a> <code style="font-family:monospace,monospace">#define PIRQ_HEADER_SIZE 32</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no space before tabs</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@35">Patch Set #1, Line 35:</a> <code style="font-family:monospace,monospace">#define IRQ_INFO_SIZE 16</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no space before tabs</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@40">Patch Set #1, Line 40:</a> <code style="font-family:monospace,monospace"> PIRQ_HEADER_SIZE + (IRQ_INFO_SIZE * CONFIG_IRQ_SLOT_COUNT), /* u16 size */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@50">Patch Set #1, Line 50:</a> <code style="font-family:monospace,monospace"> /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@51">Patch Set #1, Line 51:</a> <code style="font-family:monospace,monospace"> {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // GFX INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@51">Patch Set #1, Line 51:</a> <code style="font-family:monospace,monospace"> {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // GFX INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@51">Patch Set #1, Line 51:</a> <code style="font-family:monospace,monospace"> {0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // GFX INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@52">Patch Set #1, Line 52:</a> <code style="font-family:monospace,monospace"> {0x00,(0x12 << 3)|0x0, {{PIRQC, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SD INTA-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@52">Patch Set #1, Line 52:</a> <code style="font-family:monospace,monospace"> {0x00,(0x12 << 3)|0x0, {{PIRQC, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SD INTA-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@52">Patch Set #1, Line 52:</a> <code style="font-family:monospace,monospace"> {0x00,(0x12 << 3)|0x0, {{PIRQC, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SD INTA-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@53">Patch Set #1, Line 53:</a> <code style="font-family:monospace,monospace"> {0x00,(0x13 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SATA INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@53">Patch Set #1, Line 53:</a> <code style="font-family:monospace,monospace"> {0x00,(0x13 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SATA INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@53">Patch Set #1, Line 53:</a> <code style="font-family:monospace,monospace"> {0x00,(0x13 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // SATA INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@54">Patch Set #1, Line 54:</a> <code style="font-family:monospace,monospace"> {0x00,(0x15 << 3)|0x0, {{PIRQF, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPE INTA-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@54">Patch Set #1, Line 54:</a> <code style="font-family:monospace,monospace"> {0x00,(0x15 << 3)|0x0, {{PIRQF, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPE INTA-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@54">Patch Set #1, Line 54:</a> <code style="font-family:monospace,monospace"> {0x00,(0x15 << 3)|0x0, {{PIRQF, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPE INTA-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@55">Patch Set #1, Line 55:</a> <code style="font-family:monospace,monospace"> {0x00,(0x18 << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQA, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQC, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQA, INTC-PIRQD, INTD-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@55">Patch Set #1, Line 55:</a> <code style="font-family:monospace,monospace"> {0x00,(0x18 << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQA, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQC, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQA, INTC-PIRQD, INTD-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@55">Patch Set #1, Line 55:</a> <code style="font-family:monospace,monospace"> {0x00,(0x18 << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQA, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQC, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQA, INTC-PIRQD, INTD-PIRQC</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@56">Patch Set #1, Line 56:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1b << 3)|0x0, {{PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // HDA INTA-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@56">Patch Set #1, Line 56:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1b << 3)|0x0, {{PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // HDA INTA-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@56">Patch Set #1, Line 56:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1b << 3)|0x0, {{PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // HDA INTA-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@57">Patch Set #1, Line 57:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1c << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@57">Patch Set #1, Line 57:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1c << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@57">Patch Set #1, Line 57:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1c << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@58">Patch Set #1, Line 58:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1d << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // EHCI INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@58">Patch Set #1, Line 58:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1d << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // EHCI INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@58">Patch Set #1, Line 58:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1d << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // EHCI INTA-PIRQD</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@59">Patch Set #1, Line 59:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1e << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQD, INTC-PIRQE, INTD-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@59">Patch Set #1, Line 59:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1e << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQD, INTC-PIRQE, INTD-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@59">Patch Set #1, Line 59:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1e << 3)|0x0, {{PIRQB, PCI_IRQS}, {PIRQD, PCI_IRQS}, {PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}}, 0x0, 0x0}, // SIO INTA-PIRQB, INTB-PIRQD, INTC-PIRQE, INTD-PIRQF</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@60">Patch Set #1, Line 60:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1f << 3)|0x0, {{0x00, PCI_IRQS}, {PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPC INTB-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@60">Patch Set #1, Line 60:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1f << 3)|0x0, {{0x00, PCI_IRQS}, {PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPC INTB-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@60">Patch Set #1, Line 60:</a> <code style="font-family:monospace,monospace"> {0x00,(0x1f << 3)|0x0, {{0x00, PCI_IRQS}, {PIRQG, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x0, 0x0}, // LPC INTB-PIRQG</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@61">Patch Set #1, Line 61:</a> <code style="font-family:monospace,monospace"> {0x04,(0x00 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x4, 0x0}, // ETH INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@61">Patch Set #1, Line 61:</a> <code style="font-family:monospace,monospace"> {0x04,(0x00 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x4, 0x0}, // ETH INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that ',' (ctx:VxV)</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@61">Patch Set #1, Line 61:</a> <code style="font-family:monospace,monospace"> {0x04,(0x00 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}, {0x00, PCI_IRQS}}, 0x4, 0x0}, // ETH INTA-PIRQA</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required after that close brace '}'</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irq_tables.c@82">Patch Set #1, Line 82:</a> <code style="font-family:monospace,monospace"> if ((sum & 0xff) != intel_routing_table_copy.checksum) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">braces {} are not necessary for single statement blocks</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irqroute.h">File src/mainboard/cmr/cmedrobo/irqroute.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irqroute.h@48">Patch Set #1, Line 48:</a> <code style="font-family:monospace,monospace">#define PCI_DEV_PIRQ_ROUTES \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Macros with complex values should be enclosed in parentheses</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/irqroute.h@72">Patch Set #1, Line 72:</a> <code style="font-family:monospace,monospace">#define PIRQ_PIC_ROUTES \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">Macros with complex values should be enclosed in parentheses</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c">File src/mainboard/cmr/cmedrobo/mptable.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@47">Patch Set #1, Line 47:</a> <code style="font-family:monospace,monospace">#define IO_LOCAL_INT(type, intr, apicid, pin) \</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">macros should not use a trailing semicolon</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@53">Patch Set #1, Line 53:</a> <code style="font-family:monospace,monospace"> smp_write_pci_intsrc(mc, mp_INT, (bus), (dev), (pin), ioapic_id, (line))</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@89">Patch Set #1, Line 89:</a> <code style="font-family:monospace,monospace"> </code></p><p style="white-space: pre-wrap; word-wrap: break-word;">trailing whitespace</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@89">Patch Set #1, Line 89:</a> <code style="font-family:monospace,monospace"> </code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no spaces at the start of a line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@135">Patch Set #1, Line 135:</a> <code style="font-family:monospace,monospace"> * Bits 2-6: Originating PCI Device Number (Not its parent bridge device number)</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@138">Patch Set #1, Line 138:</a> <code style="font-family:monospace,monospace"> for(dev = all_devices; dev; dev = dev->next) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required before the open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@156">Patch Set #1, Line 156:</a> <code style="font-family:monospace,monospace"> if(PCI_IRQ(devn, (intpin - 1)) == existing_pci_entries[i]) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@156">Patch Set #1, Line 156:</a> <code style="font-family:monospace,monospace"> if(PCI_IRQ(devn, (intpin - 1)) == existing_pci_entries[i]) {</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">space required before the open parenthesis '('</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/mptable.c@174">Patch Set #1, Line 174:</a> <code style="font-family:monospace,monospace"> existing_pci_entries[i] = PCI_IRQ(devn, (intpin - 1));</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c">File src/mainboard/cmr/cmedrobo/romstage.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@45">Patch Set #1, Line 45:</a> <code style="font-family:monospace,monospace"> </code></p><p style="white-space: pre-wrap; word-wrap: break-word;">trailing whitespace</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@45">Patch Set #1, Line 45:</a> <code style="font-family:monospace,monospace"> </code></p><p style="white-space: pre-wrap; word-wrap: break-word;">please, no spaces at the start of a line</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@75">Patch Set #1, Line 75:</a> <code style="font-family:monospace,monospace"> .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@79">Patch Set #1, Line 79:</a> <code style="font-family:monospace,monospace"> .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@80">Patch Set #1, Line 80:</a> <code style="font-family:monospace,monospace"> .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@83">Patch Set #1, Line 83:</a> <code style="font-family:monospace,monospace"> .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@94">Patch Set #1, Line 94:</a> <code style="font-family:monospace,monospace"> .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@98">Patch Set #1, Line 98:</a> <code style="font-family:monospace,monospace"> .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@99">Patch Set #1, Line 99:</a> <code style="font-family:monospace,monospace"> .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30312/1/src/mainboard/cmr/cmedrobo/romstage.c@102">Patch Set #1, Line 102:</a> <code style="font-family:monospace,monospace"> .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */</code></p><p style="white-space: pre-wrap; word-wrap: break-word;">line over 80 characters</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30312">change 30312</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30312"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I40de818d85a15e6515fe6585f9f8c07336f17242 </div>
<div style="display:none"> Gerrit-Change-Number: 30312 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Michał Żygowski <michal.zygowski@3mdeb.com> </div>
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<div style="display:none"> Gerrit-Comment-Date: Wed, 19 Dec 2018 14:52:37 +0000 </div>
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