<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30288">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel: Standardize names of common MSR<br><br>Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/apollolake/pmutil.c<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/broadwell/smmrelocate.c<br>M src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/common/block/sgx/sgx.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/smmrelocate.c<br>M src/soc/intel/skylake/cpu.c<br>11 files changed, 31 insertions(+), 31 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/30288/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c</span><br><span>index 05590bd..c36d84d 100644</span><br><span>--- a/src/soc/intel/apollolake/pmutil.c</span><br><span>+++ b/src/soc/intel/apollolake/pmutil.c</span><br><span>@@ -210,7 +210,7 @@</span><br><span> msr.hi = (3579545ULL << 32) / CTC_FREQ;</span><br><span> /* Set PM1 timer IO port and enable */</span><br><span> msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_EMULATE_PM_TMR, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_EMULATE_PM_TIMER, msr);</span><br><span> }</span><br><span> </span><br><span> static int rtc_failed(uint32_t gen_pmcon1)</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ec8f7f3..957b978 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -623,7 +623,7 @@</span><br><span> int num_threads;</span><br><span> int num_cores;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(CORE_THREAD_COUNT_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_CORE_THREAD_COUNT);</span><br><span> num_threads = (msr.lo >> 0) & 0xffff;</span><br><span> num_cores = (msr.lo >> 16) & 0xffff;</span><br><span> printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index f791bdd..6b72266 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #define _BROADWELL_MSR_H_</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -33,12 +33,12 @@</span><br><span> #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span style="color: hsl(0, 100%, 40%);">-#define EMRRphysBase_MSR 0x1f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define EMRRphysMask_MSR 0x1f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_BASE 0x1f4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_MASK 0x1f5</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define UNCORE_EMRRphysBase_MSR 0x2f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define UNCORE_EMRRphysMask_MSR 0x2f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>index 5e95bb4..49b8554 100644</span><br><span>--- a/src/soc/intel/broadwell/smmrelocate.c</span><br><span>+++ b/src/soc/intel/broadwell/smmrelocate.c</span><br><span>@@ -45,8 +45,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->emrr_base.lo, relo_params->emrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(EMRRphysBase_MSR, relo_params->emrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->emrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->emrr_mask);</span><br><span> }</span><br><span> </span><br><span> static inline void write_uncore_emrr(struct smm_relocation_params *relo_params)</span><br><span>@@ -55,8 +55,8 @@</span><br><span> "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->uncore_emrr_base.lo,</span><br><span> relo_params->uncore_emrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask);</span><br><span> }</span><br><span> </span><br><span> static void update_save_state(int cpu, uintptr_t curr_smbase,</span><br><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index fe34d05..9601863 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -185,7 +185,7 @@</span><br><span> /* Set PM1 timer IO port and enable*/</span><br><span> msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |</span><br><span> EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_EMULATE_PM_TMR, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_EMULATE_PM_TIMER, msr);</span><br><span> }</span><br><span> </span><br><span> /* All CPUs including BSP will run the following function. */</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index 622eb07..6fdf26e 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -33,7 +33,7 @@</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_IA_UNTRUSTED (1 << 6)</span><br><span> #define FLUSH_DL1_L2 (1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_EMULATE_PM_TMR 0x121</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_EMULATE_PM_TIMER 0x121</span><br><span> #define EMULATE_DELAY_OFFSET_VALUE 20</span><br><span> #define EMULATE_PM_TMR_EN (1 << 16)</span><br><span> #define EMULATE_DELAY_VALUE 0x13</span><br><span>@@ -60,8 +60,8 @@</span><br><span> #define MISC_PWR_MGMT_ISST_EN_INT (1 << 7)</span><br><span> #define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12)</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRMRR_PHYS_BASE_MSR 0x1f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRMRR_PHYS_MASK_MSR 0x1f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_BASE 0x1f4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_MASK 0x1f5</span><br><span> #define PRMRR_PHYS_MASK_LOCK (1 << 10)</span><br><span> #define PRMRR_PHYS_MASK_VALID (1 << 11)</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span>diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>index 6050dec..3a4a533 100644</span><br><span>--- a/src/soc/intel/common/block/sgx/sgx.c</span><br><span>+++ b/src/soc/intel/common/block/sgx/sgx.c</span><br><span>@@ -83,7 +83,7 @@</span><br><span> if (!soc_sgx_enabled() || !is_sgx_supported())</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(PRMRR_PHYS_MASK_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PRMRR_PHYS_MASK);</span><br><span> /* If it is locked don't attempt to write PRMRR MSRs. */</span><br><span> if (msr.lo & PRMRR_PHYS_MASK_LOCK)</span><br><span> return;</span><br><span>@@ -109,19 +109,19 @@</span><br><span> * - Clear the valid bit in PRMRR mask MSR</span><br><span> * - Lock PRMRR MASK MSR */</span><br><span> prmrr_base.data32.lo |= MTRR_TYPE_WRBACK;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(PRMRR_PHYS_BASE_MSR, (msr_t) {.lo = prmrr_base.data32.lo,</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_BASE, (msr_t) {.lo = prmrr_base.data32.lo,</span><br><span> .hi = prmrr_base.data32.hi});</span><br><span> prmrr_mask.data32.lo &= ~PRMRR_PHYS_MASK_VALID;</span><br><span> prmrr_mask.data32.lo |= PRMRR_PHYS_MASK_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(PRMRR_PHYS_MASK_MSR, (msr_t) {.lo = prmrr_mask.data32.lo,</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_MASK, (msr_t) {.lo = prmrr_mask.data32.lo,</span><br><span> .hi = prmrr_mask.data32.hi});</span><br><span> }</span><br><span> </span><br><span> static int is_prmrr_set(void)</span><br><span> {</span><br><span> msr_t prmrr_base, prmrr_mask;</span><br><span style="color: hsl(0, 100%, 40%);">- prmrr_base = rdmsr(PRMRR_PHYS_BASE_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">- prmrr_mask = rdmsr(PRMRR_PHYS_MASK_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_base = rdmsr(MSR_PRMRR_PHYS_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ prmrr_mask = rdmsr(MSR_PRMRR_PHYS_MASK);</span><br><span> </span><br><span> /* If PRMRR base is zero and PRMRR mask is locked</span><br><span> * then PRMRR is not set */</span><br><span>@@ -191,7 +191,7 @@</span><br><span> static int is_prmrr_approved(void)</span><br><span> {</span><br><span> msr_t msr;</span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(PRMRR_PHYS_MASK_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PRMRR_PHYS_MASK);</span><br><span> if (msr.lo & PRMRR_PHYS_MASK_VALID) {</span><br><span> printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");</span><br><span> return 1;</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index c2c6c4d..165856f 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> #define _DENVERTON_NS_MSR_H_</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span style="color: hsl(0, 100%, 40%);">-#define CORE_THREAD_COUNT_MSR 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span>@@ -36,11 +36,11 @@</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define EMRR_PHYS_BASE_MSR 0x1f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define EMRR_PHYS_MASK_MSR 0x1f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_MASK 0x1f5</span><br><span> #define MSR_POWER_CTL 0x1fc</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index ed42fdf..e4b8c50 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -35,7 +35,7 @@</span><br><span> /* MTRR_CAP_MSR bits */</span><br><span> #define SMRR_SUPPORTED (1 << 11)</span><br><span> #define PRMRR_SUPPORTED (1 << 12)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRMRRphysBase_MSR 0x1f4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PRMRRphysMask_MSR 0x1f5</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_BASE 0x1f4</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PRMRR_PHYS_MASK 0x1f5</span><br><span> </span><br><span> #endif /* _SOC_MSR_H_ */</span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>index c8a9e00..f8f98c2 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c</span><br><span>@@ -46,8 +46,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",</span><br><span> relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(PRMRRphysBase_MSR, relo_params->prmrr_base);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(PRMRRphysMask_MSR, relo_params->prmrr_mask);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);</span><br><span> }</span><br><span> </span><br><span> static void update_save_state(int cpu, uintptr_t curr_smbase,</span><br><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 9a7315f..c3cb999 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -421,7 +421,7 @@</span><br><span> /* Set PM1 timer IO port and enable*/</span><br><span> msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |</span><br><span> EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_EMULATE_PM_TMR, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_EMULATE_PM_TIMER, msr);</span><br><span> }</span><br><span> </span><br><span> /* All CPUs including BSP will run the following function. */</span><br><span>@@ -529,7 +529,7 @@</span><br><span> * be reloaded after the core PRMRR MSRs are programmed.</span><br><span> */</span><br><span> msr1 = rdmsr(MTRR_CAP_MSR);</span><br><span style="color: hsl(0, 100%, 40%);">- msr2 = rdmsr(PRMRR_PHYS_BASE_MSR);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);</span><br><span> if (msr2.lo && (current_patch_id == new_patch_id - 1))</span><br><span> return 0;</span><br><span> else</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30288">change 30288</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30288"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba </div>
<div style="display:none"> Gerrit-Change-Number: 30288 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>