<p>Shelley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30296">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/hatch: Fixes to initial hatch mainboard checkin<br><br>Incorporating some feedback to initial hatch mainboard checking<br>(CL:30169) that came in after the CL merged.<br><br>BUG=b:20914069<br>BRANCH=None<br>TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v<br><br>Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8<br>Signed-off-by: Shelley Chen <shchen@google.com><br>---<br>M src/mainboard/google/hatch/Kconfig<br>M src/mainboard/google/hatch/chromeos.c<br>M src/mainboard/google/hatch/chromeos.fmd<br>M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h<br>D src/mainboard/google/hatch/variants/hatch/overridetree.cb<br>5 files changed, 11 insertions(+), 95 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/30296/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig</span><br><span>index 19230f7..cb36adf 100644</span><br><span>--- a/src/mainboard/google/hatch/Kconfig</span><br><span>+++ b/src/mainboard/google/hatch/Kconfig</span><br><span>@@ -2,9 +2,6 @@</span><br><span> config BOARD_GOOGLE_BASEBOARD_HATCH</span><br><span> def_bool n</span><br><span> select BOARD_ROMSIZE_KB_32768</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_GENERIC</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_I2C_HID</span><br><span style="color: hsl(0, 100%, 40%);">- select DRIVERS_SPI_ACPI</span><br><span> select EC_GOOGLE_CHROMEEC</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span>@@ -23,6 +20,10 @@</span><br><span> select GBB_FLAG_FORCE_DEV_BOOT_USB</span><br><span> select GBB_FLAG_FORCE_DEV_BOOT_LEGACY</span><br><span> select GBB_FLAG_FORCE_MANUAL_RECOVERY</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_GOOGLE_CHROMEEC_SWITCHES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAS_RECOVERY_MRC_CACHE</span><br><span style="color: hsl(120, 100%, 40%);">+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_LID_SWITCH</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span>@@ -71,10 +72,6 @@</span><br><span> int</span><br><span> default 8</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config OVERRIDE_DEVICETREE</span><br><span style="color: hsl(0, 100%, 40%);">- string</span><br><span style="color: hsl(0, 100%, 40%);">- default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config TPM_TIS_ACPI_INTERRUPT</span><br><span> int</span><br><span> default 53 # GPE0_DW1_21 (GPP_C21)</span><br><span>diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c</span><br><span>index 36fba45..fa54148 100644</span><br><span>--- a/src/mainboard/google/hatch/chromeos.c</span><br><span>+++ b/src/mainboard/google/hatch/chromeos.c</span><br><span>@@ -29,29 +29,15 @@</span><br><span> {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},</span><br><span> {-1, ACTIVE_HIGH, 0, "power"},</span><br><span> {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},</span><br><span style="color: hsl(0, 100%, 40%);">- {-1, ACTIVE_HIGH, 0, "EC in RW"},</span><br><span style="color: hsl(120, 100%, 40%);">+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),</span><br><span style="color: hsl(120, 100%, 40%);">+ "EC in RW"},</span><br><span> };</span><br><span> lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int cros_get_gpio_value(int type)</span><br><span style="color: hsl(120, 100%, 40%);">+int get_write_protect_state(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const struct cros_gpio *cros_gpios;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t i, num_gpios = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- cros_gpios = variant_cros_gpios(&num_gpios);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < num_gpios; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- const struct cros_gpio *gpio = &cros_gpios[i];</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpio->type == type) {</span><br><span style="color: hsl(0, 100%, 40%);">- int state = gpio_get(gpio->gpio_num);</span><br><span style="color: hsl(0, 100%, 40%);">- if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)</span><br><span style="color: hsl(0, 100%, 40%);">- return !state;</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- return state;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_get(GPIO_PCH_WP);</span><br><span> }</span><br><span> </span><br><span> void mainboard_chromeos_acpi_generate(void)</span><br><span>@@ -63,18 +49,3 @@</span><br><span> </span><br><span> chromeos_acpi_gpio_generate(cros_gpios, num_gpios);</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int get_write_protect_state(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return cros_get_gpio_value(CROS_GPIO_WP);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int get_recovery_mode_switch(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return cros_get_gpio_value(CROS_GPIO_REC);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int get_lid_switch(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd</span><br><span>index 6631769..9c7cc40 100644</span><br><span>--- a/src/mainboard/google/hatch/chromeos.fmd</span><br><span>+++ b/src/mainboard/google/hatch/chromeos.fmd</span><br><span>@@ -1,8 +1,6 @@</span><br><span> FLASH@0xfe000000 0x2000000 {</span><br><span> SI_ALL@0x0 0x1000000 {</span><br><span> SI_DESC@0x0 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- SI_EC@0x1000 0x100000</span><br><span style="color: hsl(0, 100%, 40%);">- SI_GBE@0x101000 0x2000</span><br><span> SI_ME@0x103000 0xefd000</span><br><span> }</span><br><span> SI_BIOS@0x1000000 0x1000000 {</span><br><span>@@ -29,7 +27,6 @@</span><br><span> RW_VPD@0x28000 0x2000</span><br><span> RW_NVRAM@0x2a000 0x6000</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- CONSOLE@0x530000 0x20000</span><br><span> RW_LEGACY(CBFS)@0x550000 0x6b0000</span><br><span> WP_RO@0xc00000 0x400000 {</span><br><span> RO_VPD@0x0 0x4000</span><br><span>diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>index 3878029..92501be 100644</span><br><span>--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h</span><br><span>@@ -24,6 +24,9 @@</span><br><span> #define GPIO_MEM_CONFIG_2 GPP_F11</span><br><span> #define GPIO_MEM_CONFIG_3 GPP_F22</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_EC_IN_RW GPP_C22</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_C20</span><br><span> </span><br><span> /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span> #define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span>diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb</span><br><span>deleted file mode 100644</span><br><span>index 88df092..0000000</span><br><span>--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb</span><br><span>+++ /dev/null</span><br><span>@@ -1,52 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-chip soc/intel/cannonlake</span><br><span style="color: hsl(0, 100%, 40%);">- device domain 0 on</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 00.0 off end # Host Bridge</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 02.0 off end # Integrated Graphics Device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 04.0 off end # SA Thermal device</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.0 off end # Thermal Subsystem</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.5 off end # UFS SCS</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 12.6 off end # GSPI #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 off end # USB xHCI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.5 off end # SDCard</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.0 off end # I2C #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.1 off end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.0 off end # Management Engine Interface 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 16.5 off end # Management Engine Interface 4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 17.0 off end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 off end # I2C #4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.2 off end # UART #2</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1a.0 off end # eMMC</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.0 off end # PCI Express Port 1 (USB)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.1 off end # PCI Express Port 2 (USB)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.2 off end # PCI Express Port 3 (USB)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.3 off end # PCI Express Port 4 (USB)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.4 off end # PCI Express Port 5 (USB)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.4 off end # PCI Express Port 13 (x4)</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.0 off end # UART #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.2 off end # GSPI #0</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.0 off end # LPC/eSPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.1 off end # P2SB</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.2 off end # Power Management Controller</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.3 off end # Intel HDA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.4 off end # SMBus</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.5 off end # PCH SPI</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1f.6 off end # GbE</span><br><span style="color: hsl(0, 100%, 40%);">- end</span><br><span style="color: hsl(0, 100%, 40%);">-end</span><br><span></span><br></pre><p>To view, visit <a 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 </div>
<div style="display:none"> Gerrit-Change-Number: 30296 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>