<p><a href="https://review.coreboot.org/c/coreboot/+/30225">View Change</a></p><p>5 comments:</p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30225/1//COMMIT_MSG">Commit Message:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30225/1//COMMIT_MSG@14">Patch Set #1, Line 14:</a> <code style="font-family:monospace,monospace">second time). This might save up to 100 milliseconds (exact value TBD).</code></p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;">I agree with Nico. It's not like we'd want to wait in coreboot if the reset hasn't finished. […]</blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">Ok, will remove ramstage section.</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30225/1/src/drivers/emmc/emmc_rom.c">File src/drivers/emmc/emmc_rom.c:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30225/1/src/drivers/emmc/emmc_rom.c@40">Patch Set #1, Line 40:</a> <code style="font-family:monospace,monospace"> byte = 0; /* preclear */</code></p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;">You mean the assignment in the next line might fail? wouldn't that violate C?</blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">I was thinking more in the sense of a HW failure... butt that would probably be caught by EMMC_STATUS_INVALID_ADDR. Will remove.</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30225/1/src/drivers/emmc/emmc_rom.c@43">Patch Set #1, Line 43:</a> <code style="font-family:monospace,monospace"> pinfo->status = EMMC_CONFIRMED_RESET_ACCEPTED;</code></p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;">Can you point me to documentation / a datasheet where this behaviour […]</blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">It's not a public datasheet. And it's the reason why this code is being implemented... depthcharge can't do anything until the bit is cleared. So that depthcharge don't have to wait.</p></li></ul></li><li style="margin: 0; padding: 0;"><p><a href="https://review.coreboot.org/#/c/30225/1/src/include/device/emmc.h">File src/include/device/emmc.h:</a></p><ul style="list-style: none; padding: 0;"><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30225/1/src/include/device/emmc.h@23">Patch Set #1, Line 23:</a> <code style="font-family:monospace,monospace">#define EMMC_RESET_COMPLETED 4</code></p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;">AFAICS, all you need to do in coreboot is to set EMMC_RESET_ALL and notify […]</blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">Ok, I started of from a wrong idea... I'll only send the reset and have payload check it.</p></li><li style="margin: 0; padding: 0 0 0 16px;"><p style="margin-bottom: 4px;"><a href="https://review.coreboot.org/#/c/30225/1/src/include/device/emmc.h@51">Patch Set #1, Line 51:</a> <code style="font-family:monospace,monospace"> */</code></p><p><blockquote style="border-left: 1px solid #aaa; margin: 10px 0; padding: 0 10px;">Why should other code use the same cbmem id? It seems to me you are extending […]</blockquote></p><p style="white-space: pre-wrap; word-wrap: break-word;">Basically because Intel was already defining (though not yet merged) the same cbmemid and I thought it would be wrong to have 2 cbmemid for the same purpose. As I did not know what Intel is planing it to, I created a method to differentiate between Intel's one and mine. Intel's code is going after sending CMD0 and CMD1, so it's cbmem use will probably be different.</p></li></ul></li></ul><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30225">change 30225</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30225"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I4bb55fde23e3b70da1cca76e5672e880317b8bd2 </div>
<div style="display:none"> Gerrit-Change-Number: 30225 </div>
<div style="display:none"> Gerrit-PatchSet: 3 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: Daniel Kurtz <djkurtz@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
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<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>
<div style="display:none"> Gerrit-CC: Nico Huber <nico.h@gmx.de> </div>
<div style="display:none"> Gerrit-Comment-Date: Tue, 18 Dec 2018 18:10:13 +0000 </div>
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