<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30276">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Add GPIO group pad base for ACPI<br><br>commit msg copied from<br>commit id: 64c9f1584c63403207ee85b1d54ca594ae1fbedf<br><br>The GPIO drivers in Windows and Linux for the Icelake CPU<br>have a sparse GPIO map and do not allocate pins contiguously.<br>Each GPIO group is allocated as 32 pads regardless of whether<br>the hardware actually has that many in the group.<br><br>It appears this originated with a bug in Windows/UEFI and was<br>carried over to Linux in order to work with existing firmware:<br>https://lore.kernel.org/patchwork/patch/855244/<br><br>In order to support using ACPI GPIOs it is necessary for coreboot<br>to be compatible with this implementation. The GPIO groups that<br>are usable by the OS are declared with a pad base which is then<br>used to compute the number for ACPI GPIOs.<br><br>Change-Id: I94fafd8af13cf229f5c467de5179aed021465739<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/icelake/gpio.c<br>1 file changed, 24 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30276/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c</span><br><span>index b244437..5362005 100644</span><br><span>--- a/src/soc/intel/icelake/gpio.c</span><br><span>+++ b/src/soc/intel/icelake/gpio.c</span><br><span>@@ -32,34 +32,48 @@</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The GPIO driver for Icelake on Windows/Linux expects 32 GPIOs per pad</span><br><span style="color: hsl(120, 100%, 40%);">+ * group, regardless of whether or not there is a physical pad for each</span><br><span style="color: hsl(120, 100%, 40%);">+ * exposed GPIO number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This results in the OS having a sparse GPIO map, and devices that need</span><br><span style="color: hsl(120, 100%, 40%);">+ * to export an ACPI GPIO must use the OS expected number.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Not all pins are usable as GPIO and those groups do not have a pad base.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This layout matches the Linux kernel pinctrl map for CNL-LP at:</span><br><span style="color: hsl(120, 100%, 40%);">+ * linux/drivers/pinctrl/intel/pinctrl-icelake.c</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> static const struct pad_group icl_community0_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_G0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_G0, GPP_B0, GPP_B23), /* GPP_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32), /* GPP_B */</span><br><span> INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_G0, GPP_A0, GPP_A23), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64), /* GPP_A */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group icl_community1_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_H0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_H0, GPP_D0, GPIO_RSVD_2), /* GPP_D */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_H0, GPP_F0, GPP_F19), /* GPP_F */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160), /* GPP_F */</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* This community is not visible to the OS */</span><br><span> static const struct pad_group icl_community2_groups[] = {</span><br><span> INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */</span><br><span> };</span><br><span> </span><br><span> </span><br><span> static const struct pad_group icl_community4_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */</span><br><span> INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),</span><br><span> };</span><br><span> </span><br><span> </span><br><span> static const struct pad_group icl_community5_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_S0, GPP_S7), /* GPP_S */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_community icl_communities[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30276">change 30276</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I94fafd8af13cf229f5c467de5179aed021465739 </div>
<div style="display:none"> Gerrit-Change-Number: 30276 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>